Reliability issues of low-cost overmolded flip-chip packages

A significant need exists for the determination of critical stress characteristics within the low-cost overmolded flip-chip (OM-FC) packages. A systematic stress analysis is reported to investigate the OM-FC package for the optimal design of package geometries, materials combinations during the attachment, and thermal testing processes. A parametric study is conducted seeking the best package performance during the identified most stringent process which causes the largest stress within the low-cost substrate. High-stress location is predicted by finite-element analysis, and it was found that mold compound (MC) curing is the most stringent process for the reliability of substrate; higher underfill fillet, thicker die, larger die size without causing edge effect, solder mask defined structure resulted in smaller stresses in substrate. MC with lower coefficient of thermal expansion is a preferable and compliant substance that is good for using as molding and underfill material     

Reliability studies of two flip-chip BGA packages using power cycling test

Power cycling tests of the second level reliability of two flip-chip BGA packages are discussed in this paper. The first one is for a flip-chip on laminate package (FCPBGA) and the other for a flip-chip on ceramic package (FCCBGA). For the FCPBGA, test strategies will be first discussed and then focus will be given to a unique failure mode associated with this type of packages assembled back to back onto printed circuit board. Instead of anticipated failures of the corner solder joints under the die shadow, as in the case of wire-bonded packages, we found that solder joints failed first in the central region of the package and then failures of solder joints spread out in the radial direction from the center of the package. Explanation will be given to the physical mechanisms that caused this type of failure. For the FCCBGA, the improved test strategies based on what has been learned from the test of FCPBGA will be presented and focus will be given to the effect of different parameters on the second level reliability of the package. Here, because of the increased rigidity of the ceramic substrate solder joints failed as expected first at the corner(s) of the ceramic substrate. Based on the test results and the modified Coffin–Manson equation, predictions or the solder joint fatigue life will be shown.     

An improvement of thermal conductivity of underfill materials for flip-chip packages

Effective heat dissipation is crucial to enhance the performance and reliability of electronic devices. In this work, the performance of encapsulants filled with carbon fiber was studied and compared with silica filled encapsulants. Encapsulants filled with mixed combination of fillers for optimizing key properties were also investigated. The thermal and electrical conductivities were investigated and glass transition temperature (Tg), thermal expansion coefficient (TCE), and storage modulus (E') of these materials were studied with thermal analysis methods. The composites filled with both carbon fiber and silica showed an increase of thermal conductivity three to five times of that of silica filled encapsulants of the same filler loading while maintaining/enhancing major mechanical and thermal properties.     

Evaluation of die edge cracking in flip-chip PBGA packages

Increasing die size and large coefficient of thermal expansion (CTE) mismatch in flip-chip plastic ball grid array (FC-PBGA) packages have made die fracture a major failure mode during reliability testing. Most die fracture observed before was die backside vertical cracking, which was caused by excessive package bending and backside defects. However, due to die edge defects induced by the singulation process and the choice of underfill material, an increasing number of die cracks were found to initiate from die edge and propagate horizontally across the die. In order to improve package reliability and performance, die edge cracking has to be eliminated. An extensive finite element analysis was completed to investigate die edge cracking and find its solutions. A fracture mechanics approach was used to evaluate the effect of various package parameters on die edge initiated fracture. Strain energy release rate was found to be an effective technique for evaluating die edge initiated fracture from singulation-induced flaws. The impact of initial flaw size and a variety of package parameters was investigated. Unlike in die backside cracking, the dominant parameters causing die edge horizontal fracture are more closely related to local effects.     

Mechanical fatigue test method for chip/underfill delamination in flip-chip packages

Underfill resin between Si chips and printed circuit boards is useful for improving the reliability of flip-chip packages. Generally, thermal cycle tests (TCTs) are applied to electronic packages under development in order to prove their reliability. At the early stage of development, however, a more effective test method is desirable, because TCTs are time-consuming. A new mechanical fatigue test for the underfill resin in flip-chip packages, namely the four points support test method, is proposed in this paper. The validity of the mechanical test method could be verified from the results of stress analyses and experiments. Considering the chip/underfill delamination statistically based on the assumption of Markov process, it was shown that the delamination probability during cyclic loads could be estimated with equations of the displacement range and number of cycles.     

Wafer level packaging of a tape flip-chip chip scale packages

The advent of chip scale packages (CSPs) within the semiconductor community has led to the development of wafer scale assembly (WSA) or wafer level packaging (WLP) manufacturing in order to raise assembly efficiencies and lower operating costs. Texas Instruments (TI) has developed a unique WLP process for forming flip-chip, ball grid array packages. The die inputs and outputs of the TI CSP are connected through solder bumps to a polyimide film interposer. Solder balls on the other side of the interposer complete the electrical connection to a customer’s printed circuit board. A wafer-sized array of interposers designed to match the pattern of dies on a wafer is aligned and reflowed to a bumped wafer. The TI WLP process is completed by singulating the CSPs from the wafer using standard wafer saw equipment.Attachment of the interposer to the die as well as applying the die and board level solder bumps are carried out in wafer form using a new bumping technology called Tacky Dots™. Tacky Dots uses an array of sticky dots formed in a photosensitive coating laminated to a polyimide film for transferring and attaching solder spheres to semiconductor substrates. A populated film containing one solder sphere per Tacky Dot is positioned over the wafer or interposer and lowered until the spheres contact the pads. A reflow process transfers the spheres from the film to the wafer or interposer and the film is removed once the spheres have frozen.This paper illustrates the process steps and custom equipment developed for forming the TI CSP. The strategic use of finite element modeling for optimizing the design of the package is outlined. The paper concludes by summarizing the current package level reliability results.     

Calibration of electromigration reliability of flip-chip packages by electrothermal coupling analysis

Electromigration reliability of solder interconnects is dominated by current density and temperature inside the interconnects. For flip-chip packages, current densities around the regions where the traces connect a solder bump increase significantly due to the differences in feature sizes and electric resistivities between the solder bump and its adjacent traces. This current-crowding effect along with induced Joule heating accelerates electromigration failures. In this paper, the effects of current crowding and Joule heating in a flip-chip package are examined and quantified by three-dimensional electrothermal coupling analysis. We apply a volumetric averaging technique to cope with the current-crowding singularity. The volumetrically averaged current density and the maximum temperature in a solder bump are integrated into Black’s equation to calibrate the experimental electromigration fatigue lives. An erratum to this article is available at .     

Reliability modelling for packages in flexible end-products

Flexible end-products like banking cards and wearable electronics are about to pervade our lives massively. Due to the fact that flexibility is a must, reliability problems are expected due to the mechanical handling loading conditions the end-product is subjected. This paper presents our effort to predict reliability problems for packages in flexible end-products. Current field returns indicate that mechanical loadings are causing crack failures in dies and packages. Both parametric 2D and 3D Finite Element models are constructed to analyse the impact of such loadings to the stress levels in the constituents. The results gain a better understanding of reliability issues and, where possible, give suggestions for preventing such issues. With the aid of the simulation results mechanical test methodologies can be designed suitable as to insure a given lifetime statement.     

Adhesion issues in flip-chip on organic modules

Flip chip attach on organic carriers is a novel electronic packaging assembly method which provides advantages of high input/output (I/O) counts, electrical performance and thermal dissipation. In this structure, the flip chip device is attached to organic laminate with predeposited eutectic solder. Mechanical coupling of the chip and the laminate is done via underfill encapsulant materials. As the chip size increases, the thermal mismatch between silicon and its organic carrier becomes greater. Adhesion becomes an important factor since the C4 joints fail quickly if delamination of the underfill from either chip or the solder mask interface occurs. Newly developed underfills have been studied to examine their properties, including interfacial adhesion strength, flow characteristics, void formation and cure kinetics. This paper will describe basic investigations into the properties of these underfills and also how these properties related to the overall development process. In addition, experiments were performed to determine the effects on adhesion degradation of flip chip assembly processes and materials such as IR reflow profile, flux quantity and residues. Surface treatment of both the chip and the laminate prior to encapsulation were studied to enhance underfill adhesion. Accelerated thermal cycling and highly accelerated stress testing (HAST) were conducted to compare various underfill properties and reliability responses     

Evaluation of solder joint reliability in flip-chip packages during accelerated testing

The microstructural investigation and thermomechanical reliability evaluation of the Sn-3.0Ag-0.5Cu solder bumped flip-chip package were carried out during the thermal shock test of the package. In the initial reaction, the reaction product between the solder and Cu mini bump of chip side was Cu₆Sn₅ intermetallic compound (IMC) layer, while the two phases which were (Cu,Ni)₆Sn₅ and (Ni,Cu)₃Sn₄ were formed between the solder and electroless Ni-P layer of the package side. The cracks occurred at the corner solder joints after the thermal shocks of 400 cycles. The primary failure mechanism of the solder joints in this type of package was confirmed to be thermally-activated solder fatigue failure. The premature brittle interfacial failure sometimes occurred in the package side, but nearly all of the failed packages showed the occurrence of the typical fatigue cracks. The finite-element analyses were conducted to interpret the failure mechanisms of the packages, and revealed that the cracks were induced by the accumulation of the plastic work and viscoplastic shear strains.     

Electrothermal coupling analysis of current crowding and Joule heating in flip-chip packages

Solder bumps serve as electrical paths as well as structural support in a flip-chip package assembly. Owing to the differences of feature sizes and electric resistivities between a solder bump and its adjacent traces, current densities around the regions where traces connect the solder bump increase in a significant amount. This current crowding effect along with the induced Joule heating would accelerate fatigue failure due to electromigration. In this paper we apply the three-dimensional electrothermal coupling analysis to investigate current crowding and Joule heating in a flip-chip package assembly carrying different constant electric currents under different ambient temperatures. Experiments are conducted to calibrate temperature-dependent electric resistivities of solder alloy, Al trace, and Cu trace, and to verify the numerical model by comparing calculated and measured maximum temperatures on the die surface. Through the electrothermal coupling analysis, effects of current crowding and Joule heating induced by different solder bump structures are examined and compared.     

Improved underfill adhesion in flip-chip packages by means of ultraviolet light/ozone treatment

The interfacial adhesion between the epoxy-based soldermask and underfill resin is successfully improved by means of ultraviolet light/ozone (UV/O/sub 3/) treatment. There is an optimized treatment condition that can impart the highest interfacial bond quality. The underlying mechanisms are evaluated based on several techniques, including X-ray photoelectron spectroscopy (XPS), contact angle measurement and nanoindentation of the UV/O/sub 3/ treated soldermask surface. Functionally similar changes in chemical element, wettability, and elastic modulus are identified of the substrate with respect to treatment time, which are also correlated to the improvement of interfacial bond strength. In particular, there is a linear relationship between the weighted dipole moment (obtained from the XPS analysis) and the surface polarity (calculated from the contact angle measurements) of the treated surface, confirming that the same conclusion can be drawn from the two different techniques. The UV/O/sub 3/ treatment is proven to be efficient in retaining the interfacial bond quality even after hygrothermal ageing.     

Interfacial delamination and fatigue life estimation of 3D solder bumps in flip-chip packages

Detailed three-dimensional finite element analysis was carried out for area-array solder-bumped flip-chip packages. The analysis enabled determinations of accurate three-dimensional effects on stress distributions as well as local fracture behaviors under thermal load. The 3D analysis also estimated thermal fatigue life of solder bumps. Since dimensions of various components span more than three orders of magnitude, the multi-scale finite element models were utilized to elucidate detailed deformation state near solder bumps. The global–local approach identified of critical solder bumps due to the overall deformation and investigated of interfacial delamination at microstructural level. The local model contained a single solder bump and sub-micron UBM layers. The two-step modeling approach enabled accurate fracture analysis otherwise difficult in large 3D models. Our analysis found the crack driving force and preferred delamination direction based on the 3D J-integral calculations. Shear deformations within and surrounding solder bump connectors were also investigated. The results revealed higher deformation in the 3D model than those predicted from 2D models. Additionally, the strain components were different. This has an important implication on the plastic flow characteristics during cyclic loading. Our model estimated about 25% greater steady-state shear strains in the 3D model than those in the 2D models. This result suggests a much shorter fatigue life than that based on the 2D analysis.     

Reliability issues for nano-scale CMOS dielectrics

Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues, new materials as metal gates and high-k gate dielectrics have been integrated. These new materials require that we gain understanding of the reliability physics related to these new materials (such as Vt instability, gate oxide breakdown) and that we develop high confidence-level design rules.     

Quantitative reliability analysis of flip-chip packages under thermal-cyclic loading and in consideration of parameter uncertainties

To study the quantitative reliability of electronic packages, a finite element analysis with the assumption that certain geometric parameters are random variables is carried out for a flip-chip package. The equivalent plastic strain range of the package subject to thermal-cyclic loading is obtained, and the fatigue life of the package is determined based on a modified Coffin-Manson equation. Both quantities obtained are random variables owing to the randomness or uncertainties of geometric parameters. It is found that, among different geometric parameters, the size of the solder bump affects the random fatigue life of the package the most. In the second phase of the study, a modified Coffin-Manson equation with random nature is considered. This can be achieved by assuming some parameters in the equation to be random variables. It also reflects a certain kind of uncertainty of the material property. Through mathematical derivation and numerical illustration, it is shown that the predicted fatigue lives may have different mean values and different variations, and the difference may be significant. The present study indicates that both random geometric configuration and random life prediction rule may cause the fatigue life of the package to have scattered distribution as those observed from experiments.     

Reliability of Cu wire bonds in microelectronic packages

In this study the thermo-mechanical response of 25 μm Cu wire bonds in an LQFP-EPad (Low Profile Quad Flat-Exposed Pad) package was investigated by numerical and experimental means. The aim was to develop a methodology for fast evaluation of the packages, with focus on wire bond fatigue, by combining finite element analysis (FEA) and mechanical fatigue testing. The investigations included the following steps: (i) simulation of the warpage induced displacements in the encapsulated LQFP-176-Epad package due to temperature changes, (ii) reproducing the thermally induced stresses in the wire bond loops in an unmolded (non-encapsulated) LQFP package using an accelerated multiaxial mechanical fatigue testing set-up under the displacement amplitudes determined in case (i) and determination of the loading cycles to failure (N_f), (iii) FEA of the experiments performed in (ii) based on the boundary conditions determined in (i) to calculate the states of stress and strain in the wire bonds subjected to multiaxial mechanical cyclic loading. Our investigations confirm that thermal and mechanical cyclic loading results in occurrence of high plastic strains at the heat affected zone (HAZ) above the nail-head, which may lead to fatigue failure of the wire bonds in the packages. The lifetime of wire bonds show a proportional relation between the location and angle of the wire bond to the direction of loading. The calculated accumulated plastic strain in the HAZ was correlated to the experimentally determined N_f values based on the volume weighted averaging (VWA) approached and presented in a lifetime diagram (∆ d - N_f) for reliability assessment of Cu wire bonds. The described accelerated test method could be used as a rapid qualification test for the determination of the lifetimes of wire bonds at different positions on the chip as well as for related improvements of package design.     

Solder reflow process induced residual warpage measurement and its influence on reliability of flip-chip electronic packages

To meet the future needs of high pin count and high performance, package size of flip-chip devices is constrained to become larger. In addition, to fulfill the environment issues, lead free solders will be replacing lead contained eutectic (Sn/37Pb) in near future. Thus, in this work, the effect of residual warpage and consequent residual stress on the reliability of large flip-chip using lead free solder is examined. Several effective experimental approaches to accurately measure residual warpage, using Moiré interferometry, shadow Moiré, and image processing schemes, are introduced. Moreover, geometric, process, and material parameters affecting the residual warpage during reflow process are discussed and some modifications are suggested. Finally, it is verified that it is crucial to accurately quantify and control the residual warpage in order to guarantee the overall reliability of flip-chip packages regardless of presence of underfill.     

A practical investigation on nickel plated copper heat spreader with different catalytic activation processes for flip-chip ball grid array packages

This study investigates the effects of two different catalytic activation techniques on the thermal performance of the flip-chip heat spreaders. The two activation techniques studied are thin nickel-copper strike and galvanic initiation. Thermal diffusivity and surface roughness of these heat spreaders were studied using the Nano-flash Apparatus and Infinite Focus Microscopy. High temperature storage tests were carried out to investigate the extent of intermetallic diffusion between the nickel and copper layers. The results show that heat spreaders with thin nickel-copper strike catalytic activation technique have a lower thermal diffusivity due to the low thermal conductivity of nickel-copper layer. Moreover, the nickel-copper layers grew thicker from around 0.2 μm at initial time to around 0.55 μm after high temperature storage duration of 168 h. On the other hand, heat spreaders processed using the galvanic initiation technique did not form any nickel-copper intermetallic diffusion layer. As a conclusion, the galvanic initiation technique can potentially provide better thermal performance for heat spreaders used in semiconductor packages.