Effects of annealing on charge in HfO/sub 2/ gate stacks

This letter presents a systematic investigation of charge in HfO/sub 2/ gate stacks. Assuming that the majority of charge is associated with the stack interfaces, it is found that the charge at the HfO/sub 2//interfacial layer (IL) interface is negative while the charge at the Si/IL interface is positive. In general, the calculated charge densities at both interfaces are of order 10/sup 12/ cm/sup -2/. A forming gas anneal (FGA) reduces the interface charge greatly at both interfaces. However, the FGA temperature does not have much effect on the charge density. The effects of post deposition anneal at various temperatures and under various atmospheres are also studied. Its found that a high temperature dilute oxidizing atmosphere anneal reduces the charge at both interfaces.     

A study on charge reduction in HfO/sub 2/ gate stacks

Charge in metal-organic chemical vapor deposition-grown HfO/sub 2/ gate stacks has been systematically studied using nMOS capacitors. It is found that, for these films, the charge in the stack is mainly concentrated at the interfaces between the layers and is negative at the HfO/sub 2//interfacial layer (IL) interface and positive at the Si/IL interface. In general, the calculated charge densities at both interfaces are of order 10/sup 12/ cm/sup -2/. A forming gas anneal (FGA) reduces both interface charge greatly. The FGA can also significantly reduce the hysteresis and interface state density. The effects of post deposition anneal at various temperatures and under various ambients have also been studied. It is found that a high-temperature dilute oxidizing ambient anneal followed by an FGA reduces the charge at both interfaces.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-K dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-K dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/ A(2-5 /spl times/ 10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8 /spl times/ 10/sup 17/ cm/sup -3/ eV/sup -1/ to 1, 3 /spl times/ 10/sup 19/ cm/sup -3/ eV/sup -1/ somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-K/gate stacks, relative comparison among them and to the Si-SiO/sub 2/ system.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.     

Modeling of tunneling currents through HfO/sub 2/ and (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks

We present a physical modeling of tunneling currents through ultrathin high-/spl kappa/ gate stacks, which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-/spl kappa/ dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO/sub 2/ with and without NH/sub 3/-based interface layers, and ALD Al/sub 2/O/sub 3/ gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks in order to project their scalability for future CMOS applications.     

ScN/sub x/ gate on atomic layer deposited HfO/sub 2/ and effect of high-pressure wet post deposition annealing

For nMOS devices with HfO/sub 2/, a metal gate with a very low workfunction is necessary. In this letter, the effective workfunction (/spl Phi//sub m,eff/) values of ScN/sub x/ gates on both SiO/sub 2/ and atomic layer deposited (ALD) HfO/sub 2/ are evaluated. The ScN/sub x//SiO/sub 2/ samples have a wide range of /spl Phi//sub m,eff/ values from /spl sim/ 3.9 to /spl sim/ 4.7 eV, and nMOS-compatible /spl Phi//sub m,eff/ values can be obtained. However, the ScN/sub x/ gates on conventional post deposition-annealed HfO/sub 2/ show a relatively narrow range of /spl Phi//sub m,eff/ values from /spl sim/ 4.5 to /spl sim/ 4.8 eV, and nMOS-compatible /spl Phi//sub m,eff/ values cannot be obtained due to the Fermi-level pinning (FLP) effect. Using high-pressure wet post deposition annealing, we could dramatically reduce the extrinsic FLP. The /spl Phi//sub m,eff/ value of /spl sim/ 4.2 eV was obtained for the ScN/sub x/ gate on the wet-treated HfO/sub 2/. Therefore, ScN/sub x/ metal gate is a good candidate for nMOS devices with ALD HfO/sub 2/.     

Evaluation of NBTI in HfO/sub 2/ gate-dielectric stacks with tungsten gates

Negative-bias temperature instability (NBTI) of the threshold voltage in ultrathin HfO/sub 2/ p-type field-effect transistors (pFET) with tungsten gates is reported. The dependence of threshold voltage, transconductance peak, and interface trap density on stress time is investigated for various negative stress voltages and temperatures. The measurements show that the threshold voltage shifts with a concomitant decrease in transconductance peak and increase in interface trap density as assessed by subthreshold slope and dc current-voltage (DCIV) method. The threshold voltage shift data are fitted with a stretched exponential equation and the fits are used for estimating lifetime. The measurements show that NBTI-related degradation in HfO/sub 2/ stacks is comparable to that observed in SiO/sub 2//poly Si pFETs.     

Charge trapping and degradation of HfO/sub 2//SiO/sub 2/ MOS gate stacks observed with enhanced CAFM

In this letter, a prototype of conductive atomic force microscope with enhanced electrical performance has been used to separately investigate the effect of the electrical stress on the SiO/sub 2/ and the HfO/sub 2/ layers of a high-/spl kappa/ gate stack. Charge trapping in HfO/sub 2/ native defects and degradation of both layers have been observed, depending on the stress level.     

Effects of thermal annealing on the charge localization characteristics of HfO2/Au/HfO2 stack

To be compatible with the mainstream nano CMOS technology and to further increase the density and to reduce power consumption of non-volatile memory, high-k dielectric will become the major technology option for next generation non-volatile memory technology. To ensure the required retention time and to maintain the scalability of floating gate memory transistor, the charge store in future memory transistor should be accompanied with the high-k insolated metal or conductive clusters, islands, or nano-particles. This work proposes a simple method to fabricate high-k isolated metal cluster array. An HfO₂/Au/HfO₂ stack was first grown by using atomic layer deposition (ALD) and thermal evaporation, respectively, for HfO₂ and Au film deposition. After a high-temperature thermal annealing, a number of HfO₂-buried Au islands with diameter of about 5 to10 nm were obtained. Capacitance–voltage (C–V) measurements show that the charge storage characteristics of the Au-embedded HfO₂ structure were affected greatly by the annealing conditions. Depending on the annealing temperature (it should be governed by thickness of Au layer also), the thermal annealing may lead to the formation of Au islands/clusters, the improvement of HfO₂ blocking property as a result of defect removal, or the deterioration of the blocking property of HfO₂ due to the crystallization of HfO₂ film. Process optimization should be conducted for further improving the charge localization characteristics.     

Characteristics of HfO/sub 2/ pMOSFET prepared by B/sub 2/H/sub 6/ plasma doping and KrF excimer laser annealing

The electrical characteristics of HfO/sub 2/ pMOSFETs prepared by B/sub 2/H/sub 6/ plasma doping and excimer laser annealing were investigated. Various metal gate electrodes were evaluated to protect the high-/spl kappa/ oxide during laser irradiation. Although the aluminum gate electrode showed superior reflectivity to the laser, the equivalent oxide thickness was increased due to the interaction between aluminum and HfO/sub 2/, which resulted in reduced capacitance. In contrast, the Al-TaN stacked gate showed good reflectivity up to laser energy of 500 mJ/cm/sup 2/ and improved capacitance was obtained compared with the Al gate. For the first time, the electrical characteristics of a HfO/sub 2/ pMOSFET with an Al-TaN gate fabricated by plasma doping and excimer laser annealing were demonstrated. It was also demonstrated that plasma doping and excimer laser annealing combined with a metal gate could be applied for high-/spl kappa/ oxide MOSFET fabrication.     

Interfacial defect states in HfO/sub 2/ and ZrO/sub 2/ nMOS capacitors

A comprehensive analysis of the bump/kink observed in the experimental capacitance-voltage (C-V) curves of HfO/sub 2/ and ZrO/sub 2/ capacitors was performed using self-consistent numerical simulations. Both HfO/sub 2/ samples grown by sputter deposition and grown by metal-organic chemical vapor deposition (MOCVD) were examined. The bumps in the C-V curves were found to be consistent with an interface state centered 0.25 eV above the valence bandedge for the sputter deposited devices, and 0.30 eV above the bandedge for the MOCVD devices. Annealing of the HfO/sub 2/ devices reduced the densities of these traps, but also increased the effective oxide thickness. Similar defect states were detected for the ZrO/sub 2/ devices centered 0.25 eV above the valence bandedge.     

Ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on surface-nitrided Ge

We have studied ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on Ge grown by ultrahigh vacuum-reactive atomic-beam deposition and ultraviolet ozone oxidation. Al/sub 2/O/sub 3/-Ge gate stack had a t/sub eq//spl sim/23 /spl Aring/, and three orders of magnitude lower leakage current compared to SiO/sub 2/. HfO/sub 2/-Ge allowed even greater scaling, achieving t/sub eq//spl sim/11 /spl Aring/ and six orders of magnitude lower leakage current compared to SiO/sub 2/. We have carried out a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectric-Ge capacitors. We show that surface nitridation is important in reducing hysteresis, interfacial layer formation and leakage current. However, surface nitridation also introduces positive trapped charges and/or dipoles at the interface, resulting in significant flatband voltage shifts, which are mitigated by post-deposition anneals.     

Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO/sub 2//metal stacks

The performance of aggressively scaled (1.4nm相似文献   

Diffusion coefficient of B in HfO/sub 2/

We implanted B ions in a 110-nm-thick HfO/sub 2/ layer, subjected the substrates to various thermal processes, and evaluated the diffusion coefficient by comparing experimental and numerical data. We found that the diffusion coefficient of B in HfO/sub 2/ is higher than that in SiO/sub 2/ by about four orders and almost the same as that in Si. Therefore, the penetration of B through this layer can be expected to be significant, making the use of a cover layer indispensable for p/sup +/ polycrystalline silicon gate devices.     

Impacts of gate electrode materials on threshold voltage (V/sub th/) instability in nMOS HfO/sub 2/ gate stacks under DC and AC stressing

Ultrathin nMOSFET hafnium oxide (HfO/sub 2/) gate stacks with TiN metal gate and poly-Si gate electrodes are compared to study the impact of the gate electrode on long term threshold instability reliability for both dc and ac stress conditions. The poly-Si/high-/spl kappa/ interface exhibits more traps due to interfacial reaction than the TiN/high-/spl kappa/ interface, resulting in significantly worse dc V/sub th/ instability. However, the V/sub th/ instability difference between these two stacks decreases and eventually diminishes as ac stress frequency increases, which suggests the top interface plays a minor role in charge trapping at high operating frequency. In addition, ac stress induced interface states (Nit) can be effectively recovered, resulting in negligible G/sub m/ degradation.     

Improvement of surface carrier mobility of HfO/sub 2/ MOSFETs by high-temperature forming gas annealing

The surface electron mobility of HfO/sub 2/ NMOSFETs with a polysilicon gate electrode was studied in terms of the effects of high-temperature forming gas (FG) annealing. The high-temperature FG annealing significantly improved the drive current or the surface electron mobility of the NMOSFETs. Improvements were also observed in the subthreshold swings and the C-V characteristics, indicating a reduction in interfacial state density (D/sub it/). The D/sub it/ reduction was quantitatively confirmed by charge pumping current measurements. The mobility enhancement was achieved without degrading the equivalent oxide thickness (EOT) or gate leakage current. Different surface preparations, such as NH/sub 3/ or NO annealing, were explored to examine their effects on the NMOSFET performance. Mobility enhancement due to high-temperature FG annealing was also observed on these samples. Whereas NH/sub 3/ surface nitridation was effective in scaling EOT, the NO-annealed sample exhibited the highest mobility. Similar improvements were also observed on HfO/sub 2/ PMOSFETs, in terms of subthreshold swings, drive current, and surface hole mobility.     

Ion implantation impurity profiles in HfO/sub 2/

We implanted B, As, and P ions in a 110-nm-thick layer of HfO/sub 2/ and extracted the parameters of a Pearson IV function. The projected range of the ion implantation was about half of that in SiO/sub 2/. Thus, when impurities were ion implanted in an Si substrate through a thin layer of HfO/sub 2/ or SiO/sub 2/, a smaller dose was retained in the substrate in the former than in the latter case. This effect was demonstrated with P-ion implantation.     

High-performance nonvolatile HfO/sub 2/ nanocrystal memory

In this letter, we demonstrate high-performance nonvolatile HfO/sub 2/ nanocrystal memory utilizing spinodal phase separation of Hf-silicate thin film by 900/spl deg/C rapid thermal annealing. With this technique, a remarkably high nanocrystal density of as high as 0.9 /spl sim/ 1.9 /spl times/ 10/sup 12/ cm/sup -2/ with an average size <10 nm can be easily achieved. Because HfO/sub 2/ nanocrystals are well embedded inside an SiO/sub 2/-rich matrix and due to their sufficiently deep energy level, we, for the first time, have demonstrated superior characteristics of the nanocrystal memories in terms of a considerably large memory window, high-speed program/erase (P/E) (1 /spl mu/s/0.1 ms), long retention time greater than 10/sup 8/ s for 10% charge loss, and excellent endurance after 10/sup 6/ P/E cycles.     

Improving channel carrier mobility and immunity to charge trapping of high-K NMOSFET by using stacked Y/sub 2/O/sub 3//HfO/sub 2/ gate dielectric

A stacked Y/sub 2/O/sub 3//HfO/sub 2/ multimetal gate dielectric with improved electron mobility and charge trapping characteristics is reported. Laminated hafnium and yttrium were sputtered on silicon followed by post-deposition anneal (PDA) in N/sub 2/ ambient. The new dielectric shows a similar scalability to HfO/sub 2/ reference. Analysis on flatband voltage shift indicates positive fixed charge induced by Y/sub 2/O/sub 3/. Excellent transistor characteristics have been demonstrated. Stacked Y/sub 2/O/sub 3//HfO/sub 2/, compared to HfO/sub 2/ reference with similar equivalent oxide thickness (EOT), shows 49% enhancement in transconductance and 65% increase in the peak electron mobility. These improvements may be attributed to better charge trapping characteristics of the multimetal dielectric.     

Threshold voltage (V/sub th/) instability in HfO/sub 2/ high-/spl kappa/ gate stacks with TiN metal gate: comparison between NH/sub 3/ and O/sub 3/ interface treatments

The impacts of O/sub 3/ or NH/sub 3/ interface treatments on the long-term V/sub th/ instability in nMOSFET HfO/sub 2/ high-/spl kappa/ gate stacks with TiN metal gate electrodes are compared. The NH/sub 3/ interface treatment is found to be beneficial to suppress the V/sub th/ shift compared to the O/sub 3/-treated samples. This is explained by an enhanced valence band electrons injection in O/sub 3/-treated samples and is experimentally confirmed through a carrier separation measurement. The dynamic stress measurement also indicates that trapped charges are more easily detrapped in NH/sub 3/-treated samples than O/sub 3/-treated samples, improving significantly the V/sub th/ stability.