A CMOS 0.25-/spl mu/m continuous-time FIR filter with 125 ps per tap delay as a fractionally spaced receiver equalizer for 1-gb/s data transmission

This paper presents a CMOS 0.25-/spl mu/m continuous-time 6-tap FIR filter that is used as a fractionally spaced receiver equalizer for 1-Gb/s data transmission. Each tap of the FIR filter delay line is realized with a second-order low-pass filter. Simulations show that the tap delay can be tuned from 100 ps to 300 ps while keeping a constant group delay within the bandwidth of 2.1 GHz and 800 MHz correspondingly. Experimental results show that the FIR filter can successfully recover a 1-Gb/s differential digital signal that has been transmitted over a 220-inch PCB trace which causes -31.48-dB attenuation at the symbol rate frequency of 1 GHz. The measured bit error rate after equalization is less than 10/sup -12/ over a 750-ps sampling range, compared to a 10/sup -2/ bit-error rate before equalization. Also presented are the measurement results comparing the horizontal and the vertical openings of the signals before and after equalization for PCB traces with different length. The chip dissipates 45 mW from a 2.5-V supply and occupies 0.33/spl times/0.27 mm/sup 2/ in a 0.25-/spl mu/m CMOS process.     

Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits

In this paper, we present integrated circuit solutions that enable high-speed data transmission over legacy systems such as short reach optics and electrical backplanes. These circuits compensate for the most critical signal impairments, intersymbol interference and crosstalk. The finite impulse response (FIR) filter is the cornerstone of our architecture, and in this study we present 5- and 10-Gsym/s FIR filters in 2-/spl mu/m GaAs HBTs and 0.18-/spl mu/m CMOS, respectively. The GaAs FIR filter is used in conjunction with spectrally efficient four-level pulse-amplitude modulation to demonstrate 10-Gb/s data throughput over 150 m of 500 MHz/spl middot/km multimode fiber. The same filter is also used to demonstrate equalization and crosstalk cancellation at 5 Gb/s on legacy backplane. The crosstalk canceller improves the bit error rate by five orders of magnitude. Furthermore, our CMOS FIR filter is tested and demonstrates backplane channel equalization at 10 Gb/s. Finally, building blocks for crosstalk cancellation at 10 Gb/s are implemented in a 0.18-/spl mu/m CMOS process. These circuits will enable 10-Gb/s data rates on legacy systems.     

An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS

This paper describes a backplane transceiver, which uses pulse amplitude modulated four-level (PAM-4) signaling and continuously adaptive transmit-based equalization to move 2.5-GBd/s symbols totalling 5 Gb/s across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors. The 17-mm/sup 2/ device is implemented in a 0.25-/spl mu/m CMOS process, operates off of 2.5- and 3.3-V supply voltages, and consumes 1 W.     

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-/spl mu/m CMOS technology. The receiver active area is 0.8 mm/sup 2/ and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10/sup -12/. The areas and power consumptions are 47 /spl mu/m /spl times/ 85 /spl mu/m and 13.2 mW for the equalizer, and 145 /spl mu/m /spl times/ 80 /spl mu/m and 10 mW for the ISI monitor.     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.     

A 17-mW 0.66-mm/sup 2/ direct-conversion receiver for 1-Mb/s cable replacement

A very-low-cost wireless personal area network (WPAN) receiver implemented in 0.25-/spl mu/m CMOS technology consumes 17mW of power and occupies an area of 0.66 mm/sup 2/. Simplicity in the physical layer, which still supports the 1-Mb/s requirement, allows for power savings in the receive front-end. A new coding scheme permits the integration of a high-pass filter to mitigate DC offset and 1/f noise. A linear front-end eliminates the external band-preselect filter. This die area is the smallest reported for Bluetooth-class front-ends.     

A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization

In this paper, a serial link design that is capable of 4.8-6.4-Gb/s binary NRZ signaling across 40' of FR4 copper backplane traces and two connectors is described. The transmitter features a programmable two-tap feed forward equalizer and the receiver uses an adaptive four-tap decision feedback equalization to compensate for the losses in the channel at 6.4 Gbps. The transceiver core is built in LSI's 0.13-/spl mu/m standard CMOS technology to be integrated into ASIC designs that require serial links. The transceiver consumes 310 mW per duplex channel at 1.2 V and 6.4 Gb/s under nominal conditions.     

An 8-Gb/s simultaneous bidirectional link with on-die waveform capture

A full-duplex transceiver capable of 8-Gb/s data rates is implemented in 0.18-/spl mu/m CMOS. This equalized transceiver has been optimized for small area (329 /spl mu/m /spl times/ 395 /spl mu/m) and low power (158 mW) for point-to-point parallel links. Source-synchronous clocking and per-pin skew compensation eliminate coding bandwidth overhead and reduce latency, jitter, and complexity. This link is self-configuring through the use of automatic comparator offset trim and adaptive deskew. Comprehensive diagnostic capabilities have been integrated into the transceiver to provide link, interconnect, and circuit characterization without the use of external test equipment. With a resolution of 4 mV and 9 ps, these capabilities enable on-die eye diagram generation, equivalent time waveform capture, noise characterization, and jitter distribution measurements.     

A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus

This paper describes a low-power synchronous pulsed signaling scheme on a fully AC coupled multidrop bus for board-level chip-to-chip communications. The proposed differential pulsed signaling transceiver achieves a data rate of 1 Gb/s/pair over a 10-cm FR4 printed circuit board, which dissipates only 2.9 mW (2.9 pJ/bit) for the driver and channel termination and 2.7 mW for the receiver pre-amplifier at 500 MHz. The fully AC coupled multipoint bus topology with high signal integrity is proposed that minimizes the effect of inter-symbol interference (ISI) and achieves a 3 dB corner frequency of 3.2 GHz for an 8-drop PCB trace. The prototype transceiver chip is implemented in a 0.10-/spl mu/m 1.8-V CMOS DRAM technology and packaged in a WBGA. It occupies an active area of 330/spl times/85 /spl mu/m/sup 2/.     

A 20-Gb/s 0.13-/spl mu/m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer

A 20-Gb/s transmitter is implemented in 0.13-/spl mu/m CMOS technology. An on-die 10-GHz LC oscillator phase-locked loop (PLL) creates two sinusoidal 10-GHz complementary clock phases as well as eight 2.5-GHz interleaved feedback divider clock phases. After a 2/sup 20/-1 pseudorandom bit sequence generator (PRBS) creates eight 2.5-Gb/s data streams, the eight 2.5-GHz interleaved clocks 4:1 multiplex the eight 2.5-Gb/s data streams to two 10-Gb/s data streams. 10-GHz analog sample-and-hold circuits retime the two 10-Gb/s data streams to be in phase with the 10-GHz complementary clocks. Two-tap equalization of the 10-Gb/s data streams compensate for bandwidth rolloff of the 10-Gb/s data outputs at the 10-GHz analog latches. A final 20-Gb/s 2:1 output multiplexer, clocked by the complementary 10-GHz clock phases, creates 20-Gb/s data from the two retimed 10-Gb/s data streams. The LC-VCO is integrated with the output multiplexer and analog latches, resonating the load and eliminating the need for clock buffers, reducing power supply induced jitter and static phase mismatch. Power, active die area, and jitter (rms/pk-pk) are 165 mW, 650 /spl mu/m/spl times/350 /spl mu/m, and 2.37 ps/15 ps, respectively.     

A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and /spl plusmn/2.5-cm range finding

A CMOS ultra-wideband impulse radio (UWB-IR) transceiver was developed in 0.18-/spl mu/m CMOS technology. It can be used for 1-Mb/s data communications as well as for precise range finding within an error of /spl plusmn/2.5 cm. The power consumptions of the transmitter and receiver for data communication are 0.7 and 4.0 mW, respectively. When an LNA operates intermittently through bias switching, the power consumption of the transceiver is only 1 mW. The range for data communication is 1 m with BER of 10/sup -3/. For ranging applications, the transmitter can reduce the power to 0.7 /spl mu/W for 1k pulses per second, and the receiver consumes little power. The transceiver design, all-digital transmitter, and intermittent circuit operation at the receiver reduce the power consumption dramatically, which makes the transceiver well suited for applications like sensor networks. The electronic field intensity is lower than 35 /spl mu/V/m, and thus the UWB system can be operated even under the current Japan radio regulations.     

A multimode 0.3-200-kb/s transceiver for the 433/868/915-MHz bands in 0.25-/spl mu/m CMOS

A fully integrated transceiver suitable for low-data-rate wireless telemetry and sensor networks operating in the license-free ISM frequency bands at 433, 868, or 915 MHz implemented in 0.25-/spl mu/m CMOS is presented. G/FSK, ASK, and OOK modulation formats are supported at data rates from 0.3 to 200 kb/s. The transceiver's analog building blocks include a low-noise amplifier, mixer, channel filter, received signal-strength indication, frequency synthesizer, voltage-controlled oscillator, and power amplifier. FSK demodulation is implemented using a novel digital complex-frequency correlator that operates over a wide modulation-index range and approximates matched filter detection performance. Automatic gain control, automatic frequency control, and symbol timing recovery loops are included on chip. Operating in the 915-MHz band in FSK mode at 9.6 kb/s, the receiver consumes 19.7 mA from a 3-V supply and achieves a sensitivity of -112.8dBm at 0.1% BER. The transmitter consumes 28.5 mA for an output power of 10 dBm and delivers up to 14 dBm.     

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-/spl mu/m digital CMOS technology

This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-/spl mu/m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 /spl mu/A/sub rms/. The input sensitivity of the receiver front-end is 16 /spl mu/A for 2.5-Gbps operation with bit-error rate less than 10/sup -12/, and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 /spl mu/m/spl times/1500 /spl mu/m.     

A 1.5-V 75-dB dynamic range third-order G/sub m/-C filter integrated in a 0.18-/spl mu/m standard digital CMOS process

A design methodology of a CMOS linear transconductor for low-voltage and low-power filters is proposed in this paper. It is applied to the analog baseband filter used in a transceiver designed for wireless sensor networks. The transconductor linearization scheme is based on regulating the drain voltage of triode-biased input transistors through an active-cascode loop. A third-order Butterworth low-pass filter implemented with this transconductor is integrated in a 0.18-/spl mu/m standard digital CMOS process. The filter can operate down to 1.2-V supply voltage with a cutoff frequency ranging from 15 to 85 kHz. The 1% total harmonic distortion dynamic range measured at 1.5 V for 20-kHz input signal and 50-kHz cutoff frequency is 75 dB, while dissipating 240 /spl mu/W.     

A 1.5-V 12-bit power-efficient continuous-time third-order /spl Sigma//spl Delta/ modulator

This paper presents the design strategy, implementation, and experimental results of a power-efficient third-order low-pass /spl Sigma//spl Delta/ analog-to-digital converter (ADC) using a continuous-time (CT) loop filter. The loop filter has been implemented by using active RC integrators. Several power optimizations, design requirements, and performance limitations relating to circuit nonidealities in the CT modulator are presented. The influence of the low supply voltage on the various building blocks such as the amplifier as well as on the overall /spl Sigma//spl Delta/ modulator is discussed. The ADC was implemented in a 3.3-V 0.5-/spl mu/m CMOS technology with standard threshold voltages. Measurements of the low-power 1.5-V CT /spl Sigma//spl Delta/ ADC show a dynamic range and peak signal-to-noise-plus-distortion ratio of 80 and 70 dB, respectively, in a bandwidth of 25 kHz. The measured power consumption is only 135 /spl mu/W from a single 1.5-V power supply.     

A 1 GHz CMOS analog front-end for a generalized PRML read channel

A 1 GHz CMOS analog front-end for general partial response maximum likelihood (GPRML) read channel in hard disk drive application has been implemented in 0.35 /spl mu/m CMOS. A continuous time analog filter fulfills the relaxed equalization for GPRML detection and can save up to 35% power consumption for the whole read channel. An analog DFE-based timing recovery loop is implemented to avoid the extremely long latency in the digital signal processing path (Viterbi decoder). The measured performances is 1.1 dB off simulations at 800 MHz and 1.6 dB off at 1GHz. The chip draws 240 mW from a 3.3 V supply at 800MHz clock and 380 mW from a 3.6 V supply at 1 GHz clock.     

A 1.6-GS/s 12-bit return-to-zero GaAs RF DAC for multiple Nyquist operation

A 12-bit 1.6-GS/s digital-to-analog converter (DAC) implemented with 4-/spl mu/m/sup 2/ GaAs HBT process is presented. Return-to-zero (RZ) current switches are added to current steering DAC for high-frequency wideband applications to achieve 800-MHz bandwidth at first and second Nyquist band without the need for a reverse sinc equalization filter in wideband transmitter application. The RZ circuit also improves spectral purity by screening the switching noise from the analog output during data transition. Measured performance shows two-tone third-order harmonic distortion of -70 dB at 1.5-GHz output frequency, clocked at 1.6 GHz. Reliable interface with CMOS logic IC is guaranteed with the inclusion of a four-clock-deep FIFO circuit. The DAC dissipates 1.2 W at -5 V when sampled with 1.6-GHz clock, with typical output voltage swing of 1.2 V/sub PP/.     

A CMOS double-heterodyne FM receiver

Experimental results for a narrow-band, adjustment-free double-heterodyne CMOS FM receiver with a high-Q switched-capacitor IF filter centered at 3 MHz are presented. The integration covers all the filtering and demodulation circuits from radio-frequency circuits (50-100 MHz) to the audio output. An experimental prototype FM receiver exhibiting a 5-mV input sensitivity and a -30-dB quieting level is implemented using 1.75-/spl mu/m double-poly CMOS technology. The chip occupies 7.7 mm and dissipates 80 mW with a 5-V supply.     

A 3-V, 0.35-/spl mu/m CMOS Bluetooth receiver IC

A fully integrated CMOS low-IF Bluetooth receiver is presented. The receiver consists of a radio frequency (RF) front end, a phase-locked loop (PLL), an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, and a frequency offset cancellation circuit. The highlights of the receiver include a low-power active complex filter with a nonconventional tuning scheme and a high-performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25-mm/sup 2/ die using TSMC 0.35-/spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 bit error rate, -10 dBm IIP3, and 15 dB noise figure were achieved in the measurements. The receiver active current is about 65 mA from a 3-V power supply.     

New miniature 15-20-GHz continuous-phase/amplitude control MMICs using 0.18-/spl mu/m CMOS technology

The design and performance of two new miniature 360/spl deg/ continuous-phase-control monolithic microwave integrated circuits (MMICs) using the vector sum method are presented. Both are implemented using commercial 0.18-/spl mu/m CMOS process. The first phase shifter demonstrates all continuous phase and an insertion loss of 8 dB with a 37-dB dynamic range from 15 to 20 GHz. The chip size is 0.95 mm /spl times/ 0.76 mm. The second phase shifter can achieve all continuous phase and an insertion loss of 16.2 dB with a 38.8-dB dynamic range at the same frequency range. The chip size is 0.71 mm /spl times/ 0.82 mm. To the best of the authors' knowledge, these circuits are the first demonstration of microwave CMOS phase shifters using the vector sum method with the smallest chip size for all MMIC phase shifters with 360/spl deg/ phase-control range above 5 GHz reported to date.