A new architecture of photonic ATM switches

A photonic asynchronous transfer mode (ATM) switch architecture for ATM operation at throughputs greater than 1 Tbit/s is proposed. The switch uses vertical-to-surface transmission electrophotonic devices (VSTEPs) for the optical buffer memory, and an optical-header-driven self-routing circuit in contrast with conventional photonic ATM switches using electrically controlled optical matrix switches. The optical buffer memory using massively parallel optical interconnections is an effective solution to achieve ultra-high throughput in the buffer. In the optical-header-driven self-routing circuit, a time difference method for a priority control is proposed. For the optical buffer memory, the write and read operations to and from the VSTEP memory for 1.6 Gbit/s, 8-bit optical signal are confirmed. The optical self-routing operation and priority control operation by the time difference method in the 4×4 self-routing circuit were performed by 1.6-Gbit/s 256-bit data with a 10-ns optical header pulse     

Large-scale ATM multistage switching network with shared buffermemory switches

The configuration of an asynchronous transfer mode (ATM) switch architecture using a shared buffer memory switch (SBMS) is discussed. The scaling factors of the ATM switching network under a condition of mixed applications, including a conventional mix and telecommunication with video, are analyzed. The use of the SBMS as the unit switch for a multistage switching network is examined. A prototype system and its performance evaluation and experimental data are presented. The data indicate excellent performance under a burst cell arrival condition. The buffer size of the SBMS can be reduced in comparison with that of an individual (nonshared) buffer memory switch. A configuration for a large-scale ATM switching network with multistage switches is proposed     

A photonic front-end processor in a WDM ATM multicast switch

Dense wavelength-division multiplexing (DWDM) technology has provided tremendous transmission capacity in optical fiber communications. However, switching and routing capacity is still far behind transmission capacity. This is because most of today's packet switches and routers are implemented using electronic technologies. Optical packet switches are the potential candidate to boost switching capacity to be comparable with transmission capacity. In this paper, we present a photonic asynchronous transfer mode (ATM) front-end processor that has been implemented and is to be used in an optically transparent WDM ATM multicast (3M) switch. We have successfully demonstrate the front-end processor in two different experiments. One performs cell delineation based on ITU standards and overwrites VCI/VPI optically at 2.5 Gb/s. The other performs cell synchronization, where cells from different input ports running at 2.5 Gb/s are phase-aligned in the optical domain before they are routed in the switch fabric. The resolution of alignment is achieved to the extent of 100 ps (or 1/4 bit). An integrated 1×2 Y-junction semiconductor optical amplifier (SOA) switch has been developed to facilitate the cell synchronizer     

Signal self-thresholding using wavelength-division multiplexed differential transmission for photonic ATM switches

A single self-thresholding method is proposed that eliminates rapid signal level fluctuations in photonic ATM switches. A 3 Gbit/s data stream with nanosecond-order level fluctuations can be discriminated. A bit error rate of 10/sup -10/ is obtained for switching cells of power -8.0 and -16.0 dBm.<>     

MEMS-actuated photonic crystal switches

A compact guided-wave optical switch is realized by integrating one-dimensional photonic crystals with microelectromechanical systems (MEMS) actuators. The ON-OFF switching is achieved by physically moving a photonic crystal defect. Experimental results show an extinction ratio of 11 dB at 1.56-/spl mu/m wavelength and a 0.5-ms time constant of the step response.     

Wide-sense non-blocking multicast ATM switches

Non-blocking multicast ATM switches can simplify the call admission control process and increase the utilisation level of external links. The condition for wide-sense non-blocking multicast ATM switches is derived and the routing algorithm is proposed. The required number of middle switches for the wide-sense non-blocking multicast switch is significantly less than that of the strictly non-blocking multicast switch     

Terminology for photonic matrix switches

A classification scheme is suggested here for matrix switches that use photonic principles, generally for broadband signal routing. The classification considers three independent properties, providing for a large number of categories with properties that differ in identifiable ways. Salient properties of each class are noted. Matrices are classified in the following ways: according to the switching principles used i.e. optical or optoelectronic; according to the multiplexing system used in the switch i.e. space division, modulation division or carrier division; and according to the optical configuration of the switched systems, i.e. centrally switched, optically extended or distributed. Examples of the various types are given     

Write policies for multicast ATM switches

A unicast and multicast-pushout write policy for shared-memory ATM switches is proposed. The scheme allocates buffers based on the service rates of unicast and multicast cells to ensure that maximum throughput can be maintained     

Sharing memory in banyan-based ATM switches

We study a multistage ATM switch in which shared-memory switching elements are arranged in a banyan topology. By “shared-memory,” we mean that each switching element uses output queueing and shares its local cell buffer memory among all its output ports. We apply a buffer management technique called delayed pushout that was originally designed for multistage ATM switches with hierarchical topologies. Delayed pushout combines a pushout mechanism, for sharing memory efficiently among queues within the same switching element, and a backpressure mechanism, for sharing memory across switch stages. The backpressure component has a threshold to restrict the amount of sharing between stages. A synergy emerges when pushout, backpressure, and this threshold are all employed together. Using a computer simulation of the switch under bursty traffic, we study delayed pushout as well as several simpler pushout and backpressure schemes under a variety of traffic conditions. Of the five schemes we simulate, delayed pushout is the only one that performs well under all load conditions     

Realization of large capacity ATM switches

Large-capacity ATM switches, with switching capacity in excess of 40 Gb/s or 100 Gb/s, are becoming an essential part of network growth. To realize such switches requires technology know-how as well as implementation trade-off considerations. This article provides a system-level exploration of large-capacity ATM switches in terms of switch fabric scalability, cell buffer management, buffer design trade-off, call processing capabilities, and future trends in switch design     

Multiwavelength highway photonic switches using wavelength-sortingelements-design

We propose multiwavelength highway photonic switch architectures for cross-connects using the wavelength routing function of the waveguide-array-grating demultiplexer. The wavelength router is used as wavelength-sorting elements. The wavelength division multiplexed (WDM) optical signals from multiple input ports are routed to group of output ports with certain combination of wavelengths. This enables multiport WDM systems to be configured using the reduced number of wavelength demultiplexing and multiplexing elements     

An efficient architecture for fault-tolerant ATM switches

A cost-effective fault-tolerant architecture called FAUST is presented for ATM switches. The key idea behind the architecture is the incorporation of spare units and associated commutation logic into strategic partitions of the switching system. The definition of a replaceable unit is flexible, and based on packaging considerations. The commutation logic can switch in a spare unit in place of a failed one at cell rate, and is distributed entirely in the existing switch control units. So the additional overhead is almost entirely in the spare modules provided. The technique is far superior to a duplex configuration in terms of reliability improvement vs. component redundancy, and can be applied to established architectures for ATM switches, including multistage sort and shared memory based architectures. Its scalability also makes it applicable to system sizes from a few tens of lines to a few thousand     

波分复用各向异性光子晶体滤波器

从光子晶体的光子频率禁带特性出发，提出了用两个或两个以上的各向异性周期结构光子晶体叠加在一起，形成叠层结构光子晶体，以获得窄带滤波特性的设想；利用光学传输矩阵法研究了这种结构的光子晶体，分析了在不同入射角和折射率条件下，该周期结构的透射和偏振的光学特性。分析表明，各向异性光子晶体在折射率比值较大或与高折射率各向同性介质结合使用，可以获得较窄的通带，从而实现滤波。数值模拟的结果也证实了上述构思的正确性。     

Provisioning QoS features for input-queued ATM switches

A new scheduling algorithm is proposed to improve on existing algorithms designed for input-queued ATM switches. By assigning a session weight according to its queue length normalised by its rate and using maximum weight matching to obtain a match, the proposed algorithm can avoid starvation of slow sessions, thus providing good delay properties as well as fair services, and at the same time reducing traffic burstiness     

Fault-tolerant multicasting in MINs for ATM switches

This article proposes a fault-tolerant multicast routing algorithm in multistage interconnection networks (MINs) for ATM switch architectures. It employs both region and cube encoding schemes as the header encoding scheme. A multicast packet can be routed to its destinations in only two phases through the MIN having a single faulty element     

Optimum architecture for input queuing ATM switches

An input queueing ATM switch architecture employing the contention resolution called 'scheduling algorithm' is described. A high efficiency of over 90% can be achieved without any considerable increase in the amount of hardware or contention control speed.<>     

Design of wide-sense nonblocking multicast ATM switches

Nonblocking multicast asynchronous transfer mode (ATM) switches can simplify the call admission control process and increase the external links' utilization. We derive the wide-sense nonblocking condition for multicast ATM switches based on a general Clos network. We also propose a routing algorithm to achieve wide-sense nonblocking. It is illustrated by an example that the number of required middle stages in our switch is significantly less than that of strictly nonblocking multicast switches     

Multimode interference photonic switches (MIPS)

The switching characteristics of multimode interference photonic switches (MIPS) are analyzed by wide-angle finite difference beam propagation method (FD-BPM). As a result, it is found that the MIPS with a multimode interference (MMI) length of 599 μm can switch the output light polarization insensitively with a crosstalk of less than -20 dB for a wavelength range of 70 nm. These analyses show that the MIPS can also have a 3-dB coupler function. Experimentally, an InGaAsP/InP 1×2 MIPS with a thicker InP cladding layer was fabricated and exhibited switching operation with crosstalks of -8 dB and -10 dB at 0 and 20 mA current injections, respectively. For a 2×2 MIPS with a thinner InP cladding layer, better switching characteristics with a crosstalk of -13 dB and an extinction ratio of 17 dB were realized     

Self-firing cell scheduler for input queueing ATM switches

The authors propose a simple cell scheduler for input queueing ATM switches. The proposed self-firing cell scheduler consists of N² processing elements connected by a two dimensional torus network, where each processing element can determine the diagonal by itself in a distributed manner. It allows a simple implementation for high speed ATM switches     

Optimal cost/performance design of ATM switches

This paper proposes a methodology for performing an evaluation and optimization of the cost of an ATM switching architecture under performance constraints given in terms of virtual connection blocking probability. An analysis of blocking networks is developed, and combined with known results concerning nonblocking networks, provides a theoretical model which relates traffic characteristics, network topology and blocking probability in a multirate/multiservice broadband environment. An analysis of the characteristics determining the cost of a generic ATM switch implementation follows. The model is oriented to optimize both the topological parameters and the speed advantage, with respect to the main cost factors of VLSI-based switching networks i.e., components count and complexity, interconnection costs