Alpha-particle tracks in silicon and their effect on dynamic MOS RAM reliability

Recent investigations [1] have found low levels of alpha particles (< 0.1 counts/cm². h) emitted from the immediate chip environment to be responsible for soft errors in 16K MOS dynamic RAM's. We have investigated this problem in two related studies. First, we review the interaction of alpha particles with the Si lattice and present range-energy and specific ionization data. Experimental values of the actual charge collected at shallow junctions for 4.9-MeV alpha events are presented. The dynamics of the collection process and the influence of the interface electric field in p-p⁺epitaxial material are identified. We further show the dependence of the collected charge on the incident particle energy and angle. Second we review the operation of current memory devices and indicate how soft failures due to alpha particles can be identified. We present soft error rate versus duty cycle data for a number of devices displaying different failure modes. The dependence of the soft error rate on incident particle energy and angle is also shown. Finally, we propose a simple accelerated test to evaluate device susceptibility to this failure mode.     

Numerical analysis of alpha-particle-induced soft errors in floating channel type surrounding gate transistor (FC-SGT) DRAM cell

This paper clarifies alpha-particle-induced soft error mechanisms in floating channel type surrounding gate transistor (FC-SGT) DRAM cells. One FC-SGT DRAM cell consists of an FC-SGT and a three-dimensional (3-D) storage capacitor. The cell itself arranges bit line (BL), storage node and body region in a silicon pillar vertically and achieves cell area of 4F/sup 2/ (F: feature size) per bit. In FC-SGT DRAM cells, the parasitic bipolar current is a major factor to cause soft errors. When an alpha particle penetrates the silicon pillar, generated electrons are collected to the storage node or BL due to the tunneling and diffusion mechanisms. On the other hand, holes are swept into the body region and accumulated. Consequently, the current flows not only in the surface but also in the entire body region due to the floating body effect. This parasitic bipolar current becomes the largest when an alpha particle penetrates the silicon pillar along the vertical axis. However, in case of FC-SGT DRAM cells, the surrounding gate structure can suppress the floating body effect compared with floating channel type SOI DRAM cells. As a result, the loss of the stored charge in the storage capacitor can be drastically decreased by using FC-SGT DRAM cell. Therefore, FC-SGT DRAM is a promising candidate for future high-density DRAMs having high soft-error immunity.     

An on-chip ECC circuit for correcting soft errors in DRAMs withtrench capacitors

A modified error-correcting code that can correct up to two soft errors on each row (word line) in a dynamic random-access memory (DRAM) chip is proposed. Double-bit soft errors frequently occur in DRAM cells with trench capacitors, when charged alpha particles impinge on the intervening space between two vertical capacitors causing plasma shorts between them. The conventional on-chip error-correcting codes (ECCs) cannot correct such double-bit word-line soft errors, which significantly increase the uncorrectable error rate (UER). An ECC circuit that uses an augmented rectangular product code to detect and correct double-bit soft errors is presented. The proposed circuit automatically corrects the addressed bit if it is faulty, and then quickly locates the other faulty bit. A comprehensive study is made to estimate improvements in soft error rate (SER) and mean time to failure (MTTF). The ability of the circuit to correct soft errors in the presence of multiple-bit errors has also been analyzed by combinatorial enumeration     

TLM: a trench leakage monitor for a four megabit SPT DRAMtechnology

The authors discuss a single trench capacitor macro-array structure used for trench dynamic random access memory (DRAM) device design and characterization, and as a manufacturing test vehicle. A nonaddressable array of trench-capacitor DRAM cells is used for quantification of trench DRAM leakage parameters, storage node parasitic device characterization, and silicon defects. Used with an addressable functional monitor, it is found to be a valuable semiconductor process development vehicle to achieve functionality and cell retention yield for a 4-Mb CMOS DRAM technology     

DRAM reliability

Dynamic random access memory (DRAM) reliability is investigated for future DRAMs where small geometrical devices are used together with new materials and novel process technologies. Among the several items of DRAM reliability, the most important aspect to consider for DRAM reliability is infant mortality which is caused by process-induced defects including random defects. Since the process-induced defects are strongly dependent on process technology, it is inevitable to minimize process-induced defects by developing new process technology. However, whenever new process technology is introduced, new screening techniques or methods are necessary for suppressing infant mortality. The degradation of pMOSFET due to buried-channel pMOSFET during burn-in stress and soft error rate due to α-particle and cosmic ray irradiation become concerns as device dimension shrinks. However, it cannot be limitations of DRAM reliability because pMOSFET degradation due to hot electron induced puchthrough can be suppressed by new layout of pMOSFET, and the soft error events can be overcome by soft error resistant device structure and proper material choices. From these considerations, it can be expected that the advances of DRAM technology generation not only improve the device performance but also enhance the reliability.     

Cosmic ray soft error rates of 16-Mb DRAM memory chips

Manufactured 16-Mb DRAM memory chips use three different cell technologies for bit storage: stacked capacitors, trenches with internal charge, and trenches with external charge. We have measured the soft fail probability of 26 different 16-Mb chips produced by nine vendors to evaluate whether the different cell technologies have an impact on the chip soft error rate. This testing involved irradiation with neutrons, protons, and pions, the principle hadrons of terrestrial cosmic rays. The results show clear differences in soft-fail sensitivity, which appears to be related to the cell structure     

Negative resistance element for a static memory cell based onenhanced surface generation [MOS devices]

A negative resistance (NR) element for a static memory cell using enhanced surface generation of MOS devices is proposed. Such a memory cell will maintain information with extremely small current information and the control circuitry can be the same as in one-transistor dynamic memories. The mechanism of operation is discussed and some experimental data are presented. It is shown that in order to maintain information in a single static memory cell, the required current can be as low as a few picoamperes. Operating currents are large enough to compensate for leakage currents of storage capacitors in dynamic RAM (DRAM) memories. By adding the proposed circuit in parallel with those capacitors, the dynamic memory can be converted into a static memory requiring no refresh circuit or restoring circuit. In the proposed memory structure, the storage capacitor can be reduced significantly or perhaps even eliminated. This will result in much faster operation in comparison to DRAM memories     

Alpha particle emission from platinum and its influence on DRAM operation

Ferroelectrics such as SrTiO/sub 3/ have been studied as DRAM capacitor insulators. Platinum is commonly used as their electrode material. However, platinum contains the isotope Pt/sup 190/, emitting alpha particles which cause soft errors. The authors measured the alpha particle emissivity of platinum coated silicon wafers. The resultant emissivity is consistent with the calculation. The impact on DRAM operation was estimated.<>     

Ferroelectric memory: on the brink of breaking through

With a memory-cell size comparable to that of a DRAM memory cell and a manufacturing process similar to that of a stacked high-density DRAM, it can be expected that the ferroelectric technology will leverage off DRAMs and leap frog to higher memory densities. Cost analysis projects cost competitiveness with flash memory and EEPROM. Ferroelectric memory technology has been shown to have reliability levels comparable to or better than other reprogrammable nonvolatile semiconductor memories. High levels of radiation hardness make these memories suitable for near and deep-space applications. Many large semiconductor companies have substantial efforts to develop and introduce ferroelectric memories into the market     

A long-refresh dynamic/quasi-nonvolatile memory device with 2-nmtunneling oxide

A memory device using silicon rich oxide (SRO) as the charge trapping layer for dynamic or quasi-nonvolatile memory application is proposed. The device achieved write and erase speed at low voltage comparable to that of a dynamic-random-access memory (DRAM) cell with a much longer data retention time. This device has a SRO charge trapping layer on top of a very thin tunneling oxide (<2 nm). Using the traps in the SRO layer for charge storage, a symmetrical write/erase characteristics were achieved. This new SRO cell has an erase time much shorter than values of similar devices reported in the literature     

Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology

A multistrata dynamic random access memory (DRAM) vertically integrated with a complementary metal oxide semiconductor (CMOS) logic device using through-silicon vias (TSVs) and a unique interposer technology was developed for high-performance, power-efficient, and scalable computing. SMAFTI (SMArt chip connection with FeedThrough Interposer) technology, featuring an ultra-thin organic interposer with high-density feedthrough conductive vias, was used for interconnecting the three-dimensionally stacked DRAM and the CMOS logic device . A DRAM-compatible TSV manufacturing process was realized through the use of a “via-first” process and highly doped poly-Si TSVs for vertical traces inside memory dice. A multilayer ultra-thin die stacking process with micro-bump interconnection using a solid-liquid interdiffusion technique was also developed. The thermal aging reliability of the micro-bump interconnection was evaluated by a unique analysis method and its basic reliability was confirmed. Finally, we fabricated a prototype package including stacked DRAM and a CMOS logic device, and observed the combined operation. High-speed 3 Gbit/s signals were successfully transmitted through the fine interposer between the memory and logic.      

Device design guidelines for FC-SGT DRAM cells with high soft-error immunity

This paper describes the device design guidelines for floating channel type surrounding gate transistor (FC-SGT) DRAM cells with high soft-error immunity. One FC-SGT DRAM cell consists of an FC-SGT and a three-dimensional storage capacitor. The cell itself arranges the bit line (BL), storage node, and body region in a silicon pillar vertically and hence, achieves a cell area of 4F/sup 2/ (F: feature size) per bit. A thin-pillar FC-SGT with a metal gate can maintain a low leakage current without using a heavy doping concentration in the body region. Furthermore, as the silicon pillar thickness is reduced, the device enters into the fully depleted operation and as a result can realize excellent switching characteristics. In FC-SGT DRAM cells, the parasitic bipolar current is a major factor that causes soft errors to occur. However, the parasitic bipolar current can be suppressed and its duration can be shortened as the silicon pillar thickness is reduced. As a result, the amount of stored charge lost in the storage capacitor can be effectively decreased by using a thin-pillar FC-SGT. In the case of a 10-nm-thick FC-SGT, the amount lost due to the parasitic bipolar current is decreased to about 28% of that due to the leakage current. Therefore, FC-SGT DRAM is a promising candidate for future nanometer high-density DRAMs having high soft-error immunity.     

The measurement of alpha particle emissions from semiconductor memory materials

With the increasing concern for the affects of alpha particles on the reliability of semiconductor memories, an interest has arisen in characterizing semiconductor manufacturing materials for extremely low-level alpha-emitting contaminants. It is shown that four elements are of primary concern: uranium, thorium, radium, and polonium. Measurement of contamination levels are given relevance by first correlating them with alpha flux emission levels and then corre1ating these flux values with device soft error rates. Measurement techniques involve either measurements of elemental concentrations-applicable to only uranium and thorium - or direct measurements of alpha emission fluxes. Alpha fluxes are most usefully measured by means of ZnS scintillation counting, practical details of which are discussed. Materials measurements are reported for ceramics, solder, silicon, quartz, and various metals and organic materials. Ceramics and most metals have contamination levels of concern, but the high temperature processing normally used in semiconductor manufacturing and low total amounts reduce problems, at least for metals. Silicon, silicon compounds, and organic materials have been found to have no detectable alpha emitters. Finally, a brief discussion of the calibration of alpha sources for accelerated device testing is given, including practical details on the affects of source/chip separation and alignment variations.     

A dynamic RAM Cell in recrystallized polysilicon

A new, one-transistor, dynamic RAM cell has been fabricated in beam-recrystallized polysilicon. Placing thin oxides both above and below the storage region doubles the storage capacitance. Complete isolation of the storage region by oxides also reduces the susceptibility of the cell to soft errors from collection of charge injected into the substrate by the surrounding elements or by alpha particles. Long storage times are feasible, being limited only by the leakage of the access transistor. A thick oxide under the bit line reduces the bit-line capacitance, further increasing the ratio of storage capacitance to bit-line capacitance.     

Soft error susceptibility mapping of DRAMs using a high-energy nuclear microprobe

Soft errors in 16 Mbit dynamic random access memories (DRAMs) have been investigated using proton microprobes at 400 keV with a spot size of 1 × 1 μm². The newly developed susceptibility mapping can reveal the correlation between the particle hit-position position and the susceptibility to soft errors in a DRAM. The cell-mode soft-errors were found to take place by the incidence of ions within 6 μm around a monitored cell. These errors would be induced by minority carrier diffusion in a lateral direction. This result manifests the possibility of multiple-bit errors by the incidence of an energetic particle.     

An experimental large-capacity semiconductor file memory using16-levels/cell storage

A 4-bit semiconductor file memory using 16-levels (4-bits)/cell storage is described. The device has 1-Mb single-transistor dynamic memory cells which are divided into 4-kb sequential-access blocks. It incorporates a staircase-pulse generator for multilevel storage operations, a voltage regulator to protect against power-supply voltage surge, and a soft-error-correction circuit based on a cyclic hexadecimal code. The device is fabricated using 1.3-μm CMOS technology. It operates with a 5-V single power supply. Random block selection time is 147 μs, while the sequential data rate is 210 ns. A single-incident alpha particle destroys 4-bit data in two or more adjacent cells. The error correction circuit completely corrects these errors. The soft-error rate under actual operating conditions with error correction is expected to be under 100 FIT (10^-7 h^-1)     

Tunneling-based SRAM

This paper describes a new high-density low-power circuit approach for implementing static random access memory (SRAM) using low current density resonant tunneling diodes (RTDs). After an overview of semiconductor random access memory architecture and technology, the concept of tunneling-based SRAM (TSRAM) is introduced. Experimental results for a compound semiconductor 1-bit 50-nW TSRAM gain cell using low current density (~1 A/cm²) RTDs and low-leakage heterostructure field effect transistors are presented. We describe a one-transistor TSRAM cell which could convert silicon dynamic RAM (DRAM) to ultradense SRAM if an ultralow current density (~1 μA/cm² ) silicon bistable device is developed. Finally, we present experimental and simulation results for a TSRAM cell using multipeaked I-V curve devices and a multivalued word line. This approach aims at increasing storage density through vertical integration of bistable devices such as RTD's     

Alpha-particle-induced soft errors in dynamic memories

A new physical soft error mechanism in dynamic RAM's and CCD's is the upset of stored data by the passage of alpha particles through the memory array area. The alpha particles are emitted by the radioactive decay of uranium and thorium which are present in parts-per-million levels in packaging materials. When an alpha particle penetrates the die surface, it can create enough electron-hole pairs near a storage node to cause a random, single-bit error. Results of experiments and measurements of alpha activity of materials are reported and a physical model for the soft error is developed. Implications for the future of dynamic memories are also discussed.     

A three charge-states model for silicon nanocrystals nonvolatile memories

In the field of nonvolatile memories, substantial improvement of reliability is obtained by replacing the continuous polysilicon floating gate by a planar distribution of silicon nanocrystals, each acting as a storage node. The test devices in the present paper are MOS capacitors containing a two-dimensional layer of nanocrystals located 2.5 nm away from the oxide/substrate interface, inside the SiO/sub 2/. This work presents various measurements of the charge current versus either bias voltage or time. On the other side, the charge and discharge dynamics of the nanocrystals had already been described by De Salvo using a model borrowed from the conventional floating-gate memory. We show this approach to be not completely suitable to explain the experimental observations. Thus, we describe and apply a so-called granular model, based on a mono-electronic principle limited by Coulomb blockade, in which electrons interact with the nanocrystals one by one. Omitting the reality of such a one-by-one principle may involve important mistakes in the interpretation of phenomena.     

New Insights on “Capacitorless” Floating-Body DRAM Cells

The notion of a "potential well" for charge storage in the floating body of the "capacitorless" DRAM cell is shown to be inadequate and misleading. The basic operation of the floating-body MOSFET cell (FBC) is physically overviewed, with supportive numerical device simulations and analytical modeling. New insights are revealed, including identification of the intrinsic dynamic capacitors that actually store the body charge. Multiple roles of an accumulation layer that is needed in fully depleted FBCs are physically defined for the first time. Optimal FBC designs are implied