Excess currents induced by hot hole injection and FN electroninjection in thin SiO2 films

The behavior of excess currents induced by Fowler-Nordheim electron injection stress (FN electron injection) has been investigated for 6.0-nm oxides. Excess currents are induced by FN electron injection in 6.0-nm oxides together with positive charges being induced in it. To clarify the role of hole injection in FN electron injection, the behavior of excess currents induced by substrate hot hole injection has also been investigated in 6.0-nm oxides. The leakage behavior after hot hole injection is the same as FN electron injection. The excess currents induced both by the FN electron injection and by the substrate hot hole injection are due to trap-assisted tunneling and field enhancement at the cathode due to the positive trapped charge. The charge centroid of the positive charges induced by both stresses are located 3.0 nm from the Si/SiO₂ interface which is at the center of 6.0-nm oxide. The excess currents induced by hot hole injection and FN electron injection are caused by traps in SiO₂ films produced by injected holes from the anode     

Impact of the trapping of anode hot holes on silicon dioxide breakdown

Hot holes are injected from the anode and trapped in thin silicon dioxide using constant voltage stress at large gate voltage. By comparing oxides having trapped holes with oxides in which the holes were detrapped, it is shown that the presence of trapped holes does not affect the breakdown of the oxide. Furthermore, as the temperature during stress is increased, less hole trapping is observed whereas the charge-to-breakdown of the oxide is decreased. The results show that although the trapping of hot holes injected using anode hole injection (AHI) may be partly responsible for defect generation in silicon dioxide, breakdown cannot be limited by the number of holes trapped in the oxide.     

A hot hole-induced low-level leakage current in thin silicondioxide films

A new kind of stress-induced low-level leakage current (LLLC) in thin silicon dioxide is reported. It is observed after the stress of hot hole injection at the gate edge. Since voltage dependence of this new kind of LLLC is steeper than that of conventional FN stress-induced LLLC, each conduction mechanism may be different. This LLLC is reduced by both hot electron injection and UV irradiation. These reductions are never observed in FN stress-induced LLLC. The most promising mechanism is sequential tunneling via trapped holes     

Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices

A novel measurement method to extract the spatial distribution of channel hot electron injection is described. The method is based on characterization of localized trapped-charge in the nitride read-only memory (NROM) device. The charge distribution is determined by iteratively fitting simulated subthreshold and gate induced drain leakage (GIDL) currents to measurements. It is shown that the subthreshold and the GIDL measurements are sensitive to charge trapped over the n+ junction edge. Their characteristics are determined by the trapped charge width, density and location and the associated fringing field. Extremely high sensitivity of the GIDL measurement to localized charge over the n+ junction is demonstrated. The extracted charge distribution width is shown to be /spl sim/40 nm, located over the junction edge.     

Investigation of oxide charge trapping and detrapping in a MOSFETby using a GIDL current technique

We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10⁴ times more efficient in trap generation than the hot electron stress in terms of injected charge     

Degradation of oxides and oxynitrides under hot hole stress

The impact of nitridation on hot hole injection and the induced degradation is quantitatively studied by comparing the behavior of a control oxide and oxynitrides. The oxynitride is prepared by either annealing the oxide in N₂O or growing directly in N₂ O. The pMOSFET's are uniformly stressed by using the substrate hot hole injection technique. The physical quantities analyzed include the hole injection current, the density of created interface states and the density of trapped holes. It is found that a 30 min annealing in N₂ O at 950°C can enhance the effective barrier for hole injection by 0.6 eV. However, the interface state generation during the injection is insensitive to nitridation. The continuing degradation post the hole injection is also investigated. This includes a poststress interface state build-up and the generation of new precursors for interface states. The nitridation reduces the poststress degradation considerably. Where it is necessary, the hole induced degradation is compared with that induced by electrons. The applicability of the models proposed for oxynitrides to the present results is examined     

Design of 0.1-μm pocket n-MOSFETs for low-voltage applications

Channel length 0.1-μm pocket n-MOSFETs meeting the specifications of sensitivity of off-state current to channel length, off-state (leakage) current, on-state (drive) current and 1 V power-supply voltage are designed using a two-dimensional device simulator, Medici, in order to construct a viable design space locating the well-designed 0.1-μm pocket devices. The 0.1-μm pocket n-MOSFETs located within the viable design space are partitioned into two types of pocket devices on the basis of gate controllability of channel- and depletion-layer charges. The 0.1-μm pocket n-MOSFETs are compared with 0.1-μm conventional bulk n-MOSFETs selected to meet the same specifications and prove to be effective in reducing sensitivity to channel-length variations.     

Hot-carrier-stress effects on gate-induced drain leakage current inn-channel MOSFETs

The effects of hot-carrier stress on gate-induced drain leakage (GIDL) current in n-channel MOSFETs with thin gate oxides are studied. It is found that the effects of generated interface traps (ΔD _it) and oxide trapped charge on the GIDL current enhancement are very different. Specifically, it is shown that the oxide trapped charge only shifts the flat-band voltage, unlike ΔD _it. Besides band-to-band (B-B) tunneling, ΔD _it introduces an additional trap-assisted leakage current component. Evidence for this extra component is provided by hole injection. While trapped-charge induced leakage current can be eliminated by a hole injection subsequent to stress, such injection does not suppress interface-trap-induced leakage current     

NROM: A novel localized trapping, 2-bit nonvolatile memory cell

This paper presents a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation. It is based on the storage of a nominal ~400 electrons above a n⁺/p junction. Programming is performed by channel hot electron injection and erase by tunneling enhanced hot hole injection. The new read methodology is very sensitive to the location of trapped charge above the source. This single device cell has a two physical bit storage capability. The cell shows improved erase performances, no over erase and erratic bit issues, very good retention at 250°C, and endurance up to 1M cycles. Only four masks are added to a standard CMOS process to implement a virtual ground array. In a typical 0.35 μm process, the area of a bit is 0.315 μm² and 0.188 μm² in 0.25 μm technology. All these features and the small cell size compared to any other flash cell make this device a very attractive solution for all NVM applications     

Trapped charge modulation: a new cause of instability inAlGaAs/InGaAs pseudomorphic HEMT's

A new degradation mechanism of PM-HEMT's subsequent to hot electron stress tests or high temperature storage tests is presented. A noticeable increase in drain-to-source current, I_DS, is observed after the tests. We show that this I_DS variation is slowly recoverable and is correlated with the presence of deep levels in the device. Stress tests cause a variation of trapped charge. Trapping of holes created by impact-ionization and/or thermally stimulated electron detrapping induce a variation of the net negative trapped charge, leading to a decrease in the threshold voltage, V_T and a consequent increase in I_DS. The correlation between g _mΔV_T and ΔI_DS clearly demonstrates that the variation of trapped charge induced by hot electron tests is localized under the gate     

The effect of channel hot-carrier stressing on gate-oxide integrityin MOSFETs

The correlation between channel hot-carrier stressing and gate-oxide integrity is studied. It is found that channel hot carriers have no detectable effect on gate-oxide integrity even when other parameters (e.g., ΔV_T and ΔI _D) have become intolerably degraded. In the extreme cases of stressing at V_G≈V_T with measurable hole injection current, however, the oxide charge to breakdown decreases linearly with the amount of hole fluence injected during the channel hot-hole stressing. This may limit the endurance of a nonvolatile memory using hot holes for erasing. This can also explain the gate-to-drain breakdown of a device biased in the snap-back region, since snap-back at low gate voltage is favorable for hole injection. Snap-back-induced oxide breakdown could be an ESD (electrostatic discharge) failure mechanism     

Avalanche electron injection in 4-nmSi3N4/8-nm SiO2 dielectric structure:turn-around phenomenon and Si-SiO2 interface degradation

Charge trapping and interface-state generation in very thin nitride/oxide (4-nm Si₃N₄+8-nm SiO₂) composite gate insulators are studied as a function of gate electrode work function and bottom oxide thickness. The behavior of the trapped positive charge under bias-temperature stress after avalanche electron injection (AEI) is investigated. Evidence is presented that secondary hole injection from the anode (gate/Si₃N₄ interface) and subsequent trapping near the SiO₂-Si interface result in a turnaround of the flatband voltage shift during AEI from the substrate. Just like the thermal oxides on Si, slow-state generation near the SiO₂-Si interface and boron acceptor passivation in the surface-space charge layer of the Si substrate are also observed after AEI in these nitride/oxide capacitors, and they are found to be strongly related to the secondary hole injection and trapping. Finally, interface-state generation can take place with little secondary anode hole injection and is enhanced by the occurrence of hole trapping     

Charge pumping spectroscopy: HfSiON defect study after substrate hot electron injection

Spectroscopic charge pumping (CP) is used to study the evolution of the energy distribution of trapped electrons within HfSiON/SiO₂ gate stacks under substrate hot electron injection (SHEI). Base level CP measurements with large pulse amplitude allow an efficient charging/discharging of traps and reaching two defect bands in the HfSiON situated at 0.40 and 0.85 eV above the Si conduction band, respectively. Unlike standard constant voltage stress (CVS), SHEI enables full control of the stress by separately controlling the applied gate field, the injected electron energy, and the fluence. During CVS, HfSiON defects at 0.40 eV are generated. Conversely, during SHEI, either the shallow or the deep defects are preferentially created depending on the gate field as well as electron energy.     

热载流子注入对MOS结构C─V和I─V特性的影响

讨论了热载流子注入对ＭＯＳ结构Ｃ─Ｖ和Ｉ─Ｖ特性的影响。指出热载流子效应引起载流子陷落和界面态的产生，导致Ｃ─Ｖ特性曲线畸变、平带电压漂移和恒定电压下ＳｉＯ２漏电流随时间漂移。本文论述了这些漂移的机理，提出了漂移的ｔｎ物理模型，从而很好地解释了实验所观察到的现象。     

Impact of wafer charging on hot carrier reliability and optimization of latent damage detection methodology in advanced CMOS technologies

We have studied the possibility to use hot carrier stresses to reveal the latent damage due to Wafer Charging during plasma process steps in 0.18 μm and 0.6 μm CMOS technologies. We have investigated various hot carrier conditions in N- and PMOSFETs and compared the results to classical parametric studies and short electron injections under high electric field in Fowler–Nordheim regime, using a sensitivity factor defined as the relative shift towards a reference protected device. The most accurate monitor remains the threshold voltage and the most sensitive configuration is found to be short hot electron injections in PMOSFET’s. The ability of very short hot electron injections to reveal charging damage is even more evidenced in thinner oxides and the better sensitivity of PMOSFET is explained in terms of conditions encountered by the device during the charging process step.     

Hot carrier effects in n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate

Charge trapping and trap generation in field-effect transistors with SiO₂/HfO₂/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case.     

Effect of long-term stress on IGFET degradations due to hot electron trapping

The threshold voltage shift through the long-term stress is measured for IGFET's. The gate bias dependence shows that the hot electron trapping is affected strongly by the electric field in the gate insulator. The threshold voltage shift versus time is well explained with the theory modified by the effect of the trapped charge on the subsequent electron trapping. The effect of transistor dimensions and temperature are also discussed.     

Experimental extraction of degradation parameters after constant voltage stress and substrate hot electron injection on ultrathin oxides

The impact of hot electrons on gate oxide degradation is studied by investigating devices under constant voltage stress and substrate hot electron injection in thin silicon dioxide (2.5–1.5 nm). The build-up defects measured using low voltage stress induced leakage current is reported. Based on these results, we propose to extract the critical parameter of the degradation under simultaneous tunnelling and substrate hot-electron stress. During a constant voltage stress the oxide field, the injected charge and the energy of carriers are imposed by V_G and cannot be studied independently. Substrate hot electron injection allows controlling the current density independent of the substrate bias and oxide voltage. The results provide an understanding for describing the reliability and the parameters dependence under combined substrate hot electron injection and constant voltage stress tunnelling.     

The study of threshold voltage extraction of nitride spacer NMOS transistors in early stage hot carrier stress

Threshold voltage V/sub t/ extracted by g/sub m/-maximum extrapolation method under early stage hot carrier stress is proven to be an inappropriate method once electrons are trapped in a nitride spacer. The trapping of electrons in a nitride spacer increases the series drain resistance, reducing the transconductance g/sub m/ and the corresponding gate-to-source voltage V/sub gs/ at which peak g/sub m/ occurs. It ultimately decreases the threshold voltage V/sub t/ extracted by the g/sub m/-maximum extrapolation method. A novel algorithm is derived to determine the relationship between the measured data and the true threshold voltage of such a device under hot carrier stress by considering the effect of series resistance in g/sub m/-maximum extrapolation method.     

The effect of hot electron current density on nMOSFET reliability

In this paper, we consider the reliability of n-channel MOSFETs using the Substrate Hot Electron (SHE) technique. We confirm that there is a dependence of oxide degradation upon the current density during SHE injection (as previously observed by ourselves and others). In order to explain this effect, the detrapping of previously trapped electrons must be taken into account A new theoretical model is presented which accounts for the main features of the phenomenon. We consider the technologically important low field case (< 2MVcm⁻¹) for a range current densities (from 0.05 to 2 mAcm⁻²) and injected charge densities up to 10 C/cm². The device lifetime for these different conditions is calculated and shown to be also a function of the current density. It is clear that in order to calculate the lifetime during normal operation from accelerated testing, the precise hot electron injection current density must be known, furthermore it must be demonstrated that the same degradation mechanisms hold at very high fields and/or current densities. This result has profound implications for device reliability predictions made using accelerated hot electron measurements and calls into question lifetime predictions made where the effect is not taken into account.