BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

A 10 bit Current-Mode CMOS A/D Converter with a Current Predictor and a Modular Current Reference

This paper describes a 10 bit CMOS current-mode A/D converter with a current predictor and a modular current reference circuit. A current predictor and a modular current reference circuit are employed to reduce the number of comparator and reference current mirrors and consequently to decrease a power dissipation. The 10 bit current-mode A/D converter is fabricated by the 0.6 m n-well double poly/triple metal CMOS technology. The measurement results show the input current range of 16–528 A, DNL and INL of ±0.5 LSB and ±1.0 LSB, conversion rate of 10 M samples, and power dissipation of 94.4 mW with a power supply of 5 V. The effective chip area excluding the pads is 1.8 mm×2.4 mm.     

A Design of a Low-Voltage Current-Mode Fully-Differential Analog CMOS Integrator Using FG-MOSFETs and Its Implementation

In the field of analog signal processing, there is a strong need for low-voltage and low-power integrated circuits. Especially in the mobile communication circuitry, an analog signal processing circuit must be fed by dry batteries of 1–1.5 V. This paper presents a design and implementation of a current-mode fully-differential analog CMOS integrator operable with such a low supply voltage. This integrator is built with a cross-coupled matched pair of 3-input FG(Floating Gate)-MOSFETs, a matched pair of 2-input FG-MOSFETs, and four bias current sources. In this circuit, both a low apparent threshold voltage of FG-MOSFETs and voltage signal summation at the floating gates are effectively utilized to enable the circuit operation with a low supply voltage and to simplify the circuit configuration. The influence of the common-mode signal and noise to the signal processing are minimized by adopting fully-differential structure. The performance of the proposed integrator circuit is predicted by theoretical analysis and by HSPICE simulations. The circuit works as an integrator in the frequency range 4–750 MHz at a 1.5 V supply voltage and dissipates DC power of about 70 W. The proposed circuit was fabricated by a Motorola 1.2 m double-poly CMOS process in the chip fabrication program of VLSI Design and Education Center (VDEC).     

An 8 Bit Current-Mode CMOS A/D Converter with Three Level Folding Amplifiers

An 8 bit current-mode folding and interpolation analog to digital converter (ADC) with three-level folding amplifiers is proposed in this paper. A current-mode three-level folding amplifier is employed not only to reduce the number of reference current sources, but also to decrease a power dissipation within the ADC. The designed ADC fabricated by a 0.8 m n-well CMOS double metal/single poly process occupies the chip area of 2.2 × 1.6. The experimental result shows the power dissipation of 33.6 mW with a power supply of 5 V.     

LV/LP CMOS Four-Quadrant Analog Multiplier Cell in Modified Bridged-Triode Scheme

A new LV/LP CMOS four-quadrant analog multiplier designed in a modified bridged-triode scheme (MBTS) is presented. Its bi-directional bridged structure brings several benefits in terms of good linearity, lower voltage operation/power consumption, less total harmonic distortions and wider frequency response. The fabricated chip in TSMC 0.35 m n-well SPQM CMOS technology has a nonlinearity error less than 42 dB over ±0.5 V input range under a nominal supply voltage of ±1.5 V, and consumes the total power dissipation of 2.7 mW.     

Current monitoring circuit for fault detection in CMOS integrated circuit

This article presents a built-in current sensor (BICS), which detects faults using the current testing technique in CMOS integrated circuits. This circuit employs cross-coupled PMOS transistors, which are used as current comparators. The proposed circuit has a negligible impact on the performance of the circuit under test (CUT). In addition, no extra power dissipation and high-speed fault detection are achieved. It can be applied to deep sub-micron processes. The validity and effectiveness are verified through the HSPICE simulation on circuits with faults. The entire area of the test chip is 116×65 μm². The BICS occupies only 41×17 μm² of the area of the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix 0.35 μm 2-poly-4-metal N-well CMOS process.     

CMOS Analog Implementation of a Discrete-Time 9-Tap FIR Filter with Circular Buffer Architecture

This paper presents the design and simulation of a 9-Tap CMOS Analog Discrete-Time Finite Impulse Response (FIR) Filter system. This unique design features a Circular Buffer Architecture which achieves high sampling rate that can be easily expanded to improve speed and extended to higher order filters. Novel area-efficient four quadrant CMOS analog adder and multiplier circuits are employed to respond for high frequency and wide linear range inputs. The layout for all circuits has been realized using the design tool MAGIC with a 1.2 m CMOS process. The performance for each circuit and the whole system are characterized using HSPICE simulation based on the extracted MAGIC netlist. The 9-tap filter was designed to achieve 5 MHz sampling rate. The implemented design requires a total chip area of 1690.9 m by 2134.2 m and ±5 volt power supply.     

Substrate Noise Simulation Techniques for Analog-Digital Mixed LSI Design

Crosstalk from digital to analog circuits can be causative of operation fails in analog-digital mixed LSIs. This paper describes modeling techniques and simulation strategies of the substrate coupling noise. A macroscopic substrate noise model that expresses the noise as a function of logic state transition frequencies among digital blocks is proposed. A simulation system based on the model is implemented in the mixed signal simulation environment, where performance degradation of the 2nd order ADC coupled to digital noise sources is clearly simulated. These results indicate that the proposed behavioral modeling approach allows practicable full chip substrate noise simulation measures.     

CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design based on current-mode data converters is presented herein. Continuous-time algorithmic converters are chosen to reduce the control circuitry and to obtain a modular design based on a cascade of bit cells. Several circuit structures to implement these cells are presented and discussed. The one that is selected enables a better trade-off speed/power than others previously reported in the literature while maintaining a low area occupation. The resulting multiplier/divider circuit offers a low voltage operation, provides the division result in both analog and digital formats, and it is suitable for applications of low or middle resolution (up to 9 bits) like applications to fuzzy controllers. The analysis is illustrated with Hspice simulations and experimental results from a CMOS multiplier/divider prototype with 5-bit resolution. Experimental results from a CMOS current-mode fuzzy controller chip that contains the proposed design are also included.     

A new true-single-phase-clocking BiCMOS dynamic pipelined logicfamily for high-speed, low-voltage pipelined system applications

New true-single-phase-clocking (TSPC) BiCMOS/BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications are simulated by using HSPICE with 1 μm BiCMOS technology. Simulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and power dissipation/MHz of the pipelined system, which is constructed by the new clock-high-evaluate-BiCMOS dynamic latch logic circuit and clock-low-evaluate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked MOS transistors, are about 2.36 (2.2) times and 1.15 (1.1) times those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V, respectively. Moreover, the chip area of these two BiCMOS pipelined systems is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1 μm BiCMOS technology verifies the speed advantage of the new BiNMOS dynamic logic circuit. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, low-voltage dynamic pipelined system applications     

A Low-Power 100 MHz Analog FIR Filter for PRML Equalization

This paper presents design of a low-power 100 MHz analog FIR filter for PRML equalization used in the read channel of hard disk drives. The chip consists of 16 channels to provide 15-tap FIR filter operation. By using rotating clocks for sample/hold operation with one dummy channel, timing constraints can be relieved, which results in low-power consumption. The chip incorporates the parallel array of sample-and-hold amplifiers for analog delay line. The sample-and-hold amplifier includes the open-loop unity-gain amplifier with gain-control circuit using replica-biasing scheme, which also improves uniformity among amplifiers. It was fabricated in a 0.8-m CMOS technology and consumes power of 200 mW for V power supply voltage.     

LV/LP CMOS Four-Quadrant Analog Multiplier Cell in Modified Bridged-Triode Scheme

A new LV/LP CMOS four-quadrant analog multiplier designed in a modified bridged-triode scheme (MBTS) is presented. Its bi-directional bridged structure brings several benefits in terms of good linearity, lower voltage operation/power consumption, less total harmonic distortions (THD) and wider frequency response. The fabricated chip in TSMC 0.35 m n-well SPQM CMOS technology has a nonlinearity error less than 42 dB over ±0.5 V input range under a nominal supply voltage of ±1.5 V,and consumes the total power dissipation of 2.7 mW.     

Design and Analysis of Built-In Testers for CMOS Switched-Current Circuits

This paper presents the design and analysis of a built-in tester circuit for MOS switched-current circuits used in low-voltage/low-power mixed-signal circuits/systems. The use of the tester can reduce the test length significantly. The developed tester is comprised of a current comparator, a voltage window comparator, and a digital latch. The current comparator is required to have high-accuracy, low-power consumption, simple structure with small chip area, and moderate speed. Results show that the developed current comparator circuit is developed with a small offset current, 0.1 nA, low power consumption, 20 W, and a layout area of 0.01 mm², where the circuit is simulated with the MOSIS SCN 2 m CMOS process parameters and 2 V supply voltage.     

A Locally Adaptive Multimode Photodetector Circuit

Photodetection circuits form the first stage of the artificial image acquisition process. The image acquisition circuits discussed in this paper pertain to circuits fabricated in a standard CMOS process. Such circuits offers advantages such as random access to a pixel, faster readout, integration of processing circuitry on the same die, low voltage and low power dissipation, and lower cost over the conventional Charge Coupled Device (CCD) process. We describe a new locally adaptive multimode photodetector circuit. The advantages of the circuit are local adaptation, wide dynamic range, excellent sensitivity, and large output voltage swing. The circuit was fabricated in the 2 CMOS process through MOSIS. Simulation and experimental results of the circuit are given.     

A single-chip codec with switched-capacitor filters

A single-chip CMOS codec with filters has been developed using charge redistribution and switched-capacitor techniques. Its features are ~30 mm/SUP 2/ small chip area, 35 mW low power dissipation, and small 16 pin package. These are achieved with novel analog circuit techniques for A/D and D/A conversions and clock generation. Measured transmission characteristics meet the system requirements.     

Low-power CMOS digital design with dual embedded adaptive powersupplies

A low-power CMOS design methodology with dual embedded adaptive power supplies is presented. A variable supply-voltage scheme for dual power supplies, namely, the dual-VS scheme, is presented. It is found that the lower supply voltage should be set at 0.7 of the higher supply voltage to minimize chip power dissipation. This knowledge aids designers in the decision of the optimal supply voltages within a restricted design time. An MEPG-4 video codec chip is designed at 2.5 and 1.75 V for internal circuits that are generated from an external power supply of 3.3 V by the dual-VS circuits. Power dissipation is reduced by 57% without degrading circuit performance compared to a conventional CMOS design     

RTD/CMOS nanoelectronic circuits: thin-film InP-based resonanttunneling diodes integrated with CMOS circuits

The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed for InP-based RTDs which are transferred and bonded to CMOS chips. The prototype comparator shows sensitivity in excess of 10⁶ VIA, and achieves error-free performance in functionality testing. An optimized integration process, under development, can yield high-speed, low power circuits by lowering the high parasitic capacitance associated with the prototype circuit     

Low Power Design of High Speed CMOS Pulse Stream Neuron Circuit

The greatinformation processing power of human being' s neural systems has attract-ed a lotof attention of those who are dedicated to the implementation of Artificial NeuralNetworks(ANNs) ,which are expected to be of the same computat...     

一种用于3.3Gbps低功耗高速互连的连续时间自适应模拟均衡器*

设计了适用于多种高速通信指标(USB2.0, PCI-E,Rapid IO)的CMOS模拟均器。通过合并低频和高频支路以降低两个支路的延迟效应,同时均衡滤波器具有比较大的输入阻抗,这有利于通过级联方式来进一步提高高频增益。本文所实现的电路结构在25dB的PCB线路衰减条件下,能够均衡频率范围从1Gbps到3.3Gbps的信号。偏置电路采用复制电路技术,有利于方便的调整主要工作模块的直流工作点。为了抑制前级输出共模对后级电路的影响,在信号的输入端引入了交流耦合。该芯片在0.18um 1P6M工艺下进行了流片验证,整体芯片面积为0.6 x 0.57 mm². 测试结果显示,该模拟均衡器能够在25dB FR4 PCB信道衰减下,对速率为3.3Gbps的信号实现自适应均衡,整体功耗大约为23.4mw.     

Low-Voltage Analog Circuits Based on Wideband Capacitive Coupling

A technique for wideband low-voltage analog circuit operation based on capacitive signal coupling is discussed. Circuits based on this technique do not show the GB degradation of other low-voltage approaches based on floating-gate transistors. The technique is validated with simulations of a new CMOS mixer and experimental results of a test chip in a 0.5 m CMOS technology.