用线性电压扫描的电容-时间瞬态测定少子产生寿命

本文建议用耗尽的线性扫描电压扫描MOS电容样品。扫描开始前MOS电容被置于强反型态,以消除表面产生的影响。根据扫描所得的电容-时间瞬态曲线,可确定样品中少于产生寿命。实验表明,对于同一个MOS电容样品,不同电压扫描率下得到的结果有很好的一致性,且与饱和电容法的结果相符合。     

长产生寿命的快速测量方法

本文提出了线性电压扫描下长产生寿命的快速测量方法。该法具有不需使C-t瞬态曲线达到饱和、数据处理简单、且不需知道样品的掺杂浓度等优点。     

一种适合于计算机辅助测量的产生寿命确定方法

提出了MOS电容线性电压扫描法产生寿命测量的新方法。通过在MOSC t曲线上读取n个不同时刻的电容值 ,计算出相应的产生寿命值 ,其精度随读取点的增加而提高 ,该方法也特别适合于计算机辅助测量系统。     

非均匀掺杂衬底MOS结构少子产生寿命的测量

本文分析了非均匀掺杂衬底MOS电容对线性扫描电压的瞬态响应,提出了三角波C-V技术测量非均匀掺杂MOs电容少子产生寿命的方法.该方法简单、且不需知道衬底的掺杂分布.     

适用于少子产生寿命CAM的线性电压扫描法

提出了 MOS电容线性电压扫描法测量半导体少子产生寿命的新方法。通过在 MOS C-t瞬态曲线上读取 n个不同时刻的电容值 ,确定出相应的少子产生寿命值。该方法基于最小二乘法原理 ,可有效地消除测量误差的影响 ,其精度随读取点的增加而提高 ,特别适合于少子产生寿命的计算机辅助测量。     

场扫描上下线性补偿电路的理论依据

电视机的场扫描由于多种原因产生非线性失真,这些失真总的效果是使锯齿波产生上凸,如图1。为了校正这个非线性失真,必须让扫描信号产生一个反向下四的预失真,如图2。实现这个预失真,一般采用上线性补偿电路(图3)和下线性补偿电路(图4)。改变R_2可以产生预失真效果,设输入电压u_1为线性锯齿电压(如图5)。扫描     

由MOS结构对线性电压扫描的瞬态响应测定产生寿命和表面产生速度

本文指出由MOS结构栅电流和高频电容对线性电压扫描的瞬态响应,可同时测定产生寿命和表面产生速度.对一些样品进行了测试,并与饱和电容法和 dC/dV法作了比较.     

饱和电容法快速确定体产生寿命和表面产生速度

本文分析了线性电压扫描下MOS电容的C-t瞬态响应,在此基础上,发展了一种快速确定体产生寿命和表面产生速度的新方法.该方法实验手续和计算均较简单,适于在需要确定很多样品的体产生寿命和表面产生速度场合下应用.     

DAC8831在恒电位仪电压扫描中的应用

为实现恒电位仪给定电压低速扫描时电压高精度、线性好及降低设计成本,设计了一种简单可行的电压扫描系统。该系统以STC89C51为主控器件,通过单片机IO口模拟SPI通信接口来控制16位数模转换芯片DAC8831,DAC8831根据预先输入的D/A控制字将数字信号转换成模拟电压,借助于外部运放实现双极性电压输出。实验结果表明,该系统输出电压范围为-4～+4 V、电压分辨率可达0.125 mV,低速电压扫描线性度好,具有应用灵活、外围电路简单,可靠性高的特点。     

基于线性电源的高压放大器

介绍基于线性电源的高压放大器的实现，他具有宽范围的电压输出、波形质量好的特点，降低了对器件耐压的要求，可用于实现压电陶瓷驱动器、高电压扫描电源以及高压功率源等应用。     

Determining the generation lifetime in a MOS capacitor using linear sweep techniques

A comparison between two linear sweep techniques for generation lifetime profiling is reviewed here. These semiconductor characterization techniques find widespread application because of their availability in commercial equipment and ability to reduce the measurement time. It is shown experimentally that parameters such as generation lifetime and surface generation velocity determined by linear sweep techniques agree well with those obtained from pulsed MOS capacitor measurement.     

Theory of field enhanced non-equilibrium transients in MIS devices under a linear voltage sweep

A theoretical method has been formulated to simulate the field enhanced non-equilibrium transients in MIS devices under linear voltage sweep. Unlike previous theories the carrier emission probability is assumed to be field-dependent. The one dimensional Poole-Frenkel model and Hartke model are used to the carrier emission probability of traps dependent on the applied electric field. These models are quite available for coulombic centers. A reasonable model of the effective generation region is applied to analyse the transients, and the non-steady-state generation effect is taken into account. The I/V characteristics at different voltage sweep rates have been obtained. The effect of field enhanced carrier emission and the effect of non-steady-state generation on I/V characteristics are discussed in detail.     

Determination of generation lifetime fromC-t transients under linear voltage ramp bias

When a linear voltage ramp is applied to the gate of a MOS capacitor, a capacitancetime (C-t) transient is observed. The MOS capacitor is biased into strong inversion before applying the voltage ramp in order to eliminate surface generation. FromC-t transient curve obtained experimentally the minority carrier generation lifetime in semiconductor can be determined. The experimental results show that for the same sample the lifetimes extracted fromC-t curves under varying voltage sweep rates are close each other, and they are consistent with the lifetimes extracted by saturation capacitance method.     

Experimental response of MOS devices to a fast linear voltage ramp

An experimental investigation is undertaken of the response of an MOS device to a linear voltage ramp of such speed as to take the device into non-equilibrium, but to allow sufficient generation to take place during the voltage sweep to provide structure in the C-V curves which can be analysed quantitatively. The main aim has been to investigate the effect of sweep rate per se, but additional data is presented which considers the voltage dependence of the space-charge width, the maximum sweep rate for quasi-equilibrium, and the effect of temperature. It is demonstrated that the technique provides quantitative information on bulk traps and a qualitative measure of the relative role of interface traps in the generation process. Transitions are observed between quasi-equilibrium and non-equilibrium which are a function of sweep rate. This is in contrast to the pulse technique, where the response is of a purely transient nature.     

DETERMINATION OF GENERATION LIFETIME FROM C-t TRANSIENTS UNDER LINEAR VOLTAGE RAMP BIAS

When a linear voltage ramp is applied to the gate of a MOS capacitor,a capacitance-time(C-t)transient is observed.The MOS capacitor is biased into strong inversion before apply-ing the voltage ramp in order to eliminate surface generation.From C-t transient curve obtainedexperimentally the minority carrier generation lifetime in semiconductor can be determined.Theexperimental results show that for the same sample the lifetimes extracted from C-t curves un-der varying voltage sweep rates are close each other,and they are consistent with the lifetimesextracted by saturation capacitance method.     

基于重复测试和栅压应力测试的石墨烯晶体管回滞特性的研究

The current transport characteristic is studied systematically based on a back-gate graphene field effect transistor, under repeated test and gate voltage stress. The interface trapped charges caused by the gate voltage sweep process screens the gate electric field, and results in the neutral point voltage shift between the forth and back sweep direction. In the repeated test process, the neutral point voltage keeps increasing with test times in both forth and back sweeps, which indicates the existence of interface trapped electrons residual and accumulation. In gate voltage stress experiment, the relative neutral point voltage significantly decreases with the reducing of stress voltage, especially in -40 V, which illustrates the driven-out phenomenon of trapped electrons under negative voltage stress.     

基于不同测量手段的纳米晶器件的存储特性

对纳米晶器件,尤其是MOS电容进行了横截面TEM分析和不同条件下的电学特性(C-V特性)测量,包括+/-BT分析. 揭示了系统的纳米晶存储物理机制,例如电荷俘获、界面态填充和温度特性. 研究结果表明,高温、大电压摆幅和偏置情况下,器件编程窗口的恶化和阈值电压的漂移与多数载流子的种类有关.