Low frequency noise in 0.12 μm partially and fully depleted SOI technology

Low frequency noise characterization of 0.12 μm silicon-on-insulator (SOI) CMOS technology is for the first time performed for partially and fully depleted N-MOSFETs. Static performances of the experimental devices are first presented, then we address the drain current fluctuations in both linear and saturation regimes. Taking into consideration the usually admitted 1/f noise models in MOS devices and their applicability in our case, we point out an enhancement of the extracted trap densities for both architectures compared to previously obtained results in 0.25 μm SOI CMOS technology. As regards drain current spectral densities in saturation mode, we notice some peculiarities occurring for the Kink-related excess noise.     

Impact of gate oxide nitridation process on 1/f noise in 0.18 μm CMOS

The aim of this paper is to study the impact of the nitridation techniques on the 1/f noise performances of dual gate 0.18 μm CMOS transistors. Nitrogen is often introduced to prevent boron penetration in ultrathin oxides especially when BF₂ is used for the PMOS junction implantation, but as a result the MOS transistor exhibits higher 1/f noise because of the increased fixed trap density. We show how the nitridation process can be improved in terms of 1/f noise characteristics, in a fully integrated technology. Projections of the 1/f noise behaviour for different technologies are also shown, to emphasise how the 1/f noise becomes an issue when other downscaling properties are considered for analog/RF CMOS applications.     

Design of an Optimized 2.5 GHz CMOS Differential LC Oscillator with Nonlinear Analysis for MOS Varactor

The oscillation amplitude and supply current relations for a differential CMOS oscillator are derived by using an analytic method. A simplified model to predict the phase noise performance of the oscillator is developed. The large signal analysis of a nonlinear inversion mode MOS varactor is presented. The derived expressions can help to design an optimized oscillator in terms of minimum phase noise and power consumption. The validity of the method has been verified by designing an LC CMOS oscillator in a 0.25 μm CMOS technology. The predictions are in good agreement with simulation results over a wide range of supply voltage.     

Statistical modeling of MOS devices for parametric yield prediction

In the manufacturing of VLSI circuits, engineering designs should take into consideration random variations arising from processing. In this paper, statistical modeling of MOS devices is reviewed, and effective and practical models are developed to predict the performance spread (i.e., parametric yield) of MOS devices and circuits due to the process variations. To illustrate their applications, the models are applied to the 0.25 μm CMOS technology, and measured data are included in support of the model calculations.     

STI process steps for sub-quarter micron CMOS

This paper presents Shallow Trench Isolation (STI) process steps for sub-1/4 μ CMOS technologies. Dummy active areas, vertical trench sidewalls, excellent gap filling, counter mask etch step and CMP end point detection, have been used for a 0.18 μm CMOS technology. Electrical results obtained with a 5.5 nm gate oxide thickness show good isolation down to 0.3 μm spacing. Good transistor performances have been demonstrated.     

Hot-carrier reliability of 20V MOS transistors in 0.13 μm CMOS technology

This paper presents results of reliability investigation of 20 V N-Drift MOS transistor in 0.13 μm CMOS technology. Due to high performances required for CMOS applications, adding high voltage devices becomes a big challenge to guarantee the reliability criteria. In this context, new reliability approaches are needed. Safe Operating Area are defined for switch, V_ds limited and V_gs limited applications in order to improve circuit designs. For V_ds limited applications, deep doping dose effects in drift area are investigated in correlation to lifetime evaluations based on device parameter shifts under hot carrier stressing. To further determine the amount and locations of hot carriers injections, accurate 2D technological and electrical simulations are performed and permit to select the best compromise between performance and reliability for N-Drift MOS transistor.     

High-voltage solutions in CMOS technology

This paper presents trends on CMOS high-voltage techniques for power integrated circuits (PICs). Several fully CMOS compatible drain engineering techniques will be presented. Experimental devices were fabricated in standard CMOS processes from three different lithography generations (2, 0.7 and 0.5 μm) without resorting to any extra processing steps. MOS devices layout specificity towards performance improvement, namely breakdown, parasitic effects and degradation, will be emphasized.A recently developed technique used to enlarge high-voltage devices safe-operating area and reduce leakage current will also be presented due to the very promising experimental results.Comparison with more sophisticated and expensive technologies still reveals CMOS as a highly accessible and versatile technology for future PICs.     

Impact of latch phenomenon on low-frequency noise in SOI MOSFETs

The low-frequency noise in fully (FD) and partially (PD) depleted SOI MOSFETs is experimentally investigated for channel lengths down to 0.1 μm. The noise is discussed in terms of carrier number and mobility fluctuations for a wide range of SOI structures. Furthermore, the influence of the latch effect on low-frequency noise is analyzed. It is found that the flicker noise is mainly caused by the carrier number fluctuations due to the dynamic trapping of electrons (or holes) by oxide interface traps in all the SOI devices. However, an excess noise is also obtained in the presence of a parasitic bipolar action.     

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.     

Integration challenges in sub-0.25 μm CMOS-based technologies

Market demands, which require increased functionality at lower costs are driving the development of high performance CMOS technologies with very high integration density. These demands are pushing the continuous scaling down of technologies and are resulting in a progressive acceleration of the rate of introduction of new technology generations.Current research and development activities in CMOS technology are focused on scaling CMOS technologies below 0.25 μm dimensions. While some of the process modules can be scaled down in a conventional way, in some cases severe limitations are reached and it is necessary to introduce major modifications to the process flow.In this paper we will present an overview of the main considerations to be kept in mind when scaling down to a 0.18 or 0.13 μm CMOS technology generation.     

Low-frequency noise measurements on submicrometre n-channel and p-channel MOSFETs at various operating regions

Silicon founders give in their MOS transistor card models some low-frequency noise parameters for SPICE-based circuit simulators corresponding to pure 1/f ^a or flicker noise, with a very close to unity. MOS transistors used in analogue circuit applications are usually devices with large channel length and width. In low-noise applications, methods such as correlated double sampling are used to suppress the low frequency noise generated by them. Nevertheless, the transistors presently are submicrometre devices exhibiting very different low-frequency noise behaviour. In this paper, experimental low-frequency noise results obtained at room temperature on NMOS and PMOS transistors fabricated using a 0.7 μm process are presented. Both large and small devices on the same process are considered. All regions of operation of transistors are considered. We show that the low-frequency noise behaviour of small area MOSFETs is very different from that of large area devices and that the spectrum is the summation of Lorentzian spectra generated by the switching of individual active traps.     

A novel low-power full-adder cell for low voltage

This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the time-consuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster.     

3D CMOS devices in recrystallized silicon

A 2 μm scale three-dimensional CMOS process has been developed which allows the fabrication of MOS devices in two independent active device layers. NMOS transistors have been fabricated in the substrate and CMOS devices, including inverters and ring oscillators, in a thin laser-recrystallized polysilicon layer. The processing parameters were determined carefully in order to obtain a monocrystalline top layer and to avoid any damage to the underlying devices already existing.     

A Systematical Approach for Noise in CMOS LNA

A systematic approach is used to analyze the noise in CMOS low noise amplifier(LNA),including channel noise and induced gate noise in MOS devices.A new analytical formula for noise figure is proposed.Based on this formula,the impacts of distributed gate resistance and intrinsic channel resistance on noise performance are discussed.Two kinds of noise optimization approaches are performed and applied to the design of a 5.2GHz CMOS LNA.     

Electrostatic discharge (ESD) protection for CMOS output buffers in scaled-down VLSI technology

To provide area-efficient output ESD protection for the scaled-down CMOS VLSI, a new output ESD protection is proposed. In the new output ESD protection circuit, there are two novel devices, the PTLSCR (PMOS-trigger lateral SCR) and the NTLSCR (NMOS-trigger lateral SCR). The PTLSCR is in parallel and merged with the output PMOS, and the NTLSCR is in parallel and merged with the output NMOS, to provide area-efficient ESD protection for CMOS output buffers. The trigger voltages of PTLSCR and NTLSCR are lowered below the breakdown voltages of the output PMOS and NMOS in the CMOS output buffer. The PTLSCR and NTLSCR are guaranteed to be turned on first before the output PMOS or NMOS are broken down by the ESD voltage. Experimental results have shown that the PTLSCR and NTLSCR can sustain over 4000 V (700 V) of the human-body-model (machine-model) ESD stresses within a very small layout area in a 0.6 μm CMOS technology with LDD and polycide processes. The noise margin of the proposed output ESD protection design is greater than 8 V (lower than −3.3 V) to avoid the undesired triggering on the NTLSCR (PTLSCR) due to the overshooting (undershooting) voltage pulse on the output pad when the IC is under normal operating conditions with 5 V VDD and 0 V VSS power supplies.     

CMOS低噪声放大器中噪声的系统研究方法

采用系统研究方法来分析包括MOS器件的沟道噪声和感应栅噪声在内的CMOS低噪声放大器中的噪声,并提出了一个新的噪声系数解析式.基于此解析式,讨论了分布栅电阻和内部沟道电阻对噪声性能的影响.对噪声性能进行了两种不同的优化,并应用于5.2GHz CMOS低噪声放大器的设计.     

The influence of stud bumping stress on device degradation in scaled MOSFETs

This paper presents the effect of area bumping on device degradation in scaled metal-oxide-semiconductor field-effect transistors (MOSFETs). We have investigated the gate channel length dependence of g_m degradation after stud bumping above the MOSFETs and changes in the charge pumping currents for those devices. The von Mises’s equivalent stress is used to simulate the distribution of mechanical stress at the gate edges. From the relationship between the distribution of the von Mises’s equivalent stress and the change in the charge pumping currents after stud bumping, we show that stress concentrates within 0.1 μm of the gate edges. Furthermore, by estimating the amount of increased interface-state density we predicted that stud bumping stress greatly influences the device degradation of scaled MOS devices.     

A high-linear wide-tunable CMOS transconductor for video frequency applications

In this paper a new CMOS transconductor structure based on a g_m-boosted degenerated differential pair is presented for applications in the video frequency range. The proposed circuit combines two techniques, a switchable array of source degenerating MOS resistors and a programmable output current mirror, in order to widen the G_m tuning range while maintaining linearity. Degeneration MOS resistors are made common-mode voltage independent thanks to a simple control circuit. Post-layout simulation results from a 0.35 μm design supplied at 3.3 V show a wide tuning range (10–100 MHz), good linearity (−58.4 dB for an output signal voltage of 1.1 V_p–p) and low excess phase (<0.5° over the whole tuning range).     

A DOL CMOS static memory cell

A new CMOS static memory cell, called the double-lambda diode (DOL), is described. It offers the speed and the power dissipation advantages of conventional CMOS static memory cells at half the area. The cell uses complementary depletion MOS devices. The processing technology is based on a twin-tub CMOS process. Using 2.5 /spl mu/m design rules the cell area is 500 /spl mu/m/SUP 2/. In addition, a 300 /spl mu/m/SUP 2/ single-lambda diode (SIL) cell using a poly resistor as a load is discussed. Comparisons of these cells with other MOS static memory cells are presented.     

Comparison of low frequency noise and high frequency performances of double and simple polysilicon Bi-CMOS BJT

The issue of this paper concerns 0.35 μm Bi-CMOS double polysilicon bipolar transistors and 0.5 μm Bi-CMOS simple polysilicon bipolar transistors. Low-frequency noise measurements are performed. Noise spectral densities are analysed versus bias and geometry. From these noise measurements, base and emitter series resistances are extracted. A comparison of both technologies is done. Though double polysilicon transistors have a more complex structure than the simple polysilicon ones, they exhibit similar or even better performances. Indeed, DC characteristics and noise levels are equivalent for both technologies. Double polysilicon transistors exhibit a reduction of the base resistance and a significant improvement of the transition frequency f_T is obtained.