Macromodeling of nonlinear digital I/O drivers

In this paper, a modeling technique using spline functions with finite time difference approximation is discussed for modeling moderately nonlinear digital input/output (I/O) drivers. This method takes into account both the static and the dynamic memory characteristics of the driver during modeling. Spline function with finite time difference approximation includes the previous time instances of the driver output voltage/current to capture the output dynamic characteristics of digital drivers accurately. In this paper, the speed and the accuracy of the proposed method is analyzed and compared with the radial basis function (RBF) modeling technique, for modeling different test cases. For power supply noise analysis, the proposed method has been extended to multiple ports by taking the previous time instances of the power supply voltage/current into account. The method discussed can be used to capture sensitive effects like simultaneous switching noise (SSN) and cross talk accurately when multiple drivers are switching simultaneously. A comparison study between the presented method and the transistor level driver models indicate a computational speed-up in the range of 10-40 with an error of less than 5%. For highly nonlinear drivers, a method based on recurrent artificial neural networks (RNN) is discussed.     

Parametric macromodels of differential drivers and receivers

This paper addresses the modeling of differential drivers and receivers for the analog simulation of high-speed interconnection systems. The proposed models are based on mathematical expressions, whose parameters can be estimated from the transient responses of the modeled devices. The advantages of this macromodeling approach are: improved accuracy with respect to models based on simplified equivalent circuits of devices; improved numerical efficiency with respect to detailed transistor-level models of devices; hiding of the internal structure of devices; straightforward circuit interpretation; or implementations in analog mixed-signal simulators. The proposed methodology is demonstrated on example devices and is applied to the prediction of transient waveforms and eye diagrams of a typical low-voltage differential signaling (LVDS) data link.     

Low-power CMOS/BiCMOS drivers and receivers for on-chipinterconnects

Novel low-voltage swing CMOS and BiCMOS driver/receiver circuits for low-power VLSI applications are proposed. Interconnect wire drivers with low output signal swing are employed. Special receivers provide single and double level conversion while minimizing the total driver/receiver transmission delay. These level converters have no DC power dissipation. At 3.3 V power supply voltage, the proposed circuits consume less power without delay penalty. The power saving is observed to be as high as 30%. At lower supplies further power and delay improvements are observed     

A non-iterative continuous model for switching window computation with crosstalk noise

Proper modeling of switching windows leads to a better estimate of the noise-induced delay variations. In this paper, we propose a new non-iterative continuous switching model. The proposed new model employs an ordering technique combined with the principle of superposition of linear circuits. The principle of superposition considers the impact of aggressors one after the other. The ordering technique avoids convergence and multiple solution issues in many practical cases. Our model surpasses the accuracy of the traditional discrete model and the speed of fixed point iteration method.     

A comprehensive delay macro modeling for submicrometer CMOS logics

The increasing need for high-performance, cost-effective, application-specific integrated circuits, associated to the reduction of design cycle time, compels designers to manage and optimize the circuit speed performance at each step of the design flow. Circuits are usually designed at gate level; the gate selection or sizing and their placement are driven by estimated delay, hence the need for accurate estimations at the logical level. In the submicrometer range, the gap between gate-level logical estimations and transistor-level electrical simulations dramatically increases. We propose here a comprehensive analytical modeling of the speed performance of CMOS gates with an accuracy comparable to electrical simulators. A design-oriented expression of delay is first developed for CMOS inverters, considering input slope, input-to-output capacitance coupling, and short-circuit current effects. The extension to more complex gates is proposed using a serial array reduction technique taking account of the gate input dependency and the input-slope-induced nonlinearity. Validations are obtained over a large range of design, load, and input slope conditions by comparison with SPICE simulations (level 6 with 0.65-μm foundry specified card model) used as a reference     

Time domain modelled ADC BIST with ramp noise projection

This paper proposes a time domain modelled built-in self-test (BIST) with ramp noise projection and their effects on analogue to digital converter (ADC) in testing. A self-biased linear ramp generator has been proposed for high precision testing. Threshold inversion quantization (TIQ) comparator based fast switching flash ADC has considered under test. A time domain model of output response analysis technique has been proposed to calibrate the linearity errors of the converter. An ADC has been validated with different input frequencies to characterize the harmonic distortion and average delay of the system. The proposed testing technique requires less time to measures the uncertainties of the ADC since the full computation is performed within one ramp cycle. The testing results of the proposed BIST technique are aimed to characterize, validate and compare to the best results of the existing ADC BIST techniques for test accuracy.     

Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation

One of the main requirements for generating test patterns for analog and mixed-signal circuits is fast fault simulation. Analog fault simulation is much slower than the digital equivalent. This is due to the fact that digital circuit simulators use less complex algorithms compared with transistor-level simulators. Two of the techniques to speed up analog fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioral/macro modeling, whereby parts of the circuit are modeled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioral fault modeling to speed-up fault simulation for analog circuits.     

A multistage ATM switch with interstage buffers

Asynchronous transfer mode (ATM) is the transport technique for the broadband ISDN recommended by CCITT (I.121). Many switches have been proposed to accommodate the ATM that requires fast packet switching capability.^1-8 The proposed switches for the broadband ISDN can be classified as being of input queueing or output queueing type. Those of the input queueing type have a throughput performance which is approximately 58 per cent that of the output queueing type. However, output queueing networks require larger amounts of hardware than input queueing networks. In this paper, we propose a new multistage switch with internal buffering that approaches a maximum throughput of 100 per cent as the buffering is increased. The switch is capable of broadcasting and self-routeing. It consists of two switching planes which consist of packet processors, 2 x 2 switching elements, distributors and buffers located between stages and in the output ports. The internal data rate of the proposed switch is the same as that of the arriving information stream. In this sense, the switch does not require speed-up. The switch has log₂ N stages that forward packets in a store-and-forward fashion, thus incurring a latency of log₂ N time periods. Performance analysis shows that the additional delay is small.     

A Hybrid Simulation Approach for Fast and Accurate Timing Analysis of Multi-Processor Platforms Considering Communication Resources Conflicts

In the early design phase of embedded systems, discrete-event simulation is extensively used to analyse time properties of hardware-software architectures. Improvement of simulation efficiency has become imperative for tackling the ever increasing complexity of multi-processor execution platforms. The fundamental limitation of current discrete-event simulators lies in the time-consuming context switching required in simulation of concurrent processes. In this paper, we present a new simulation approach that reduces the number of events managed by a simulator while preserving timing accuracy of hardware-software architecture models. The proposed simulation approach abstracts the simulated processes by an equivalent executable model which computes the synchronization instants with no involvement of the simulation kernel. To consider concurrent accesses to platform shared resources, a correction technique that adjusts the computed synchronization instants is proposed as well. The proposed simulation approach was experimentally validated with an industrial modeling and simulation framework and we estimated the potential benefits through various case studies. Compared to traditional lock-step simulation approaches, the proposed approach enables significant simulation speed-up with no loss of timing accuracy. A simulation speed-up by a factor of 14.5 was achieved with no loss of timing accuracy through experimentation with a system model made of 20 functions, two processors and shared communication resources. Application of the proposed approach to simulation of a communication receiver model led to a simulation speed-up by a factor of 4 with no loss of timing accuracy. The proposed simulation approach has potential to support automatic generation of efficient system models.     

Study on multiple receiver systems in non-line-of-sight ultraviolet communication systems

In this article, multiple receiver effects in a non-line-of-sight （NLOS） ultraviolet （UV） communication system is studied. The idea of using multiple receivers for diversity reception is known as a practical, effective and widely applied technique in wireless communications. The current approach is to use multiple antennas at the receiver in order to improve the quality of the received signal. A method of modeling and simulation is proposed to depict the principle and feasibility of the multiple receiver adopted in UV communication. The study provides an insight to the channel characteristics and achievable capabilities of ultraviolet communication systems with multiple receivers. It provides guidelines for practical system design with discussions on trade off between the receiver gain and the additional cost.     

Automated energy calculation and estimation for delay-insensitive digital circuits

With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes a procedure to simulate a transistor-level design using a VHDL testbench, and then presents a fast and efficient energy estimation approach for delay-insensitive (DI) systems, based on gate-level switching. Specifically, the VHDL testbench reads the transistor-level design's outputs and supplies the inputs accordingly, also allowing for automatic checking of functional correctness. This type of transistor-level simulation is absolutely necessary for asynchronous circuits because the inputs change relative to handshaking signals, which are not periodic, instead of changing relative to a periodic clock pulse, as do synchronous systems. The method further supports automated calculation of power and energy metrics. The energy estimation approach produces results three orders of magnitude faster than transistor-level simulation, and has been automated and works with standard industrial design tool suites, such as Mentor Graphics and Synopsys.Both methods are applied to the NULL Convention Logic (NCL) DI paradigm, and are first demonstrated using a simple NCL sequencer, and then tested on a number of different NCL 4-bit×4-bit unsigned multiplier architectures. Energy per operation is automatically calculated for both methods, using an exhaustive testbench to simulate all input combinations and to check for functional correctness. The results show that both methods produce the desired output for all circuits, and that the gate-level switching approach developed herein produces results more than 1000 times as fast as transistor-level simulation, that fall within the range obtained by two different industry-standard transistor-level simulators. Hence, the developed energy estimation method is extremely useful for quickly determining how architecture changes affect energy usage.     

Analytical model for switching transitions of submicron CMOS logics

We propose a new analytical model for the switching characteristics of CMOS logics. Our new model, named the Switching Response of CMOS logic by Convolution approach (SRC), can successfully produce the output waveforms under any switching conditions with simple analytical expressions. SRC modeling is a process of transforming CMOS logic into a linear system. This model provides procedures to determine the transfer function and the driving function (input of linear system) of the linear system from given CMOS logic, and then an output waveform, expressed as a third-order equation, is obtained by the convolution of two functions. All parameters in this model are determined in a straightforward manner from given device characteristics and layout geometry without empirical or fitting processes and presimulations. In addition, a delay equation is developed based upon the SRC model. With this delay equation, the delay can be predicted within a few percent differences compared to SPICE simulation results for the wide range of input transition time and output loading capacitance     

Soft‐output MMSE V‐BLAST receiver with MMSE channel estimation under correlated Rician fading MIMO channels

For wireless multiple‐input multiple‐output (MIMO) communications systems, both channel estimation error and spatial channel correlation should be considered when designing an effective signal detection system. In this paper, we propose a new soft‐output MMSE based Vertical Bell Laboratories Layered Space‐Time (V‐BLAST) receiver for spatially‐correlated Rician fading MIMO channels. In this novel receiver, not only the channel estimation errors and channel correlation but also the residual interference cancellation errors are taken into consideration in the computation of the MMSE filter and the log‐likelihood ratio (LLR) of each coded bit. More importantly, our proposed receiver generalizes all existing soft‐output MMSE V‐BLAST receivers, in the sense that, previously proposed soft‐output MMSE V‐BLAST receivers can be derived as the reduced forms of our receiver when the above three considered factors are partially or fully simplified. Simulation results show that the proposed soft‐output MMSE V‐BLAST receiver outperforms the existing receivers with a considerable gain in terms of bit‐error‐rate (BER) performance. Copyright © 2011 John Wiley & Sons, Ltd.     

Top-down design methodology of a multi-bit continuous-time delta–sigma modulator

Transistor-level simulation of complex systems involving analog and digital parts is a time-consuming task. The growing interaction of analog and digital devices calls for the use of top-down design methodologies, resulting in behavioral modeling at different levels of abstraction. In this article, an advanced design methodology using a combination of behavioral models and transistor-level models is presented. This methodology is very interesting for complex mixed-signal IC design, improving the design flexibility and reducing the simulation time. To validate the proposed methodology, a continuous-time delta–sigma modulator based on a high-speed low-resolution quantizer is modeled, taking into account their nonidealities such as excess loop delay, clock jitter and feedback DAC element mismatch. The main features of the multi-bit quantizer are 3-bit resolution with 4 GHz sampling rate and FOM of about 7 pJ/conv. This modulator samples signals at high-IF, performing directly the analog-to-digital conversion in the modern RF front-end receivers.     

Precise CMOS current sample/hold circuits using differential clockfeedthrough attenuation techniques

New CMOS current sample/hold (CSH) circuits capable of overcoming the accuracy limitations in conventional circuits without significantly reducing operating speed are proposed and analyzed. A novel differential clock feedthrough attenuation (DCFA) technique is developed to attenuate the signal-dependent clock feedthrough errors. Unlike conventional techniques, the DCFA circuit allows the use of dynamic mirror techniques, and results in no additional finite output resistance errors or device mismatch errors. The test chip of the proposed fully differential CSH circuit with multiple outputs has been fabricated in 1.2-μm CMOS technology. Using a single 5-V power supply, experimental results show that the signal-dependent clock feedthrough error current is less than ±0.4 μA for the input currents from -550 μA to 550 μA. The acquisition time for a 900-μA step transition to 0.1% settling accuracy is 150 ns. For a 410-μA_p-p input at 250 MHz with the fabricated fully-differential CSH circuit clocked at 4 MHz, a total harmonic distortion of -60 dB, and a signal-to-noise ratio of 79 dB have been obtained. The active chip area and power consumption of the fabricated CSH circuit are 0.64 mm² and 20 mW, respectively. Both simulation and experimental results have successfully verified the functions and performance of the proposed CSH circuits     

Soft error modeling and remediation techniques in ASIC designs

Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain uncertainty bounds on estimated error propagation probability (EPP) values used in our SER modeling framework. Comparison of this method with the Monte-Carlo fault injection and simulation approach confirms the accuracy and speed-up of the presented technique for both the computed EPP values and uncertainty bounds.Based on our SER estimation framework, we also present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for the entire logic-level design while minimizing area and delay penalties. Experimental results confirm that these techniques are able to significantly reduce soft error rate with modest area and delay overhead.     

A novel approach to high-level switching activity modeling withapplications to low-power DSP system synthesis

We address high-level synthesis of low-power digital signal processing (DSP) systems by using efficient switching activity models. We present a technology-independent hierarchical scheme that can be easily integrated into current communications/DSP CAD tools for comparing the relative power/performance of two competing DSP designs without specific knowledge of transistor-level details. The basic building blocks considered for such systems are a full adder, a half adder, and a one-bit delay. Estimates of the switching activity at the output of these primitives are used to model the activity in more complex building blocks of DSP systems. The presented hierarchical method is very fast and simple. The accuracy of estimates obtained using the proposed approach is shown to be within 4% of the results obtained using extensive bit-level simulations. Our approach shows that the choice of multiplier/multiplicand is important when using array multipliers in a datapath. If the input signal with smaller mean square value is chosen as the multiplicand, almost 20% savings in switching activity can be achieved. This observation is verified by an analog simulation using a 16 × 16 bit array multiplier implemented in a 0.6-μ process with 3.3 V supply voltage     

Linear space-time multiuser detection for multipath CDMA channels

We consider the problem of detecting synchronous code division multiple access (CDMA) signals in multipath channels that result in multiple access interference (MAI). It is well known that such challenging conditions may create severe near-far situations in which the standard techniques of combined power control and temporal single-user RAKE receivers provide poor performance. To address the shortcomings of the RAKE receiver, multiple antenna receivers combining space-time processing with multiuser detection have been proposed in the literature. Specifically, a space-time detector based on minimizing the mean-squared output between the data stream and the linear combiner output has shown great potential in achieving good near-far performance with much less complexity than the optimum space-time multiuser detector. Moreover, this space-time minimum mean-squared error (ST-MMSE) multiuser detector has the additional advantage of being well suited for adaptive implementation. We propose novel trained and blind adaptive algorithms based on stochastic gradient techniques, which are shown to approximate the ST-MMSE solution without requiring knowledge of the channel. We show that these linear space-time detectors can potentially provide significant capacity enhancements (up to one order of magnitude) over the conventional temporal single-user RAKE receiver     

Multiple-input and -output OR/AND circuits for VLSI GaAs IC's

OR/AND circuits with multiple input and output have been demonstrated experimentally for low-power 2K and 6K GaAs gate arrays with two levels of logic at approximately a 155-percent increase in speed and power product. The proposed multiple-logic levels process in parallel some complex logic functions with only one gate delay. Two proposed bootstrap techniques have shown an improvement of typically 12 percent in speed without an increase in power for low-power applications. In coupling these OR/AND circuits with the allowable buffered stage and the bootstrap enhancements, one can obtain good device performance over a spectrum of SSI to VLSI in the SDFL circuit family.     

Kernel-based template attacks of cryptographic circuits using static power

Side-channel attacks using static power have been shown to be successful against cryptographic circuits in different environments. This class of attacks exploits the power leakage when the circuit is in a static state, during which the power leakage is expected to be a fixed value. Due to the low signal-to-noise ratio of static power, usually more traces are needed for a static power attack to reach the same success rate as a dynamic power attack. The probabilistic distribution pattern of static power varies significantly in different devices, which further poses challenges to the accurate modeling of static power. In this paper we propose non-parametric template attacks which use a kernel methodology to improve the accuracy of modeling static power consumption. The proposed template attacks are tested using transistor-level simulations of circuits designed with a 45-nm standard cell library. Our test results show that our approach improves the success rate of template attacks using static power in cases where the distribution of static power consumption cannot be accurately modeled by Gaussian models.