Co,Fe, and Ti Implants in InGaAs and Co Implants in InP at 200° C

Elevated temperature (200° C) single- and multiple-energy Co implants inn-type InP, Co and Fe implants in n-type In_0.53Ga_0.47As, and Ti implants inp-type In_0.53Ga_0.47As were performed. For elevated temperature, single-energy Co and Fe implants, no satellite peaks at various locations like 0.8R _P, R_P + ΔR_P, and 2R _P R _P is the projected range and ΔR _P the straggle of the implant) are observed, in contrast to the case of room temperature implants. However, the outdiffusion of the implant is as severe as that in room temperature implantation for high temperature anneals. Indiffusion of the implant also occurs, but it is not as severe as the outdiffusion. High temperature annealing of Ti-implanted material results in a slight indiffusion of Ti, with minimal redistribution or outdiffusion. For all elevated temperature implants, the lattice quality of the annealed material is close to that of the virgin unimplanted material. For all ion species used in this study, resistivities close to the intrinsic limit are obtained in the implanted and annealed materials.     

Effect of Rapid Thermal Annealing on Sputtered CaCu<Subscript>3</Subscript>Ti<Subscript>4</Subscript>O<Subscript>12</Subscript> Thin Films

Calcium copper titanium oxide (CaCu₃Ti₄O₁₂, abbreviated to CCTO) films were deposited on Pt/Ti/SiO₂/Si substrates at room temperature (RT) by radiofrequency magnetron sputtering. As-deposited CCTO films were treated by rapid thermal annealing (RTA) at various temperatures and in various atmospheres. X-ray diffraction patterns and scanning electron microscope (SEM) images demonstrated that the crystalline structures and surface morphologies of CCTO thin films were sensitive to the annealing temperature and ambient atmosphere. Polycrystalline CCTO films could be obtained when the annealing temperature was 700°C in air, and the grain size increased signifi- cantly with annealing in O₂. The 0.8-μm CCTO thin film that was deposited at RT for 2 h and then annealed at 700°C in O₂ exhibited a high dielectric constant (ε′) of 410, a dielectric loss (tan δ) of 0.17 (at 10 kHz), and a leakage current density (J) of 1.28 × 10⁻⁵ A/cm² (at 25 kV/cm).     

Annealing temperature dependence of TiB2 schottky barrier contacts on n-GaN

The annealing temperature (25–700°C) dependence of Schottky contact characteristics on n-GaN using a TiB₂/Ti/Au metallization scheme deposited by sputtering is reported. The Schottky barrier height increased from 0.65 to 0.68 eV as the anneal temperature was varied from 25°C to 350°C and decreased to 0.55 eV after annealing at 700°C. The barrier height showed no measurable dependence on measurement temperature up to 150°C. The elemental profile obtained from samples annealed at 350°C showed limited Ti diffusion from the elemental Ti layer into the gold layer. Annealing at 700°C produced significant out-diffusion of this layer, while the TiB₂ layer retained its stability. These contacts show promise for applications requiring good thermal stability, such as power amplifiers, but much more work is needed to establish their long-term reliability. In addition, TiB₂ has a strong propensity for oxidation, and it is imperative that overlayers such as Au be deposited in the same deposition chamber.     

OMVPE growth of InP and Ga0.47ln0.53as using ethyldimethylindium

We report the organometallic vapor phase epitaxial (OMVPE) growth of InP and Ga_0.47In_0.53As using a new organometallic indium source, ethyldimethylindium (EDMIn), rather than the traditional sources triethylindium (TEIn) or trimethylindium (TMIn). EDMIn is a liquid at room temperature and its vapor pressure at 17° C was found to be 0.85 Torr using thermal decomposition experiments. The growth results using EDMIn were compared to those using TMIn in the same atmospheric pressure reactor. For InP, use of EDMIn resulted in a high growth efficiency of 1.3 × 10⁴ μm/ mole, which was independent of the growth temperature and comparable to the growth efficiency obtained with TMIn. The high growth efficiency is consistent with the observation of no visible parasitic gas phase reactions upstream of the substrate. The 4K photoluminescence (PL) spectra consist of a peak due to bound excitons and an impurity related peak 38 meV lower in energy. This impurity peak is ascribed to conduction band to acceptor transitions from carbon, due to the decreasing relative intensity of this peak with increasing V/III ratio. The relative intensity of the C impurity peak decreases by five times when the growth temperature is increased from 575 to 675° C, with a corresponding increase in the room temperature electron mobility from 725 to 3875 cm²/ Vs. For GalnAs lattice-matched to InP, use of EDMIn also resulted in a temperatureindependent high growth efficiency of 1.0 x 10⁴ μm/mole, indicating negligible parasitic reactions with AsH₃. The In distribution coefficient was nearly constant at a value of 0.9, however the run to run composition variation was slightly higher for EDMIn than for TMIn. The 4K PL showed donor-acceptor pair transitions due to C and Zn. The C impurity peak intensity decreased dramatically with increasing growth temperature, accompanied by an increase in the room temperature electron mobility to 5200 cm²/Vs. Overall, the growth of both InP and GalnAs using EDMIn was qualitatively similar to that using TMIn, although the room temperature electron mobilities were lower for the new source than for our highest purity bottle of TMIn.     

Si- and Mg-implanted InP,GaInAs and short-time proximity cap annealing

Si- and Mg-ions with energies of 180 keV have been implanted into semi-insulating InP substrates and low doped n- and p-type GalnAs epitaxial layers (3 · l0¹⁶cm⁻³). Sheet resistances and doping profiles are analyzed and compared with LSS theory. Post-implantation annealing is studied with respect to encapsulation, time and temperature. We have tested as new encapsulation techniques for InP the simple proximity cap annealing and for GalnAs the As-doped spun-on SiO₂. Proximity cap annealing yields decomposition-free surfaces when using a recessed capsubstrate. At annealing temperatures of around 800 °C less activation is obtained than with conventional PSG annealing and a surface accumulation of charge-carriers is established. A time limit of around 3 min is found for Si- and Mg-implanted InP, beyond which the sheet resistance no longer decreases and the doping saturates. For Si in InP, short-time annealing yields to a 68 % activation of carriers, not significantly higher than with conventional long-time annealing. In the case of Si in GalnAs, however, short-time annealing is much more effective. A 100 % activation is obtained for a dose of 2.10¹⁴ cm⁻², while only 7 % is found for long annealing. Even at such a high dose of 1. 10¹⁶cm⁻² we have achieved about an order of magnitude higher activation with short annealing than with long annealing. Most information contained in this paper was presented at the 1984 Electron Materials Conference as paper L-l.     

Rapid isothermal annealing of high- and low-energy ion-implantedInP and In0.53Ga0.47As

Rapid isothermal annealing (RIA) was performed on 0.5-16-MeV Si ⁺, 1-MeV Be⁺, and 150-keV Ge⁺ implanted InP:Fe and 380-keV Fe⁺ implanted InGaAs. Annealings were performed in the temperature range 800-925°C using an InP proximity wafer in addition to the Si₃N₄ dielectric cap. Dopant activations close to 100% were obtained for 3×10¹⁴ cm^-2 Si⁺ and 2×10¹⁴ cm^-2 Be⁺ implants in InP:Fe. For the elevated temperature (200°C) 1×10¹⁴ cm^-2 Ge⁺ implant, a maximum of 50% activation was obtained. No redistribution of dopant was observed for Si and Ge implants due to annealing. However, redistribution of dopant was seen for Be and Fe implants due to annealing. Phosphorous coimplantation has helped to eliminate the Be in-diffusion problem in InP, but did not help to reduce Fe in-diffusion and redistribution in InGaAs. Using an RIA cycle with low temperature and short duration is the only solution to minimize Fe redistribution in InGaAs     

Capacitance-voltage profiling and thermal evolution of the conduction band-offset of unstrained Ga0.47In0.53As/InP single quantum well

We report the results of capacitance-voltage (C-V) and Deep Level Transient Spectroscopy (DLTS) measurements performed upon a Ga_0.47In_0.53As/InP quantum well structure. At room temperature, a conduction-band offset ΔE_c=(200±10)meV and charge densities σ_I=±(3±1)*10¹¹ times the electronic charge per cm² have been measured from C-V experiments. At lower temperature (T≤150K) we have observed an important decrease of the band-offset, considerably larger than a pure thermal effect. We have shown that the explanation lies in the presence of a high concentration of deep traps located at the well-barrier interfaces. Two species A and B have been detected through DLTS experiments with activation energies E_tA=90 meV and E_tB=195 meV, respectively. The filling of these trap levels at low temperature lowers the band offset from 200 to 120 meV, owing to band repulsion effects.     

MeV energy sulfur implantation in GaAs and InP

Room temperature and elevated temperature sulfur implants were performed into semi-insulating GaAs and InP at variable energies and fluences. The implantations were performed in the energy range 1–16 MeV. Range statistics of sulfur in InP and GaAs were calculated from the secondary ion mass spectrometry atomic concentration depth profiles and were compared with TRIM92 values. Slight in-diffusion of sulfur was observed in both InP and GaAs at higher annealing temperatures for room temperature implants. Little or no redistribution of sulfur was observed for elevated temperature implants. Elevated temperature implants showed higher activations and higher mobilities compared to room temperature implants in both GaAs and InP after annealing. Higher peak electron concentrations were observed in sulfur-implanted InP (n ≈ 1 × 10¹⁹ cm⁻³) compared to GaAs (n ≈ 2 × 10¹⁸ cm⁻³). The doping profile for a buried n⁺ layer (n ≈ 3.5 × 10¹⁸ cm⁻³) of a positive-intrinsic-negative diode in GaAs was produced by using Si/S coimplantation.     

Research of SiO2/InP structure prepared by photo-CVD

The SiO₂ film as an insulator in InP MOS structure was grown by mercury-sensitized photo induced chemical-vapor deposition (photo-CVD) utilizing gaseous mixture of monosilane (SiH₄) and nitrous oxide (N₄O) under 253.7 nm ultraviolet light irradiation. The PHOTOX SiO₂ film (i.e., SiO₂ film prepared by photo-CVD system) deposited at 250° C has a refractive index of 1.46 and breakdown field strength of 7.0 MV/cm. The 1 MHz capacitance-voltage characteristics of the InP MOS diode was measured to study the interface state densities. The minimum value is 1.2 × 10¹¹ cm⁻²eV⁻¹ for the sample prepared at a substrate temperature of 250° C.     

Ir Diffusion Barriers in Ni/Au Ohmic Contacts to <Emphasis Type="Italic">p</Emphasis>-Type CuCrO<Subscript>2</Subscript>

The use of Ir diffusion barriers in Ni/Au-based Ohmic contacts to p-type CuCrO₂ layers was investigated. A specific contact resistance of ~5 × 10⁻⁴ Ω cm² was achieved after annealing at 500°C for the Ir-containing contacts, and the contacts were rectifying for lower anneal temperatures. In this case, the contact resistance was basically independent of the measurement temperature, indicating that tunneling is the dominant transport mechanism in the contacts. The morphology for the Ir-containing contacts was still smooth at 500°C although Auger electron spectroscopy depth profiling showed that some of the nickel had diffused to the surface and had oxidized. Contacts annealed at 800°C showed that some copper and most of the nickel had diffused to the surface and oxidized. The presence of the Ir diffusion barrier does increase the thermal stability of the contacts by ∼200°C compared to conventional Ni/Au contacts. By contrast, the use of other materials such as TaN, ZrN, and W₂B₅ as the diffusion barrier led to poorer thermal stability, with the contact resistance increasing sharply above 400°C.     

A comparison of TMGa and TEGa for low-temperature metalorganic chemical vapor deposition growth of CCI4-doped inGaAs

Factors which influence the alloy composition and doping level of CCl₄-doped In_0.53Ga_04.7As grown at low temperatures (450°C < T_g < 560°C) by low-pressure metalorganic chemical vapor deposition (MOCVD) have been investigated. The composition is highly dependent on substrate temperature due to the preferential etching of In from the surface during growth and the temperature-dependent growth efficiency associated with the Ga source. The lower pyrolysis temperature of TEGa relative to TMGa allows the growth of CCl₄-doped InGaAs at lower growth temperatures than can be achieved using TMGa, and results in improved uniformity. High p-type doping (p ∼ 7 × 10¹⁹ cm^-8) has been achieved in C-doped InGaAs grown at T = 450°C. Secondary ion mass spectrometry analysis of a Cdoping spike in InGaAs before and after annealing at ∼670°C suggests that the diffusivity of C is significantly lower than for Zn in InGaAs. The hole mobilities and electron diffusion lengths in p⁺-InGaAs doped with C are also found to be comparable to those for Be and Zn-doped InGaAs, although it is also found that layers which are highly passivated by hydrogen suffer a degradation in hole mobility. InP/InGaAs heterojunction bipolar transistors (HBTs) with a C-doped base exhibit high-frequency performance (f_t = 62 GHz, f_max=42 GHz) comparable to the best reported results for MOCVD-grown InP-based HBTs. These results demonstrate that in spite of the drawbacks related to compositional nonuniformity and hydrogen passivation in CCl₄-doped InGaAs grown by MOCVD, the use of C as a stable p-type dopant and as an alternative to Be and Zn in InP/ InGaAs HBTs appears promising.     

Preparation of PbTiO3 thin films by plasma enhanced MOCVD and the effect of rapid thermal annealing

Dielectric PbTiO₃-thin films were prepared on p-Si(100) substrate by plasma enhanced metalorganic chemical vapor deposition using high purity Ti(O-i-C₃H₇)₄, Pb(tmhd)₂, and oxygen. As-deposited films were post-treated by rapid thermal annealing method, and the effect of annealing was examined under various conditions. The deposition process was controlled by mixed-control scheme at temperatures lower than 350°C, but controlled by heterogeneous surface reaction at temperatures greater than 350°C. The as-deposited films showed PbO structure at 350∼400°C, but (100) and (101) PbTiO₃ orientations started to appear at 450°C. The deposition rate was increased with rf power due to the enhanced dissociation of Ti and Pb precursors. It was found that the concentration of oxygen plays an important role in crystallization of PbTiO₃ during the rapid thermal annealing. A linear relationship was obtained between the dielectric constant of PbTiO₃ films and the annealing temperature. However, the surface roughness and leakage current density increased mainly due to the defects caused by volatilization of lead and the interface layer formed during the high temperature annealing.     

Nearly equilibrium growth of In1−x Gax Asy P1−y (0 ≤ y ≤ 1) Lattice-Matched to <100> InP

Data for nearly-equilibrium LPE growth at 626°C of InGaAs lattice-matched to the <100> face of InP are presented and the modeling of phase equilibria in this system is discussed. Because the simple solution approximation, which is useful for modeling binary (InP) and ternary (InGaAs) growth, is found to be unsatisfactory for the quaternary, a semi-empirical model suitable for determining the phase equilibria for LPE growth of any lattice-matched composition over a wide temperature range is proposed. The model is based on a simple scaling of data for lattice-matched growth at one liquidus temperature, 626°C, to other temperatures using data for the two lattice-matching compositions, InP and InGaAs, for which the temperature dependencies can be calculated. Using this ‘model’, melt compositions for growth with 600 < T_ℓ < 660°C are calculated and compared with expermental results. The nearly-equilibrium growth technique is fully described and empirical techniques for adjusting melt compositions to improve the degree of lattice-match are also given.     

Lateral diffusion effects in AuGe based source-drain contacts to AllnAs/InGaAs/InP doped channel MODFETs

We have investigated the formation of source-drain AuGe/Au and Ni/AuGe/Ni/Au alloyed ohmic contacts to AlInAs/InGaAs/InP doped channel MODFETs, and observed lateral diffusion of the contact system after the standard annealing procedure at the temperature range of 185 to 400°C. Auger depth profiling of contacts annealed at 250°C, revealed that Au(Ge) diffused through the top InGaAs and AlInAs layers into the active InGaAs layer, but had reduced penetration into the AlInAs buffer layer. This reduction in diffusion along the depth axis at the AlInAs buffer layer boundary is believed to result in enhanced lateral diffusion and the observed lateral encroachment of the contacts. Both Au and Ni containing contact systems showed similar behavior in terms of lateral diffusion with encroachment extending between 0.25 and 0.5 μm at the periphery of the contacts for annealing temperatures between 300 and 400°C. A controlled ramp-to-peak temperature annealing procedure is developed to suppress such lateral diffusion effects. Low temperature annealing (250°C) using this procedure resulted in equally low contact resistance values (∼0.1Θ-mm) and no lateral diffusion. It is concluded that in thin multilayered structures the modified annealing procedure presented here, is necessary for optimal ohmic contact formation.     

Correlation between the electrical properties and the interfacial microstructures of TiAl-based ohmic contacts to p-type 4H-SiC

In order to understand a mechanism of TiAl-based ohmic contact formation for p-type 4H-SiC, the electrical properties and microstructures of Ti/Al and Ni/Ti/Al contacts, which provided the specific contact resistances of approximately 2×10⁻⁵ Ω-cm² and 7×10⁻⁵ Ω-cm² after annealing at 1000°C and 800°C, respectively, were investigated using x-ray diffraction (XRD) and high-resolution transmission electron microscopy (HRTEM). Ternary Ti₃SiC₂ carbide layers were observed to grow on the SiC surfaces in both the Ti/Al and the Ni/Ti/Al contacts when the contacts yielded low resistance. The Ti₃SiC₂ carbide layers with hexagonal structures had an epitaxial orientation relationship with the 4H-SiC substrates. The (0001)-oriented terraces were observed periodically at the interfaces between the carbide layers and the SiC, and the terraces were atomically flat. We believed the Ti₃SiC₂ carbide layers primarily reduced the high Schottky barrier height at the contact metal/p-SiC interface down to about 0.3 eV, and, thus, low contact resistances were obtained for p-type TiAl-based ohmic contacts.     

Current-voltage characteristics and X- ray diffraction study of Pd/Si1- xGex schottky contacts

The electrical characteristics of Pd/p-Si_1-xGe_x Schottky contacts have been investigated. The Schottky contacts were formed by depositing Pd metal on substrates at room temperature (RT = 300K) and at low temperature (LT = 77K). Post annealing was performed in nitrogen atmosphere at 450 and 550°C, respectively, to study the effect of silicide formation on contact characteristics. The current-voltage measurements showed that the barrier height, ϕ_B, decreased with the increase of the gemanium composition. The contact postannealed at 550°C showed a current transport mechanism obviously different from the as-deposited Schottky contacts. Nearly identical characteristics were observed for the low temperature deposited contacts and the room temperature deposited contacts with 550°C post-annealing. They both showed thermionic emission dominated transport mechanism. X-ray diffraction technique was used to characterize the effect of different temperature treatments on the crystal structure. The full width at half maximum of Si_1-xGe_x(400) phase decreased at low temperature deposited sample, while it increased at room temperature deposition.     

Refractory metal boride ohmic contacts to P-type 6H-SiC

Ohmic contacts have been fabricated on p-type 6H-SiC (1.3×10¹⁹ cm⁻³) using CrB₂, W₂B, and TiB₂. The boride layers (∼100–200 nm) were sputter-deposited in a system with a base pressure of 3×10⁻⁷ Torr. Specific contact resistances were measured using the linear transmission line method, and the physical properties of the contacts were examined using Rutherford backscattering spectrometry. All as-deposited contacts exhibited rectifying characteristics. Ohmic behavior was observed following short anneals (2–10 min) at 1100°C and 5×10⁻⁷ Torr. Current-voltage characteristics were linear for CrB₂ and W₂B and quasi-linear for TiB₂. The lowest values of the specific contact resistance (r_c in Ω-cm²) measured at room temperature for CrB₂ and W₂B were 8.2×10⁻⁵ and 5.8×10⁻⁵, respectively. The specific contact resistance for TiB₂ was not determined accurately. Longer anneals (30 min for W₂B and 90 min for CrB₂) reduced the room temperature values of r_c to 6.1×10⁻⁵ for W₂B and 1.9×10⁻⁵ for CrB₂. Backscattering spectra revealed substantial concentrations of oxygen in all as-deposited boride films. The short anneal cycle removed the oxygen in the CrB₂ films and reduced the concentration substantially in the W₂B films; however, annealing had no affect on the oxygen concentration in the TiB₂ films. The CrB₂/SiC interface remained stable during annealing; i.e., Si and carbon were not observed in the boride layers after annealing. In contrast, W₂B and TiB₂ reacted with the SiC epilayers, and after annealing, Si and carbon were observed at the surface of each boride layer.     

High resistivity LT-In0.47Ga0.53P grown by gas source molecular beam epitaxy

Low-temperature (LT) growth of In_0.47Ga_0.53P was carried out in the temperature range from 200 to 260°C by gas source molecular beam epitaxy using solid Ga and In and precracked PH₃. The Hall measurements of the as-grown film showed a resistivity of ∼10⁶ Ω-cm at room temperature whereas the annealed film (at 600°C for 1 h) had at least three orders of magnitude higher resistivity. The Hall measurements, also, indicated activation energies of ∼0.5 and 0.8 eV for the asgrown and annealed samples, respectively. Double-crystal x-ray diffraction showed that the LT-InGaP films had ∼47% In composition. The angular separation, Δθ, between the GaAs substrate and the as-grown LT-InGaP film on (004) reflection was increased by 20 arc-s after annealing. In order to better understand the annealing effect, a LT-InGaP film was grown on an InGaP film grown at 480°C. While annealing did not have any effect on the HT-InGaP peak position, the LT-InGaP peak was shifted toward the HT-InGaP peak, indicating a decrease in the LT-InGaP lattice parameter. Cross-sectional transmission electron microscopy indicates the presence of phase separation in LT-InGaP films, manifested in the form of a “precipitate-like” microstructure. The analytical scanning transmission electron microscopy analysis of the LT-InGaP film revealed a group-V nonstoichiometric deviation of ∼0.5 at.% P. To our knowledge, this is the first report about the growth and characterization of LT-InGaP films.     

Effect of NO annealing conditions on electrical characteristics of n-type 4H-SiC MOS capacitors

This paper presents the results of the effect of NO annealing temperature and annealing time on the interfacial properties of n-type 4H-SiC MOS capacitors. The interface trap density measured by conductance technique at 330°C decreases as NO annealing temperature increases from 930°C to 1130° and annealing time is extended from 30 min. to 180 min. The changes in effective oxide charge between room temperature and high temperature are calculated and used to compare different n-type 4H-SiC MOS capacitors. Higher NO annealing temperature and longer NO annealing time decrease the change in effective oxide charge, which is consistent with the NO annealing temperature/time dependence of interface trap density measured by conductance technique. However, NO annealing temperature has more pronounced influence on the SiO₂/SiC interface than NO annealing time.     

N type doping of inp by ion implantation

Results are reported on the electrical properties of semi-insulating InP implanted with⁷⁸Se and³²S at different energies and doses. The implants were into both room temperature and heated substrates and annealed over the temperature range from 400°C to 760°C. Pronounced differ-ences have been found in the annealing temperature depend-ence between hot and room temperature implants. In most cases hot implants can be activated at much lower temp-eratures than previous reported results would indicate, making ion implantation, in principle, compatible with a wider range of device processing techniques. The role of dielectric coatings as both implantation barriers and annealing encapsulants has also been investigated.