Efficient Monte Carlo device modeling

A single-particle approach to full-band Monte Carlo device simulation is presented which allows an efficient computation of drain, substrate and gate currents in deep submicron MOSFETs. In this approach, phase-space elements are visited according to the distribution of real electrons. This scheme is well adapted to a test-function evaluation of the drain current, which emphasizes regions with large drift velocities (i.e., in the inversion channel), a substrate current evaluation via the impact ionization generation rate (i.e., in the LDD region with relatively high electron temperature and density) and a computation of the gate current in the dominant direct-tunneling regime caused by relatively cold electrons (i.e., directly under the gate at the source well of the inversion channel). Other important features are an efficient treatment of impurity scattering, a phase-space steplike propagation of the electron allowing to minimize self-scattering, just-before-scattering gathering of statistics, and the use of a frozen electric field obtained from a drift-diffusion simulation. As an example an 0.1-μm n-MOSFET is simulated where typically 30 minutes of CPU time are necessary per bias point for practically sufficient accuracy     

Effects of silicon layer properties on device reliability for0.1-μm SOI n-MOSFET design strategies

We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1-μm SOI n-MOSFET design strategies. The simulation approach features a Monte Carlo device simulator in conjunction with commercially available process and device simulators. The two channel designs are: 1) a lightly-doped (10¹⁶ cm^-3) channel and 2) a heavily-doped (10¹⁸ cm^-3) channel. For each design, the silicon layer thicknesses (T_Si) of 30, 60, and 90 nm are considered. The devices are biased under low-voltage conditions where the drain voltage is considerably less than the Si/SiO₂ barrier height for electron injection. A comparative analysis of the Monte Carlo simulation results shows that an increase in T_Si results in decreasing hot electron injection into the back oxide in both device designs. However, electron injection into the front oxide exhibits opposite trends of increasing injection for the heavily-doped channel design and decreasing injection for the lightly-doped channel design. These important trends are attributed to highly two-dimensional electric field and current density distributions. Simulations also show that the lightly-doped channel design is about three times more reliable for thick silicon layers. However, as the silicon layer is thinned to 30 nm, the heavily-doped channel design becomes about 10% more reliable instead     

Spatial retardation of carrier heating in scaled 0.1-μmn-MOSFET's using Monte Carlo simulations

A comprehensive Monte Carlo simulator is employed to investigate nonlocal carrier transport in 0.1 μm n-MOSFET's under low-voltage stress. Specifically, the role of electron-electron (e-e) interactions on hot electron injection is explored for two emerging device designs biased at a drain voltage V_d considerably less than the Si/SiO₂ injection barrier height φ_b. Simulation of both devices reveal that 1) although qV_d<φ_b, carriers can obtain energies greater than φ_b, and 2) the peak for electron injection is displaced approximately 20 nm beyond the peak in the parallel channel electric field. These phenomena constitute a spatial retardation of carrier heating that is strongly influenced by e-e interactions near the drain edge. (Virtually no injection is observed in our simulations when e-e scattering is not considered.) Simulations also show that an aggressive design based on larger dopant atoms, steeper doping gradients, and a self-aligned junction counter-doping process produces a higher peak in the channel electric field, a hotter carrier energy distribution, and a greater total electron injection rate into the oxide when compared to a more conventionally-doped design. The impact of spatially retarded carrier heating on hot-electron-induced device degradation is further examined by coupling an interface state distribution obtained from Monte Carlo simulations with a drift-diffusion simulator. Because of retarded carrier heating, the interface states are mainly generated further over the drain region where interface charge produces minimal degradation. Thus, surprisingly, both 0.1 μm n-MOSFET designs exhibit comparable drain current degradation rates     

Design of 10-nm-scale recessed asymmetric Schottky barrier MOSFETs

We have proposed and simulated a new 10-nm and sub-10 nm n-MOSFET that has a recessed channel and asymmetric source/drain Schottky Contacts (RASC MOSFETs). The recessed channel can effectively suppress short-channel effects, and the asymmetric source/drain contacts in which a higher Schottky barrier at the source contact can yield smaller off-state current while a lower Schottky barrier at the drain can yield larger on-state current. The simulated results show that the device can exhibit an on/off ratio as high as 10⁶ and an on-state current of 393 μA/μm with a supply voltage of 1.0 V. Furthermore, the parameters of RASC MOSFETs are rather insensitive to size variations. These characteristics make the 10-nm or even sub-10 nm transistors potentially suitable for logic and memory applications     

Monte Carlo simulation and measurement of nanoscale n-MOSFETs

The output characteristics of state-of-the-art n-MOSFETs with effective channel lengths of 40 and 60 nm have been measured and compared with full-band Monte Carlo simulations. The device structures are obtained by process simulation based on comprehensive secondary ion mass spectroscopy and capacitance-voltage measurements. Good agreement between the measured output characteristics and the full-band Monte Carlo simulations is found without any fitting of parameters and the on-currents are reproduced within 4%. The analysis of the velocity profiles along the channel confirms that the on-current is determined by the drift velocity in the source side of the channel. Analytic-band Monte Carlo simulations are found to involve an overestimation of the drain current in the nonlinear regime which becomes larger for increasing drain voltage and decreasing gate length. The discrepancy originates from a higher nonlinear drift velocity and a higher overshoot peak in bulk silicon which is due to differences in the band structures above 100 meV. The comparison between analytic-band and full-band Monte Carlo simulation therefore shows that the source-side velocity in the on-state is influenced by nonlinear and quasiballistic transport.     

Full-band Monte Carlo investigation of hot carrier trends in thescaling of metal-oxide-semiconductor field-effect transistors

A full-band Monte Carlo (MC) device simulator has been used to study the effects of device scaling on hot electrons in different types of n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) structures. Simulated devices include a conventional MOSFET with a single source/drain implant, a lightly-doped drain (LDD) MOSFET, a silicon-on-insulator (SOI) MOSFET, and a MOSFET built on an epitaxial layer on top of a heavily-doped ground plane. Different scaling techniques have been applied to the devices, to analyze the effects on the electric field and on the energy distributions of the electrons, as well as on drain, substrate, and gate currents. The results provide a physical basis for understanding the overall behavior of impact ionization and gate oxide injection and how they relate to scaling. The observed nonlocality of transport phenomena and the nontrivial relationship between electric fields and transport parameters indicate that simpler models cannot adequately predict hot carrier behavior at the channel lengths studied (sub-0.3-μm). In addition, our results suggest that below 0.15 μm, the established device configurations (e.g. LDD) that are successful at suppressing the hot carrier population for longer channel lengths, become less useful and their cost-effectiveness for future circuit applications needs to be reevaluated     

Ensemble Monte Carlo study of channel quantization in a 25-nmn-MOSFET

We develop a self-consistent, ensemble Monte Carlo device simulator that is capable of modeling channel carrier quantization and polysilicon gate depletion in nanometer-scale n-MOSFETs. A key feature is a unique bandstructure expression for quantized electrons. Carrier quantization and polysilicon depletion are examined against experimental capacitance-voltage (C-V) data. Calculated drain current values are also compared with measured current-voltage data for an n-MOSFET with an effective channel length (L_eff) of 90 nm. Finally, the full capabilities of the Monte Carlo simulator are used to investigate the effects of carrier confinement in a L_eff=25 nm n-MOSFET. In particular, the mechanisms affecting the subband populations of quantized electrons in the highly nonuniform channel region are investigated. Simulation results indicate that the occupation levels in the subbands are a strong function of the internal electric field configurations and two-dimensional (2-D) carrier scattering     

Interface traps at high doping drain extension region insub-0.25-μm MOSTs

A huge bulk (or drain) current I_b (or I_d) peak versus gate voltage was observed for the 0.25-μm or sub-0.25-μm metal-oxide-semiconductor field effect transistors (MOSTs) with high doping concentration source/drain extension, when the drain-bulk p-n junction is forward biased. This current is increased under Fowler-Nordheim (FN) or channel hot carrier (CHC) stress and is identified as thermal-trap-tunneling electron current at the drain extension-gate overlap region. It is extremely sensitive that one interface trap will induce 0.1 pA current increment of peak I_b (or I_d)     

Numerical analysis of nonequilibrium electron transport inAlGaAs/InGaAs/GaAs pseudomorphic MODFETs

Nonequilibrium electron transport in InGaAs pseudomorphic MODFETs has been analyzed with the moment equations approach. In the model, the momentum and energy balance equations for the two-dimensional electrons in the InGaAs channel are solved with relaxation times generated from a Monte Carlo simulation. The two-dimensional electron wave functions and the quantized state energies in the InGaAs quantum well are calculated exactly from the Schrodinger equation along the direction perpendicular to the quantum well. Also included is a two-dimensional Poisson equation solver. In the calculation, all of the equations are solved iteratively until a self-consistent solution is achieved. The simulation results for a realistic device structure with a 0.5-μm recessed gate show a significant overshoot velocity of 4.5×10⁷ cm/s at a drain bias of 1.0 V. Electron temperature reaches a peak value of around 2500 K under the gate. In energy transport, the diffusive component of the energy flux is found to be dominant in the high-field region     

Ensemble Monte Carlo study of interface-state generation inlow-voltage scaled silicon MOS devices

An ensemble Monte Carlo (MC) model coupled with an interface-state generation model was employed to predict the quantity and lateral distribution of hot-electron-induced interface states in scaled silicon MOSFETs. Constant field and more generalized scaling methods were used as the basis to simulate devices with 0.33-, 0.20-, and 0.12-μm channel lengths. The dependencies of interface-state generation on applied bias and electric field profiles were investigated. Hot-electron injection and interface-state density profiles were simulated at biases as low as 1.44 V (i.e., lower than the 3.1 V potential barrier at the Si/SiO₂ interface). These simulations demonstrate that “lucky electron” and/or electron temperature models are no longer accurate for predicting hot-electron effects in such regimes. Electron-electron scattering is shown to be a critical consideration for simulation of hot-electron injection at low drain to source bias voltages, where local interfacial barrier heights are greater than the energy gained by an electron from the applied electric field. Simulations indicate that a scaled decrease in the channel length of a device may be accompanied by an increase in the lateral electric field without incurring a penalty for higher hot-electron degradation. It is also shown that conventional hot-electron stressing using accelerated stress bias conditions may continue to be valuable for predicting the reliability of device designs scaled to 0.1-μm channel lengths     

Simulation of Schottky barrier MOSFETs with a coupled quantuminjection/Monte Carlo technique

A full-band Monte Carlo device simulator has been used to analyze the performance of sub-0.1 μm Schottky barrier MOSFETs. In these devices, the source and drain contacts are realized with metal silicide, and the injection of carriers is controlled by gate voltage modulation of tunneling through the source barrier. A simple model treating the silicide regions as metals, coupled with an Airy function approach for tunneling through the barrier, provides injecting boundary conditions for the Monte Carlo procedure. Simulations were carried out considering a p-channel device with 270 Å gate length for which measurements are available. Our results show that in these structures there is not a strong interaction with the oxide interface as in conventional MOS devices and carriers are injected at fairly wide angles from the source into the bulk of the device. The Monte Carlo simulations not only give good agreement with current-voltage (I-V) curves, but also easily reproduce the subthreshold behavior since all the computational power is devoted to simulation of channel particles. The simulations also clarify why these structures exhibit a large amount of leakage in subthreshold regime, due to both thermionic and tunneling emission. Computational experiments suggest ways to modify the doping profile to reduce to some extent the leakage     

Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD withpreheating

Undoped epitaxial channel n-MOSFET with high transconductance was developed. In order to obtain a good crystal quality of the epitaxial layer and, thus, to achieve high performance, it is important to reduce the oxygen concentration at the epitaxial Si/Si substrate interface. In this paper, we describe the relationship between the electrical characteristics and the surface density of oxygen at the epitaxial Si/Si substrate. We also describe the dependence of the electrical characteristics on epitaxial Si thickness. The g_m of n-MOSFET with 40-nm epitaxial Si for 0.10-μm gate length was 630 mS/mm at V _d-1.5 V, and the drain current was 0.77 mA/μm. This g_m value in the case of the epitaxial Si channel is about 20% larger than that of bulk the MOSFET. These results show that epitaxial Si channel MOSFET's are useful for future high-speed ULSI devices     

P-MOSFET's with ultra-shallow solid-phase-diffused drain structureproduced by diffusion from BSG gate-sidewall

A p-MOSFET structure with solid-phase diffused drain (SPDD) is proposed for future 0.1-μm and sub-0.1-μm devices. Highly doped ultrashallow p⁺ source and drain junctions have been obtained by solid-phase diffusion from a highly doped borosilicate glass (BSG) sidewall. The resulting shallow, high-concentration drain profile significantly improves short channel effects without increasing parasitic resistance. At the same time, an in situ highly-boron-doped LPCVD polysilicon gate is introduced to prevent the transconductance degradation which arises in ultrasmall p-MOSFETs with lower process temperature as a result of depletion formation in the p⁺-polysilicon gate. Excellent electrical characteristics and good hot-carrier reliability are achieved     

Gate length scaling for Al0.2Ga0.8N/GaNHJFETs: two-dimensional full band Monte Carlo simulation includingpolarization effect

Two-dimensional self-consistent full band Monte Carlo (FBMC) simulator was developed for electron transport in wurtzite phase AlGaN/GaN heterojunction (HJ) FET. Recessed gate Al_0.2Ga_0.8N/GaN HJFET structures with an undoped cap layer were simulated, where the spontaneous and piezoelectric polarization effects were taken into account. The polarization effect was shown to not only increase the current density, but also improve the carrier confinement, and hence improve the transconductance. An off-state drain breakdown voltage (BV_ds) of 300 V and a maximum linear output power (P_max) of 46 W/mm were predicted for a 0.9-μm gate device. For a 0.1-μm gate device, 60 V BV_ds , 20 W/mm P_max, and 160 GHz current-gain cutoff frequency were predicted. Although there is considerable uncertainty due to lack of information on the band structure, scattering rates, and surface conditions, the present results indicate a wide margin for improvements over current performance of AlGaN/GaN HJFETs in the future. To our knowledge, this is the first report on the FBMC simulation for AlGaN/GaN HJFETs     

A Quantum-Corrected Monte Carlo Study on Quasi-Ballistic Transport in Nanoscale MOSFETs

In this paper, the authors study a quasi-ballistic transport in nanoscale Si-MOSFETs based upon a quantum-corrected Monte Carlo device simulation to explore an ultimate device performance. It was found that, when a channel length becomes shorter than 30 nm, an average electron velocity at the source-end of the channel increases due to ballistic transport effects, and then, it approaches a ballistic limit in a sub-10-nm regime. Furthermore, the authors elucidated a physical mechanism creating an asymmetric momentum distribution function at the source-end of the channel and the influences of backscattering from the channel region. The authors also demonstrated that an electron injection velocity at a perfectly ballistic transport is independent of the channel length and corresponds well to a prediction from Natori's analytical model     

Simulation of a long term memory device with a full bandstructureMonte Carlo approach

Simulations of charging characteristics of a long term memory device, based on a floating gate structure, are presented. The analysis requires the inclusion of hot electron effects and a detailed account of the semiconductor bandstructure, because device operation is based on the injection of electrons into the gate oxide high above the silicon conduction band edge. We have developed a Monte Carlo simulator based on a full bandstructure approach which accurately accounts for the high energy tail of the electron distribution function. For practical simulation of the prototype structure; with 3.0-μm source-drain separation, the simulator is used as a post-processor on the potential profile obtained from a PISCES IIB drift-diffusion solution. The computations are in quantitative agreement with experimental results for the gate injection current, measured at fixed drain and gate biases     

A new asymmetrical halo source GOLD drain (HS-GOLD) deepsub-half-micrometer n-MOSFET design for reliability and performance

An asymmetrical n-MOSFET device structure was developed that is suitable, in terms of reliability and performance, for scaling down to the sub-quarter-micrometer level without reduction of the supply voltage below 3.5 V. In this structure, large-tilt implantation is used to form the gate-overlapped LDD (GOLD) region at the drain electrode only. A halo (punchthrough stopper) is used at the source, but not at the drain. Superior hot carrier reliability and high punchthrough resistance are obtained using this device structure. A reliability-limited supply voltage of 4.2 V is obtained for an asymmetrical n-MOSFET with effective channel lengths as short as 0.25 μm. By extrapolation from the measured threshold roll-off characteristics, the authors expect that this structure can be designed with substantially shorter channel length while maintaining the 3.5-V supply voltage     

Monte Carlo surface scattering simulation in MOSFET structures

The Monte Carlo method has been applied to MOSFET devices with the gate lengths less than 1 µm. The electric field in the channel was obtained by an analytical approach. Since the classical situation is approached in the submicrometer gate device, the partial diffusive model is employed for surface scattering process. Transient phenomena such as velocity overshoot have been predicted with drain biases causing a large field gradient in the channel. Comparison of the results of the Monte Carlo simulation with those obtained by an analytical approach based on static mobility shows that the carrier transit time in the channel is shorter (as much as two times) than that predicted by the analytical approach for a 0.3 µm gate device.     

Ensemble Monte Carlo simulation of a 0.35-μm pseudomorphic HEMT

Theoretical analysis and precise comparison to experiment of the performance of a 0.35-μm pseudomorphic Al_0.15Ga_0.85 As/In_0.15Ga_0.85As high-electron-mobility transistor (HEMT) are presented. The calculations are made using an ensemble Monte Carlo simulation with the unique inclusion of real space transfer as well as the full details of the two-dimensional electron gas, velocity overshoot, and ballistic transport, and the effects of the two-dimensional electric field profile. The calculated current-voltage characteristic is compared to recent experimental measurements showing excellent agreement to within ~10% over a full range of gate and drain biases. It is found that near the source, the two-dimensional system dominates the transport physics, while near the pinch-off point, the effects of real space transfer become apparent. It is further determined that the high-speed performance of the pseudomorphic HEMT stems predominantly from the high electron confinement within the two-dimensional system, and the high electron mobility and confinement within the gamma valley in the bulk InGaAs     

High-gain lateral bipolar action in a MOSFET structure

A hybrid-mode device based on a standard submicrometer CMOS technology is presented. The device is essentially a MOSFET in which the gate and the well are internally connected to form the base of a lateral bipolar junction transistor (BJT). At low collector current levels, lateral bipolar action with a current gain higher than 1000 is achieved. No additional processing steps are needed to obtain the BJT when the MOSFET is properly designed. n-p-n BJTs with a 0.25-μm base width have been successfully fabricated in a p-well 0.25-μm bulk n-MOSFET process. The electrical characteristics of the n-MOSFET and the lateral n-p-n BJT at room and liquid nitrogen temperatures are reported