一种高速CMOS SRAM读出灵敏放大器的设计

提出了一种ＣＭＯＳ ＳＲＡＭ读出灵敏放大器的新结构。该放大器同传统的ＰＭＯＳ电流镜放大器和ＰＭＯＳ交叉耦合放大器相比，具有速度快、增益大、功耗小等特点，可广泛应用于ＳＲＡＭ的设计中。最后，用ＨＳＰＩＣＥ的仿真结果证明了该设计的正确性及其优点。     

A current-controlled latch sense amplifier and a staticpower-saving input buffer for low-power architecture

Two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described. One is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically. This sense amplifier reduces power without degrading access time compared with the conventional current-mirror sense amplifier. The other is a static power-saving input buffer (SPSIB) that reduces DC current in interface circuits receiving TTL high input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM     

一种应用于DSP嵌入式存储器的灵敏放大器设计

提出了一种新型灵敏放大器,电路由单位增益电流传输器、电荷转移放大器及锁存器三部分组成。基于0.18μm标准CMOS单元库的仿真结果表明,与现有几种灵敏放大器相比,新型灵敏放大器具有更低的延时和功耗,在1.8 V工作电压、500 MHz工作频率、80μA输入差动电流以及DSP嵌入式SRAM6T存储单元测试结构下,每个读周期的延迟为728 ps,功耗为10.5fJ。与电压灵敏放大器相比,延迟减少约41%,功耗降低约50%;与常规电荷转移灵敏放大器相比,延迟减少约22%,功耗降低约37%;与WTA电流灵敏放大器相比,延迟减少11%,功耗降低31.8%。     

A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture

Circuit techniques for a reduced-voltage-amplitude data bus, fast access 16-Mb CMOS SRAM are described. An interdigitated bit-line architecture reduces data bus line length, thus minimizing bus capacitance. A hierarchical sense amplifier consists of 32 local sense amplifiers and a current sense amplifier. The current sense amplifier is used to reduce the data bus voltage amplitude and the sensing of the 16-b data bus signals in parallel. Access time of 15 ns and an active power of 165 mW were achieved in a 16-Mb CMOS SRAM. A split-word-line layout memory cell with double-gate pMOS thin-film transistors (TFTs) keeps the transistor width stable while providing high-stability memory cell characteristics. The double-gate pMOS TFT also increases cell-storage node capacitance and soft-error immunity     

Offset compensating bit-line sensing scheme for high density DRAM's

This paper describes a new bit-line sensing scheme that minimizes the sensitivity degradation caused by the electrical imbalance in a sense amplifier composed of scaled-down transistors. The new sensing scheme incorporates an offset compensating technique in a direct bit-line sensing scheme using a current-mirror differential amplifier. The compensation is performed by means of a simple negative feedback method that accomplishes cancellation of the total electrical imbalance in the sense amplifier with a short presetting time. The features of the circuit have been examined using simple DRAM test chips fabricated with a 0.5 μm CMOS process. Experimental results indicate that the magnitude of the imbalance of the sense amplifier is reduced to one-sixth by introducing the offset compensating scheme as compared to the conventional sensing scheme     

高速低功耗电流型灵敏放大器的设计

提出了一款适合在低电压、大容量SRAM中应用的高速低功耗电流型灵敏放大器。该电路在交叉耦合反相器之间添加了一对隔离管,有效消除了大量位线寄生电容所带来的负面影响,从而极大提高了灵敏放大器的速度。同时,通过对时序控制电路的优化,有效降低了放大器的功耗。采用SMIC0．13μm数字工艺在HSpice下进行仿真,结果表明：在室温,1．2V工作电压下,灵敏放大器的放大延迟仅为0．344ns,功耗为102μw。相比文献中提出的电流型灵敏放大器,速度分别提高了9．47％和31．2％,功耗则降低了64．8％与63％。     

A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM

An ultrahigh-speed 4.5-Mb CMOS SRAM with 1.8-ns clock-access time, 1.8-ns cycle time, and 9.84-μm² memory cells has been developed using 0.25-μm CMOS technology. Three key circuit techniques for achieving this high speed are a decoder using source-coupled-logic (SCL) circuits combined with reset circuits, a sense amplifier with nMOS source followers, and a sense-amplifier activation-pulse generator that uses a duplicate memory-cell array. The proposed decoder can reduce the delay time between the address input and the word-line signal of the 4.5-Mb SRAM to 68% of that of an SRAM with conventional circuits. The sense amplifier with nMOS source followers can reduce not only the delay time of the sense amplifier but also the power dissipation. In the SRAM, the sense-amplifier activation pulse must be input into the sense amplifier after the signal from the memory cell is input into the sense amplifier. A large timing margin required between these signals results in a large access time in the conventional SRAM. The sense-amplifier activation pulse generator that uses a duplicate memory-cell array can reduce the required timing margin to less than half of the conventional margin. These three techniques are especially useful for realizing ultrahigh-speed SRAM's, which will be used as on-chip or off-chip cache memories in processor systems     

Defect Analysis and Defect Tolerant Design of Multi-port SRAMs

Multi-port SRAMs are often implemented using static random access memory (SRAM) due to its fast operation and the ability to support multiple read and write operations simultaneously, thus increasing data throughput in embedded systems and meeting the expected demands of parallel or pipelined microprocessors. With the continuous scaling of transistor feature size, designing low power robust memories and investigating their failure characteristics become critical. In this paper, we study the defects occurring in the multi-port SRAM cells. The memory is modeled at the transistor level and analyzed for electrical defects by applying a set of test patterns. Not only have existing models been taken into account in our simulation but also a new fault model, namely, simultaneous deceptive destructive read fault for the multi-port memory is introduced. In addition, we extend our study to the defect tolerant design of memories by proposing a differential current-mode sense amplifier for 3-port SRAM based register file. We examine the fault models of resistive defects within the SRAM cell and its failure boundary. A read disturb fault for multi-port memories is tested on the faulty cell by simultaneous read operations with different numbers of ports. Experimental results show that the proposed current-mode sensing scheme has improvements for memory fault-tolerance of resistive defects at 4.6× for dual-port read and 5.8× for 3-port read compared to voltage-mode sensing with 0.18 μm manufacturing process technology.     

Impact and mitigation of SRAM read path aging

This paper proposes an appropriate method to estimate and mitigate the impact of aging on the read path of a high performance SRAM design; it analyzes the impact of the memory cell, and sense amplifier (SA), and their interaction. The method considers different workloads, technology nodes, and inspects both the bit-line swing (BLS) (which reflect the degradation of the cell) and the sensing delay (SD) (which reflects the degradation of the sense amplifier); the voltage swing on the bit lines has a direct impact on the proper functionality of the sense amplifier. The results with respect to the quantification of the aging, show for the considered SRAM read-path design that the cell degradation is marginal as compared to the sense amplifier, while the SD degradation strongly depends on the workload, supply voltage, temperature, and technology nodes (up to 41% degradation). The mitigation schemes, one targeting the cell and one the sense amplifier, confirm the same and show that sense amplifier mitigation (up to 15.2% improvement) is more effective for the SRAM read path than cell mitigation (up to 11.4% improvement).     

A 16-Mb CMOS SRAM with a 2.3-μm2 single-bit-linememory cell

A novel architecture that enables fast write/read in poly-PMOS load or high-resistance polyload single-bit-line cells is developed. The architecture for write uses alternate twin word activation (ATWA) with bit-line pulsing. A dummy cell is used to obtain a reference voltage for reading. An excellent balance between a normal cell signal line and a dummy cell signal line is attained using balanced common data-line architecture. A newly developed self-bias-control (SBC) sense amplifier provides excellent stability and fast sensing performance for input voltages close to V_CC at a low power supply of 2.5 V. The single-bit-line architecture is incorporated in a 16-Mb SRAM, which was fabricated using 0.25-μm CMOS technology. The proposed single-bit-line architecture reduces the cell area to 2.3-μm² , which is two-thirds of a conventional two-bit-line cell with the same processes. The 16-Mb SRAM, a test chip for a 64-Mb SRAM, shows a 15-ns address access time and a 20-ns cycle time     

Automated bias control (ABC) circuit for high-performance VLSIs

A biasing scheme for sensing circuits, namely an automated bias control (ABC) circuit, for high-performance VLSIs is described. The ABC circuit can automatically gear the output level of sensing circuits to the input threshold voltage of the succeeding CMOS converters. The sensing performance can be accelerated with the ABC circuit either by reducing the excessive signal level margin between the sensing circuits and the CMOS converters or by reducing extra stages of signal amplification. Since feedback control of the ABC circuit ensures correct DC biasing even under large process deviations and circuit condition changes, a wider operation margin can also be obtained. Three successful applications of the ABC circuit are reported: a sense amplifier, an address transition detector (ATD), and an ECL-CMOS input buffer. A 64-kb BiCMOS SRAM employing the proposed sense amplifier and the ATD has been fabricated with a 0.8-μm 9-GHz BiCMOS technology. The SRAM has an address access time of 4.5 ns     

0.9 V current-mode sense amplifier using concurrent bit- and data-line tracking and sensing techniques

A novel high-speed sense amplifier for ultra-low-voltage SRAM applications is presented. It overcomes the long-unattended weaknesses of existing designs simply by forcing the data-lines to track the changes on the bit-lines. It has improved the sensing speed and the power consumption of the best prior art by 202 and 216%, respectively. Furthermore, the new design can operate down to a supply voltage of 0.9 V.     

一种低功耗抗辐照加固256kb SRAM的设计

设计了一个低功耗抗辐照加固的256kbSRAM。为实现抗辐照加固，采用了双向互锁存储单元（DICE）构以及抗辐照加固版图技术。提出了一种新型的灵敏放大器，采用了一种改进的采用虚拟单元的自定时逻辑来实现低功耗。与采用常规控制电路的SRAM相比，读功耗为原来的11％，读取时间加快19％。     

A 25 ns 64K static RAM

A high-performance 64K/spl times/1-bit CMOS SRAM is described. The RAM has an access time of 25 ns with active power of 350 mW and standby power of 15 mW. The access time has been obtained by using a 1.5 /spl mu/m rule CMOS process, advanced double-level A1 interconnection technology, an equalizer circuit, and a digit line sense amplifier that is the first sense amplifier directly connected to digit lines. The WRITE recovery circuit is effective in improving WRITE characteristics, and a block selecting circuit was used for low power dissipation.     

A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier

A 7-ns 140-mW 1-Mb CMOS SRAM was developed to provide fast access and low power dissipation by using high-speed circuits for a 3-V power supply: a current-sense amplifier and pre-output buffer. The current-sense amplifier shows three times the gain of a conventional voltage-sense amplifier and saves 60% of power dissipation while maintaining a very short sensing delay. The pre-output buffer reduces output delays by 0.5 ns to 0.75 ns. The 6.6-μm² high-density memory cell uses a parallel transistor layout and phase-shifting photolithography. The critical charge that brings about soft error in a memory cell can be drastically increased by adjusting the resistances of poly-PMOS gate electrodes. This can be done without increasing process complexity or memory cell area. The 1-Mb SRAM was fabricated using 0.3-μm CMOS quadrupole-poly and double-metal technology. The chip measures 3.96 mm×7.4 mm (29 mm²)     

A 9-ns 1-Mbit CMOS SRAM

A 1-Mbit CMOS static RAM (SRAM) with a typical address access time of 9 ns has been developed. A high-speed sense amplifier circuit, consisting of a three-stage PMOS cross-coupled sense amplifier with a CMOS preamplifier, is the key to the fast access time. A parallel-word-access redundancy architecture, which causes no access time penalty, was also incorporated. A polysilicon PMOS load memory cell, which had a large on-current-to-off-current ratio, gave a much lower soft-error rate than a conventional high-resistance polysilicon load cell. The 1-Mbit SRAM, fabricated using a half-micrometer, triple-poly, and double-metal CMOS technology, operated at a single supply voltage of 5 V. An on-chip power supply converter was incorporated in the SRAM to supply a partial internal supply voltage of 4 V to the high-performance half-micrometer MOS transistors.<>     

SRAM灵敏放大器的设计改进及其Hspice仿真分析

静态随机存取存储器（SRAM）由于其自身的低功耗和高速的优势而成为半导体存储器中不可或缺的重要产品。提高和改善静态存储器的性能依然是集成电路设计领域的重要课题。从降低静态存储器功耗的角度出发，重点研究了静态存储器的关键模块——灵敏放大器的工作机理和结构，设计了一种改进型的锁存型灵敏放大器，Hspice的仿真表明，该放大器的功耗大大低于传统的静态存储器的灵敏放大器模块的功耗。     

高速低功耗SRAM中灵敏放大器的设计

本文对比分析了运放型、交叉耦合型和锁存器型灵敏放大器三种不同的SRAM灵敏放大器的基本结构并通过仿真比较了它们的优缺点,在此基础上设计了读出放大时间在最坏情况下需0.5 ns,静态维持功耗约为0.1 mW的SRAM灵敏放大器.     

X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs

In an SRAM circuit, the leakage currents on the bit lines are getting increasingly prominent with the dwindling of transistors' threshold voltages as the technology scales down to 90 nm and beyond. Excessive bit-line leakage current results in slower read operations or even functional failure. In this paper, we present a new technique, called X-calibration, to combat this phenomenon. Unlike the previous method that attempts to compensate the leakage current directly, this scheme first transforms the bit-line leakage current into an equilibrium offset voltage across the bit-line pair, and then simple circuitry is utilized to cancel this offset accurately at the input of the sense amplifier so that the sensing is not affected by the bit-line leakage. SPICE simulation of a 1 Kbit SRAM macro shows that this X-calibration scheme can handle 83% higher bit-line leakage current than the previous bit-line leakage compensation scheme. Measurement results of the test chip show that the SRAM macro adopting X-calibration scheme can cope with up to 320 $mu{hbox{A}}$ bit-line leakage current.      

An experimental 295 MHz CMOS 4K×256 SRAM using bidirectionalread/write shared sense amps and self-timed pulsed word-linedrivers

An experimental 4 K word by 256 b CMOS synchronous SRAM employing read/write shared sense amplifiers and self-timed pulsed word-lines is described. The read/write shared sense amplifier allows the RAM to have 256 I/Os and the self-timed pulsed word-line scheme reduces power consumption. Fully differential I/O buses, laid out in fourth metal over the memory cell arrays, use a 0.3 V differential swing. The SRAM is fabricated in a 0.35 μm four-layer metal CMOS process employing a 6-T SRAM cell measuring 5.2 μm×6.6 μm. The die measures 13.22 mm×4.80 mm. The SRAM operates at 295 MHz with a 3.3 V supply, achieving a bandwidth of 9.44 Gbyte/s