基于改进的NSGA遗传算法的SOC软硬件划分方法

在遗传算法中引入精英保持策略构造非支配集和生成新群体,并用排除法构造非支配集,本文得到了一种改进的非支配集分类遗传算法,该算法具有全局收敛特性,并简化了计算复杂性.本文将此算法应用于SOC设计的软硬件划分.针对SOC系统设计中存在多个IP核的特点,采用整数向量的个体编码方案,避免了个体编码解码的冗余.本文给出了仿真实验结果,验证了该划分方法的有效性.     

基于扩展背包问题的的软硬件划分算法

软硬件划分问题常以时间为约束对硬件面积进行优化。随着嵌入式的发展，功耗这一因素也越来越重要，故在约束条件中加入了功耗的约束。贪婪算法是解决0-1背包问题的一种简单有效的方法，因此建立多约束的软硬件划分问题与0-1背包问题之间的联系，采用扩展的贪婪算法解决多性能指标的软硬件划分问题。利用仿真与动态规划方法的对比，进行了有效性验证。     

一种基于SystemC的软硬件协同设计方法

随着集成电路工艺的飞速发展,传统的设计方法已不能满足设计高集成度的复杂数字系统的要求。软硬件协同设计成为嵌入式系统设计的新方法。SystemC是一种兼容C++的系统建模语言,它同时支持RTL级、行为级和系统级描述,使其成为软硬件协同设计平台的基础。     

Rapid Prototyping of Embedded Hardware/Software Systems

Prototyping of embedded hardware/software systems is important, because it shortens the path from specification to the final product. Prototypes play a major role in decision making, concept and design validation, feature and limit exploration, as well as design verification in every phase of the product development cycle, including product planning, requirement engineering, and product development. This overview discusses the motivation for building prototypes, provides the key areas for research and explains how prototypes can assist in product planning and throughout all steps of the engineering process. Special attention is given to prototyping in the industry to support the design and testing of multimodal and multifunctional embedded systems.     

一种基于改进模拟退火算法的软硬件划分技术

提出一种应用于嵌入式系统软硬件划分的改进模拟退火算法.算法通过使用基于Cauchy分布的扰动模型和Tsallis接收准则来提高模拟退火算法的性能.通过对比经典的模拟退火软硬件划分技术以及实验结果的验证表明,使用改进模拟退火算法能加快划分的收敛,并且找到目标函数的最优值的概率也更大.     

基于关键路径和面积预测的软硬件划分方法

本文提出了一种基于关键路径和面积预测的软硬件划分方法,这种划分方法将软硬件映射和任务调度合而为一,在调度过程中同时完成软硬件的映射,充分发挥了任务调度的作用.在实验过程中,我们对比了基于模拟退火算法的软硬件划分方法(SA)和基于路径分析的软硬件划分方法(PA).实验结果表明,我们提出的方法在成功率以及结果的优化程度上都能取得更好的效果.     

Hardware/Software Co-Design of Complex Embedded Systems: An Approach Using Efficient Process Models, Multiple Formalism Specification and Validation via Co-Simulation

This paper presents a hardware/software co-design approachwhere different specification languages can be used in parallel, allowingeffective system co-modeling. The proposed methodology introduces a processmodel that extends the traditional spiral model so as to reflect the designneeds of modern embedded systems. The methodology is supported by an advancedtoolset that allows co-modeling and co-simulation using SDL, Statecharts andMATRIX_X, and interactive hardware/software partitioning. The effectivenessof the proposed approach is exhibited through two applicati on examples: thedesign of a car window lift mechanism, and the design of a MAC layer protocolfor wireless ATM networks.     

Improving Software Performance with Configurable Logic

We examine the energy and performance benefits that can be obtained by re-mapping frequently executed loops from a microprocessor to reconfigurable logic. We present a design flow that finds critical software loops automatically and manually re-implements these inconfigurable logic by implementing them in SA-C, a C language variation supportinga dataflow computation model and designed to specify and map DSP applicationsonto reconfigurable logic. We apply this design flow on several examples fromthe MediaBench benchmark suite and report the energy and performance improvements.     

嵌入式系统的软硬件协同设计

协同设计改变了传统的设计反复修改系统方案的缺点，通过综合分析系统软硬件功能，最大限度地挖掘系统软硬件之间的并发性，将软硬件开发结合得更紧密，可以大大提高设计效率，使设计出来的系统工作在最佳工作状态。本文将系统地阐述软硬件协同设计技术。     

Functional Validation of Mixed Hardware/Software Systems based on Specification, Partitioning, and Simulation of Test Cases

Tecs is a test case development methodology for the functional validation of large electronic systems, typically consisting of several custom hardware and software components. The methodology determines a hierarchical top-down test case development process including test case specification, validation, partitioning and implementation. The test case development process addresses the functional validation of the system and its components such as ASICs, boards, HW and software modules; it does not facilitate timing or performance verification. The system functions are used to define test cases at the system level and to derive sub-functions for the system components. Test cases are specified, using a special purpose formalism, and validated before they are applied to the system under test. Furthermore, we propose a technique to partition test cases corresponding to the partitioning of the system into sub-systems and components. This technique can significantly reduce system simulation time because it allows the full validation of system functions by simulation at the sub-system and component level. The system model need only be simulated with a reduced set of stimuli to validate the interfaces between sub-systems. We present a test case specification language and tools that support the proposed methodology. The validation of a switching function illustrates methodology, language, and tools.     

An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling

The paper proposes a novel heuristic technique for integrated hardware-software partitioning, hardware design space exploration and scheduling. The technique maps an application specified as a task graph on a heterogeneous architecture with an objective to minimize the latency of the task graph subject to the area constraint on the hardware coprocessor. The technique uses an iterative approach where the partitioner decides the processor mapping and HW design points of some tasks. The scheduler then simultaneously decides the processor mapping, HW design point and schedule time of the remaining tasks. There exists a tight coupling between the two design stages allowing them to produce superior quality designs in fewer iterations. The technique accounts for the time overheads due to inter-processor /intra-processor communication and shared memory access conflicts. It can therefore be used for both communication intensive and computation intensive applications. The technique also considers dynamic reconfiguration capability of the hardware coprocessor. The technique performs tradeoff analysis and maps hardware tasks to mutually exclusive temporal segments if this results in lower latency. The effectiveness of the technique is demonstrated by a case study of the JPEG image compression algorithm, comparison with an optimal ILP based approach and experimentation with synthetic graphs.     

采用软/硬件协同设计的RS译码器

RS码在数字通信系统中得到了广泛的应用，本文在分析RS译码过程的原理基础上，提出了采用软／硬件协同设计的方法来实现RS译码器，并与目前已有的纯硬件方案做了性能对比。     

System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search

This paper presents two heuristics for automatic hardware/software partitioning of system level specifications. Partitioning is performed at the granularity of blocks, loops, subprograms, and processes with the objective of performance optimization with a limited hardware and software cost. We define the metric values for partitioning and develop a cost function that guides partitioning towards the desired objective. We consider minimization of communication cost and improvement of the overall parallelism as essential criteria during partitioning. Two heuristics for hardware/software partitioning, formulated as a graph partitioning problem, are presented: one based on simulated annealing and the other on tabu search. Results of extensive experiments, including real-life examples, show the clear superiority of the tabu search based algorithm.     

COPART:一种面向约束条件的自适应软硬件划分算法

本文介绍一种将自适应算法、遗传算法和列表调度算法结合起来应用于软硬件划分问题的算法COPARTART，并提出了一种基于约束条件的开销系数自适应调整方法，该方法所获得的划分结果能够良好体现设计目标。     

改进多路软硬件划分算法的筛选法

文章提出筛选法对基于抽象体系结构模板的多路软硬件划分算法进行了改进,从而使整个软硬件划分-任务调度过程的时间大大缩短。该方法在原算法的软硬件划分和任务调度过程之间加入了一个筛选步骤,对软硬件划分结果的硬件面积进行预估,依据预估的结果进行筛选,筛选后满足要求的划分方案才进行调度,从而大大减少了调度过程的工作量。实验结果表明,加入筛选步骤后,在最终结果性能基本不损失的前提下,整个软硬件划分-任务调度过程的速度有明显提高。     

基于Markov过程的硬/软件综合系统可靠性分析

现代大型监控系统通常是一个复杂的硬/软件综合系统,其可靠性分析对于系统的设计、评估具有重要意义.综合考虑硬件、软件特点以及两者之间的相互作用关系,提出一种基于Markov过程的综合系统可靠性分析模型,模型中将系统失效分为硬件失效、软件失效与硬/软件结合失效.实际应用中,由于系统的状态数较大,提出利用循环网络方法对Markov状态转移方程进行求解,从而方便地得到系统处于各状态的瞬时概率与稳态概率.通过分析硬/软件综合系统可靠度、可用度与系统可靠性参数之间的关系,指出硬/软件结合失效将影响系统可用度,忽略硬/软件结合失效将导致可靠性估计值偏离实际值.     

SOC设计的软硬件协同验证研究

软硬件协同验证是SOC的核心技术.通过分析SOC验证方法与软硬件协同验证技术,提出C与平台相合的协同验证方法.该方法是在系统级用SystemC确定SOC系统的体系框架、存储量大小、接口IO与验证软件算法的可行性、有效性、可靠性.在硬件设计中,利用验证可重用的硬IP和软IP快速建立SOC系统,并把核心IP集成嵌入进SOC系统中.在软件设计中,利用成熟的操作系统与应用系统来仿真验证SOC芯片的功能与性能.该方法应用于一个基于ARM7TDMI的SOC设计,大大缩短了验证时间,提高了验证效率与质量.     

并行K均值聚类和贪婪算法融合的软硬件划分

提出了一种并行K均值聚类和贪婪算法融合的软硬件划分算法.算法首先将有相似属性的任务节点通过并行K均值聚类算法组成一个大的任务节点,而后使用贪婪算法划分由大的任务节点组成的系统.实验结果表明,这种软硬件划分的方法具有高效率及高面积利用率的特点,尤其对多节点的复杂任务算法的求解时间远小于贪婪算法.     

一种求解非线性整数规划的分布估计算法

分布估计算法是遗传算法和统计学习的结合,通过统计学习的手段建立解空间内个体分布的概率模型,对概率模型随机采样产生新的群体,如此反复进行,实现群体的进化。将分布估计算法推广应用到整数规划的解空间中,提出一种求解整数规划的新算法,经数值实验表明该算法有效。