Active Microelectronic Neurosensor Arrays for Implantable Brain Communication Interfaces

We have built a wireless implantable microelectronic device for transmitting cortical signals transcutaneously. The device is aimed at interfacing a cortical microelectrode array to an external computer for neural control applications. Our implantable microsystem enables 16-channel broadband neural recording in a nonhuman primate brain by converting these signals to a digital stream of infrared light pulses for transmission through the skin. The implantable unit employs a flexible polymer substrate onto which we have integrated ultra-low power amplification with analog multiplexing, an analog-to-digital converter, a low power digital controller chip, and infrared telemetry. The scalable 16-channel microsystem can employ any of several modalities of power supply, including radio frequency by induction, or infrared light via photovoltaic conversion. As of the time of this report, the implant has been tested as a subchronic unit in nonhuman primates (${sim} 1$ month), yielding robust spike and broadband neural data on all available channels.      

A miniaturized neuroprosthesis suitable for implantation into the brain

This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 /spl times/ 400-/spl mu/m pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1/spl deg/C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.     

Realization and characterization of 8×8 resonant cavity LEDarrays mounted onto CMOS drivers for POF-based interchipinterconnections

An 8×8 array of resonant-cavity light emitting diodes (RCLED's) emitting at 980 nm and flip-chip mounted onto complimentary metal-oxide-semiconductor (CMOS) integrated drivers, is presented. The RCLED's are optimized for maximal extraction efficiency into the numerical aperture of polymer optical fibers (NA=0.5) and minimal optical crosstalk. Design of the optimal cavity structure is presented, and 8×8 arrays are realized and mounted directly onto standard CMOS chips using a solder reflow technique. The CMOS integrated drivers are designed for high-speed operation and low-power consumption, and are realized in 0.8 and 0.6-μm CMOS technology. The electrooptical modules have been realized and characterized, and over 50-μW optical power coupled to POF at 3-mA drive current is reported. Open eye diagrams at operation speed up to 250 Mb/s are presented. These characteristics are compatible with CMOS integrated low-power receivers     

Area-Power Efficient VLSI Implementation of Multichannel DWT for Data Compression in Implantable Neuroprosthetics

Time-frequency domain signal processing of neural recordings, from high-density microelectrode arrays implanted in the cortex, is highly desired to ease the bandwidth bottleneck associated with data transfer to extra-cranial processing units. Because of its energy compactness features, discrete wavelet transform (DWT) has been shown to provide efficient data compression for neural records without compromising the information content. This paper describes an area-power minimized hardware implementation of the lifting scheme for multilevel, multichannel DWT with quantized filter coefficients and integer computation. Performance tradeoffs and key design decisions for implantable neuroprosthetics are presented. A 32-channel 4-level version of the circuit has been custom designed in 0.18-mum CMOS and occupies only 0.22 mm² area and consumes 76 muW of power, making it highly suitable for implantable neural interface applications requiring wireless data transfer.     

High-Power Integrated Stimulator Output Stages With Floating Discharge Over a Wide Voltage Range for Nerve Stimulation

Two integrated nerve stimulator circuits are described. Both generate passively charge-balanced biphasic stimulating pulses of 1 to 16 mA with 10-$mu $s to 1-ms widths from 6- to 24-V supplies for implanted book electrodes. In both circuits, the electrodes are floating during the passive discharge anywhere within the range of the power rails, which may be up to 24 V. The first circuit is used for stimulation only. It uses a floating depletion transistor to enable continuous discharge of the electrodes, except when stimulating, without using power. The second circuit also allows neural signals to be recorded from the same tripole. It uses a modified floating complementary metal–oxide semiconductor (CMOS) discharge switch capable of operating over a range beyond the gate-to-source voltage limits of its transistors. It remains off for long periods using no power while recording. A 0.6-$mu $m silicon-on-insulator CMOS technology has been used. The measured performance of the circuits has been verified using multiple tripoles in saline.      

An Integrated Implantable Stimulator That is Fail-Safe Without Off-Chip Blocking-Capacitors

We present a neural stimulator chip with an output stage (electrode driving circuit) that is fail-safe under single-fault conditions without the need for off-chip blocking-capacitors. To miniaturize the stimulator output stage two novel techniques are introduced. The first technique is a new current generator circuit reducing to a single step the translation of the digital input bits into the stimulus current, thus minimizing silicon area and power consumption compared to previous works. The current generator uses voltage-controlled resistors implemented by MOS transistors in the deep triode region. The second technique is a new stimulator output stage circuit with blocking-capacitor safety protection using a high-frequency current-switching (HFCS) technique. Unlike conventional stimulator output stage circuits for implantable functional electrical stimulation (FES) systems which require blocking-capacitors in the microfarad range, our proposed approach allows capacitance reduction to the picofarad range, thus the blocking-capacitors can be integrated on-chip. The prototype four-channel neural stimulator chip was fabricated in XFAB's 1-$mu{hbox {m}}$ silicon-on-insulator CMOS technology and can operate from a power supply between 5–18 V. The stimulus current is generated by active charging and passive discharging. We obtained recordings of action potentials and a strength-duration curve from the sciatic nerve of a frog with the stimulator chip which demonstrate the HFCS technique. The average power consumption for a typical 1-mA 20-Hz single-channel stimulation using a book electrode, is 200 $mu{hbox {W}}$ from a 6 V power supply. The silicon area occupation is 0.38 ${hbox {mm}}^{2}$ per channel.      

Thermal impact of an active 3-D microelectrode array implanted in the brain.

A chronically implantable, wireless neural interface device will require integrating electronic circuitry with the interfacing microelectrodes in order to eliminate wired connections. Since the integrated circuit (IC) dissipates a certain amount of power, it will raise the temperature in surrounding tissues where it is implanted. In this paper, the thermal influence of the integrated 3-D Utah electrode array (UEA) device implanted in the brain was investigated by numerical simulation using finite element analysis (FEA) and by experimental measurement in vitro as well as in vivo. The numerically calculated and experimentally measured temperature increases due to the UEA implantation were in good agreement. The experimentally validated numerical model predicted that the temperature increases linearly with power dissipation through the UEA, with a slope of 0.029 degree C/mW over the power dissipation levels expected to be used. The influences of blood perfusion, brain metabolism, and UEA geometry on tissue heating were also investigated using the numerical model.     

Brain–Silicon Interface for High-Resolution in vitro Neural Recording

A 256-channel integrated interface for simultaneous recording of distributed neural activity from acute brain slices is presented. An array of 16 times 16 Au recording electrodes are fabricated directly on the die. Each channel implements differential voltage acquisition, amplification and band-pass filtering. In-channel analog memory stores an electronic image of neural activity. A 3 mm times 4.5 mm integrated prototype fabricated in a 0.35-mum CMOS technology is experimentally validated in single-channel extracellular in vitro recordings from the hippocampus of mice and in multichannel simultaneous recordings in a controlled environment     

A Partial-Current-Steering Biphasic Stimulation Driver for Vestibular Prostheses

This paper describes a novel partial-current-steering stimulation circuit for implantable vestibular prostheses. The drive hardware momentarily delivers a charge-balanced asymmetric stimulus to a dummy load before steering towards the stimulation electrodes. In this fashion, power is conserved while still gaining from the benefits of current steering. The circuit has been designed to be digitally programmable as part of an implantable vestibular prosthesis. The hardware has been implemented in AMS 0.35 $mu{hbox{m}}$ 2P4M CMOS technology.      

Power feasibility of implantable digital spike sorting circuits for neural prosthetic systems.

A new class of neural prosthetic systems aims to assist disabled patients by translating cortical neural activity into control signals for prosthetic devices. Based on the success of proof-of-concept systems in the laboratory, there is now considerable interest in increasing system performance and creating implantable electronics for use in clinical systems. A critical question that impacts system performance and the overall architecture of these systems is whether it is possible to identify the neural source of each action potential (spike sorting) in real-time and with low power. Low power is essential both for power supply considerations and heat dissipation in the brain. In this paper we report that state-of-the-art spike sorting algorithms are not only feasible using modern complementary metal oxide semiconductor very large scale integration processes, but may represent the best option for extracting large amounts of data in implantable neural prosthetic interfaces.     

Design of high-speed,high-density CNNS in cmos technology

An analogue VLSI circuit architecture for the CMOS implementation of cellular neural networks (CNNs) is presented. It is based exclusively on the use of small capacitors and operational transconductance amplifiers operating in continuous time. Integrated circuit implementations of this architecture are very well suited for processing applications requiring large array size and high speed. We describe a systematic design approach for those circuits and present the design, fabrication and testing of two chips. These chips are used for connected component detection applications and are the first working integrated circuit implementation of a CNN. They contain 2000 transistors and have been fabricated using 2 μm CMOS technology. the density is 32 cells per square millimetre of silicon and the time constant of the processing is of the order of 10^?7 s. Experimental results of static and dynamic tests are given, including a complete image-processing example.     

A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC

This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm _* 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.     

Programmable analogue vlsi cnn chip with local digital logic

A new integrated circuit cellular neural network implementation with digitally or continuously selectable template coefficients is presented. Local logic and memory are added into each cell, providing a simple dual (analogue and digital) computing structure. Variable gain OTAs are used as the voltage-controlled current sources to programme the template element values. the cells have local switched feedback (both analogue and digital) to feed from the output to the input or state capacitor. Therefore this analogue array processor can be applied to solve problems with a sequence of different templates. A 4 × 4 CNN circuit is realized using the 2 μm analogue CMOS process.     

An Ultra Low-Power CMOS Automatic Action Potential Detector

We present a low-power complementary metal–oxide semiconductor (CMOS) analog integrated biopotential detector intended for neural recording in wireless multichannel implants. The proposed detector can achieve accurate automatic discrimination of action potential (APs) from the background activity by means of an energy-based preprocessor and a linear delay element. This strategy improves detected waveforms integrity and prompts for better performance in neural prostheses. The delay element is implemented with a low-power continuous-time filter using a ninth-order equiripple allpass transfer function. All circuit building blocks use subthreshold OTAs employing dedicated circuit techniques for achieving ultra low-power and high dynamic range. The proposed circuit function in the submicrowatt range as the implemented CMOS 0.18- $mu{rm m}$ chip dissipates 780 nW, and it features a size of 0.07 ${rm mm}^{2}$. So it is suitable for massive integration in a multichannel device with modest overhead. The fabricated detector succeeds to automatically detect APs from underlying background activity. Testbench validation results obtained with synthetic neural waveforms are presented.      

An Energy-Efficient Micropower Neural Recording Amplifier

This paper describes an ultralow-power neural recording amplifier. The amplifier appears to be the lowest power and most energy-efficient neural recording amplifier reported to date. We describe low-noise design techniques that help the neural amplifier achieve input-referred noise that is near the theoretical limit of any amplifier using a differential pair as an input stage. Since neural amplifiers must include differential input pairs in practice to allow robust rejection of common-mode and power supply noise, our design appears to be near the optimum allowed by theory. The bandwidth of the amplifier can be adjusted for recording either neural spikes or local field potentials (LFPs). When configured for recording neural spikes, the amplifier yielded a midband gain of 40.8 dB and a -3-dB bandwidth from 45 Hz to 5.32 kHz; the amplifier's input-referred noise was measured to be 3.06 muV_rms while consuming 7.56 muW of power from a 2.8-V supply corresponding to a noise efficiency factor (NEF) of 2.67 with the theoretical limit being 2.02. When configured for recording LFPs, the amplifier achieved a midband gain of 40.9 dB and a -3-dB bandwidth from 392 mHz to 295 Hz; the input-referred noise was 1.66 muV_rms while consuming 2.08 muW from a 2.8-V supply corresponding to an NEF of 3.21. The amplifier was fabricated in AMI's 0.5-mum CMOS process and occupies 0.16 mm² of chip area. We obtained successful recordings of action potentials from the robust nucleus of the arcopallium (RA) of an anesthesized zebra finch brain with the amplifier. Our experimental measurements of the amplifier's performance including its noise were in good accord with theory and circuit simulations.     

Ultralow power voltage reference circuit for implantable devices in standard CMOS technology

An ultralow power CMOS voltage reference for body implantable devices is presented in this paper. The circuit core consists of only regular threshold voltage PMOS transistors, thus leading to a very reduced output voltage dispersion, defined as σ/μ, and extremely low power consumption. A mathematical model of the generated reference voltage was obtained by solving circuit equations, and its numerical solution has been validated by extensive electrical simulations using a commercial circuit simulator. The proposed solution incorporates a passive RC low-pass filter, to enhance power supply rejection (PSR) over a wide frequency range, and a speed-up section, to accelerate the switching-on of the circuit. The prototype was implemented in 0.18 μm standard CMOS technology and is able to operate with supply voltages ranging from 0.7 to 1.8 V providing a measured output voltage value of 584.2 mV at the target temperature of 36° C. The measured σ/μ dispersion of the reference voltage generated is 0.65% without the need of trimming. At the minimum supply of 0.7 V, the experimental power consumption is 64.5 pW, while the measured PSR is kept below –60 dB from DC up to the MHz frequency range.     

Development of radio frequency transmitters including on‐chip antenna for intelligent human sensing systems

This paper presents the essentials of the development of an integrated smart microsensor system that has been developed to monitor the motion and vital signs of humans in various environments. Integration of RF transmitter technology with complementary metal‐oxide‐semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize wireless smart microsensors for the monitoring system. Sensors for the measurement of body temperature, perspiration, heart rate (pressure sensor), and motion (accelerometers) are candidates for integration on the wireless smart microsensor system. In this paper, the development of radio frequency transmitter (RF) that will be integrated on wireless smart microsensors is presented. A voltage controlled RF‐CMOS oscillator (VCO) has been fabricated for the 300‐MHz frequency band applications. Also, spiral inductors for an LC resonator and an integrated antenna have been realized with a CMOS‐compatible metallization process. The essential RF components have been fabricated and evaluated experimentally. The fabricated CMOS VCO showed a conversion factor from voltage to frequency of about 81 MHz/V. After matching the characteristic impedance (50 Ω) of the on‐chip integrated antenna and the VCO output, more than 5 m signal transmission from the microchip antenna has been observed. The transmitter showed remarkable improvement in transmission power efficiency by correct matching with the microchip antenna. Essential technologies of the RF transmitter for the wireless smart microsensors have been successfully developed. Also, for the 300‐MHz band application, the integrated RF transmitter, with the CMOS oscillator and the on‐chip antenna, has been successfully demonstrated for the first time. Copyright © 2007 Institute of Electrical Engineers of Japan© 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Wireless Neural Recording With Single Low-Power Integrated Circuit

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6- $mu$m 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor.      

Micropower CMOS Integrated Low-Noise Amplification, Filtering, and Digitization of Multimodal Neuropotentials

Electrical activity in the brain spans a wide range of spatial and temporal scales, requiring simultaneous recording of multiple modalities of neurophysiological signals in order to capture various aspects of brain state dynamics. Here, we present a 16-channel neural interface integrated circuit fabricated in a 0.5 mum 3M2P CMOS process for selective digital acquisition of biopotentials across the spectrum of neural signal modalities in the brain, ranging from single spike action potentials to local field potentials (LFP), electrocorticograms (ECoG), and electroencephalograms (EEG). Each channel is composed of a tunable bandwidth, fixed gain front-end amplifier and a programmable gain/resolution continuous-time incremental DeltaSigma analog-to-digital converter (ADC). A two-stage topology for the front-end voltage amplifier with capacitive feedback offers independent tuning of the amplifier bandpass frequency corners, and attains a noise efficiency factor (NEF) of 2.9 at 8.2 kHz bandwidth for spike recording, and a NEF of 3.2 at 140 Hz bandwidth for EEG recording. The amplifier has a measured midband gain of 39.6 dB, frequency response from 0.2 Hz to 8.2 kHz, and an input-referred noise of 1.94 muV _rms while drawing 12.2 muA of current from a 3.3 V supply. The lower and higher cutoff frequencies of the bandpass filter are adjustable from 0.2 to 94 Hz and 140 Hz to 8.2 kHz, respectively. At 10-bit resolution, the ADC has an SNDR of 56 dB while consuming 76 muW power. Time-modulation feedback in the ADC offers programmable digital gain (1-4096) for auto-ranging, further improving the dynamic range and linearity of the ADC. Experimental recordings with the system show spike signals in rat somatosensory cortex as well as alpha EEG activity in a human subject.     

A 128-Channel 6 mW Wireless Neural Recording IC With Spike Feature Extraction and UWB Transmitter

This paper reports a 128-channel neural recording integrated circuit (IC) with on-the-fly spike feature extraction and wireless telemetry. The chip consists of eight 16-channel front-end recording blocks, spike detection and feature extraction digital signal processor (DSP), ultra wideband (UWB) transmitter, and on-chip bias generators. Each recording channel has amplifiers with programmable gain and bandwidth to accommodate different types of biological signals. An analog-to-digital converter (ADC) shared by 16 amplifiers through time-multiplexing results in a balanced trade-off between the power consumption and chip area. A nonlinear energy operator (NEO) based spike detector is implemented for identifying spikes, which are further processed by a digital frequency-shaping filter. The computationally efficient spike detection and feature extraction algorithms attribute to an auspicious DSP implementation on-chip. UWB telemetry is designed to wirelessly transfer raw data from 128 recording channels at a data rate of 90 Mbit/s. The chip is realized in 0.35 $mu {rm m}$ complementary metal–oxide–semiconductor (CMOS) process with an area of 8.8$,times,$ 7.2 $, {hbox {mm}}^{2}$ and consumes 6 mW by employing a sequential turn-on architecture that selectively powers off idle analog circuit blocks. The chip has been tested for electrical specifications and verified in an ex vivo biological environment.