Impact of defects on the high-κ/MG stack: The electrical characterization challenge

The integration of high-κ dielectrics in MOSFET devices is beset by many problems. In this paper a review on the impact of defects in high-κ materials on the MOSFET electrical characteristics is presented. Beside the quality of the bulk of the dielectric itself, the interfaces between the high-κ and the interfacial oxide layer and the gate electrode are of crucial importance. When poly-Si is used as gate electrode, the defects at the poly-Si/high-κ interface control the band alignment as well as the gate depletion. The quality and thickness of the interfacial SiO₂ controls both the carrier mobility in the channel as well as the kinetics of charging and discharging of pre-existing high-κ defects. The quality of the interfacial layer has also important consequences for reliability specifications like negative bias instability and dielectric breakdown.     

Probing stress effects in HfO2 gate stacks with time dependent measurements

Effects of constant voltage stress (CVS) on gate stacks consisting of an ALD HfO₂ dielectric with various interfacial layers were studied with time dependent sensing measurements: DC I–V, pulse I–V, and charge pumping (CP) at different frequencies. The process of injected electron trapping/de-trapping on pre-existing defects in the bulk of the high-κ film was found to constitute the major contribution to the time dependence of the threshold voltage (V_t) shift during stress. The trap generation observed with the low frequency CP measurements is suggested to occur within the interfacial oxide layer or the interfacial layer/high-κ interface, with only a minor effect on V_t.     

Monte carlo study of mobility in Si devices with -based oxides

HfO₂-based high-κ dielectrics are among the most likely candidates to replace SiO₂ and the currently favoured oxinitride in the next generation of MOSFETs. High-κ materials allow the use of a thicker gate dielectric, maintaining the gate capacitance with reduced gate leakage. However, they lead to a fundamental mobility degradation due to the coupling of carriers to surface soft (low-energy) optical phonons. Comparing the vertical field dependence of the mobility for HfO₂ and SiO₂, the severe degradation in mobility in the presence of high-κ becomes evident. The introduction of a SiO₂ interfacial layer between the channel and the HfO₂ mitigates this degradation, by increasing the effective distance between the carriers and the SO phonons, thus decreasing the interaction strength, this does though lead to an increase in the equivalent oxide thickness (EOT) of the gate dielectric. The material of choice for the first commercial introduction of high-κ gate stacks is Hafnium Silicate (Si_xHf_1-xO₂). This alloy stands up better to the processing challenges and as a result suffers less from dielectric fluctuations. We show that as the fraction of Hf increases within the alloy, the inversion layer mobility is shown to decrease due to the corresponding decrease in the energy of the surface optical phonons and increase in the dielectric constant of the oxide.     

Refined electrical analysis of two charge states transition characteristic of “borderless” silicon nitride

In this paper we evaluate the electrical properties of silicon nitride so called “borderless nitride” deposited by PECVD process in the pre metal dielectric stack. Thus metal/silicon nitride/semiconductor structures have been analysed by an original electrical characterization based on C(V) and I(V) hysteresises. The objective is to understand how this material, initially introduced as etch stop layer and contaminant diffusion barrier, can impact active device performances. It appears that silicon nitride contains a huge defect quantity characterized in a non steady state and strongly influenced by maximum voltage applied. These charges can be balanced between either positive and negative states and are suspected to be K centers defects existing under two paramagnetic states K⁺ and K⁻. In addition, a RF power variation of SiH₄/NH₃ ratio, giving refractive indexes from 1.94 to 2.77, have shown that flatband voltage shift decreases with [Si]/[N] ratio whereas leakage current increases.     

Improvement of gate dielectric reliability for p+poly MOS devices using remote PECVD top nitride deposition on ultra-thin (2.4–6 nm) gate oxides

Dual layer dielectrics have been formed by remote PECVD deposition of ultra-thin (0.4–1.2 nm) nitrides onto thin thermal oxides grown on n-type Si(100) substrates. Activation of boron-implanted p+ polycrystalline silicon gate electrodes was accomplished by a high temperature anneal, 1–4 min at 1000°C. Boron penetration through the dielectric film to the n-type substrate was investigated by performing a quasi-static C–V analysis and monitoring the flatband voltage shift. Boron penetration was effectively stopped by a 0.8 nm nitride film, and partially stopped by a 0.4 nm nitride film. In addition, the charge to breakdown as monitored by the Q_bd value to 50% cumulative failure was highest for the device with the 0.8 nm top nitride, and decreased significantly in the thermal oxide. However there were essentially no differences in the mid-gap interface state densities, D_it, between oxide and nitride/oxide gate dielectric structures with Al gate. It is concluded that the 0.8 nm of plasma nitride was sufficient to block boron atom out-diffusion from a heavily implanted p+ poly-silicon gate electrode under the conditions of an aggressive implant activation anneal to improve the dielectric reliability.     

Precise determination of metal effective work function and fixed oxide charge in MOS capacitors with high-κ dielectric

Effective metal work function, Φ_m,eff, and oxide charge, Q_ox, were determined on MOS capacitors with slanted high-κ dielectric. Φ_m,eff and Q_ox were extracted using flat-band voltage shift versus equivalent oxide thickness data, both deduced from the capacitance–voltage measurements. Slanted HfSiO_x dielectric (initial thickness was 9 nm) was prepared by gradual etching in HF-based solution. As a metal electrode, thin Ru-films were deposited by MOCVD-derived technique—Atomic Vapor Deposition^® on the slanted HfSiO_x as well as SiO₂ dielectrics. The Φ_m,eff of Ru was found to be 4.74 and 4.81 eV for Ru/HfSiO_x and Ru/SiO₂ gate stacks, respectively. Ultraviolet photoelectron spectroscopy yields the work function of 4.62 eV in agreement with the capacitance–voltage data. We also studied the I–V characteristics of the Ru/HfSiO_x/Si MOS capacitors. The barrier height was found to be constant within the HfSiO_x bulk.     

Thermal Ta2O5––alternative to SiO2 for storage capacitor application

Tantalum pentoxide thin layers (10–100 nm) obtained by thermal oxidation of rf sputtered Ta films on Si have been investigated with respect of their dielectric, structural and electric properties. It is established that stoichiometric Ta₂O₅ detected at the surface of the layers is reduced to tantalum suboxides in their depth. The oxide parameters are discussed in terms of a presence of an unavoidable ultrathin SiO₂ between Si and Ta₂O₅ and bond defects in both the oxide and the interface transition region. Conditions which guarantee obtaining high quality tantalum oxide with a dielectric constant of 32–35 and a leakage current less than 10⁻⁷–10⁻⁸ A/cm² at 1.5 V (SiO₂ equivalent thickness of 2.5–3 nm) are established. These specifications make the layers obtained suitable alternative to SiO₂ for high density DRAMs application.     

Growth of lanthanum oxide films for application as a gate dielectric in CMOS technology

We have investigated properties of insulating lanthanum oxide (La₂O₃) films in connection with the replacement of silicon oxide (SiO₂) gate dielectrics in new generation of CMOS devices. The La₂O₃ layers were grown using metal organic chemical vapour deposition (MOCVD) at 500 °C. X-ray diffraction analysis revealed polycrystalline character of the films grown above 500 °C. The X-ray photoemission spectroscopy detected lanthanum carbonate as a principal impurity in the films and lanthanum silicate at the interface with silicon. Density of oxide charge, interface trap density, leakage currents and dielectric constant ( κ) were extracted from the C-V and I-V measurements. Electrical properties, in particular dielectric constant of the MOCVD grown La₂O₃ are discussed with regard to the film preparation conditions. The as grown film had κ11. Electrical measurements indicate possible presence of oxygen vacancies in oxide layer. The O₂-annealed La₂O₃ film had κ17.     

Effects of Ti content and wet-N2 anneal on Ge MOS capacitors with HfTiO gate dielectric

Thin HfTiO gate dielectric is deposited by reactive co-sputtering method followed by wet or dry N₂ anneal. The effects of Ti content on the performance of HfTiO gate dielectric are investigated by using different sputtering powers for the Ti target. Experimental results indicate that as the Ti content increases, the dielectric constant (κ) can increase up to 40 for a Ti content of 28%. However, when the Ti content is too high, the interface properties and gate leakage properties are deteriorated. On the contrary, results show that owing to the hydrolyzable property of GeO_x, the wet-N₂ anneal can greatly suppress the growth of unstable low-κ GeO_x interlayer, resulting in lower interface-state density and gate leakage current, in addition to larger κ value. In this study, when the sputtering power of the Ti target is 80 W together with a 25-W power for the Hf target and a post-deposition anneal (PDA) in wet-N₂ ambient at 500 °C for 300 s, excellent device performance is achieved: equivalent oxide thickness of 0.72 nm, equivalent dielectric constant of 39, interface-state density of 6.5 × 10¹¹ eV⁻¹ cm⁻² and gate leakage current of 5.7 × 10⁻⁴ A/cm² at V_g = 1 V. Therefore, in order to obtain high-quality HfTiO gate dielectric for small-scaled Ge MOS devices, not only should the Ti content be optimized, the PDA should also be done in a wet-N₂ ambient.     

Full-band tunneling in high-κ dielectric MOS structures

High-κ oxides such as ZrO₂ and HfO₂ have attracted great interest, due to their physical properties, suitable to replacement of SiO₂ as gate dielectric materials. In this work, we investigate the tunneling properties of ZrO₂ and HfO₂ high-κ oxides, by applying quantum mechanical methods that include the full-band structure of Si and oxide materials. Semiempirical sp³s*d tight-binding parameters have been determined to reproduce ab initio band dispersions. Transmission coefficients and tunneling current have been calculated for Si/ZrO₂/Si and Si/HfO₂/Si MOS structures, showing a very low gate leakage current in comparison to SiO₂-based structures with equivalent oxide thickness.     

New dielectric material system of Nd(Mg1/2Ti1/2)O3–CaTiO3 at microwave frequency

The microwave dielectric properties of (1 − x)CaTiO₃–xNd(Mg_1/2Ti_1/2)O₃ (0.1  x  1.0) ceramics prepared by the conventional solid state method have been investigated. The system forms a solid solution throughout the entire compositional range. The dielectric constant decreases from 152 to 27 as x varies from 0.1 to 1.0. In the (1 − x)CaTiO₃–xNd(Mg_1/2Ti_1/2)O₃ system, the microwave dielectric properties can be effectively controlled by varying the x value. At 1400 °C, 0.1CaTiO₃–0.9Nd(Mg_1/2Ti_1/2)O₃ has a dielectric constant (ε_r) of 42, a Q × f value of 35 000 GHz and a temperature coefficient of resonant frequency (τ_f) of −10 ppm/°C. As the content of Nd(Mg_1/2Ti_1/2)O₃ increases, the highest Q × f value of 43 000 GHz for x = 0.9 is achieved at the sintering temperature 1500 °C.     

Electrical characterization and analysis techniques for the high-κ era

Various conventional and novel electrical characterization techniques have been combined with careful, robust analysis to properly evaluate high-κ gate dielectric stack structures. These measurement methodologies and analysis techniques have enhanced the ability to separate pre-existing defects that serve as fast transient charging and discharging sites from defects generated with stress. In addition, the differentiation of electrically active bulk high-κ traps, silicon substrate interface traps, and interfacial layer traps has been effectively demonstrated.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

A new empirical extrapolation method for time-dependent dielectric breakdown reliability projections of thin SiO2 and nitride–oxide dielectrics

The results of an investigation of time-dependent dielectric breakdown (TDDB) of thin gate oxide and nitride–oxide (N–O) films are presented for a wide range of fields and temperatures. It was found that TDDB of both gate oxide and N–O films followed a power-law dependence of mean value of average leakage current (I_avg). An empirical extrapolation model using average leakage current as a major parameter was proposed based on experimental results. This proposed lifetime model has been successful to predict dielectric reliability. It could continuously fit the entire breakdown data from both wafer level and module level stress. The extrapolation from wafer level data to module data was excellent. The power of current versus TDDB showed exponential dependence on oxide thickness. This proposed TDDB projection methodology also worked for N–O films with an abrupt current increase in the I–V curve at a certain voltage well below the breakdown voltage, while the conventional models clearly failed to fit all data from this region. The observation of TDDB dependence of the current may open a new window for oxide lifetime projections and provide some insights into the nature of oxide breakdown and its implications for reliability studies.     

Interfacial layer quality effects on low-frequency noise (1/f) in p-MOSFETs with advanced gate stacks

The effects of interfacial layer quality on the low-frequency noise behavior of p-channel MOSFETs with high-κ gate dielectric and metal gate are investigated. Devices with chemically grown SiO₂ interfacial layers (0.8 nm) are compared with N₂O (0.8 nm) interfacial oxides. A 0.4 nm SiO₂ interfacial layer device is used for comparison purposes. A cross-over kind of behavior has been observed in N₂O devices, which occur at lower gate voltages (1.2–1.3 V) when normalized spectral densities and input referred noise are investigated. This behavior is found to be closely related to the observed transconductance variation in these devices. The dominant mechanism of 1/f noise is found to be Hooge’s mobility fluctuations. Hooge’s parameter, as a figure of merit, shows an increase for 0.4 nm devices when compared to 0.8 nm devices, while 0.8 nm N₂O devices confirm their cross-over nature.     

Valence band structures and optical transitions of Ga1−xInxNyAs1−y/GaAs compressively strained quantum wells

The electronic structures of the Ga_1−xIn_xN_yAs_1−y/GaAs compressively strained quantum wells (QW) are investigated using 6×6 k·p Hamiltonian including the heavy hole, light hole and spin–orbit splitting band. The curves of dependence of transition energy on well width and N mole fraction are obtained. The valence subband energy dispersion curves, density of state and TE and TM squared optical transition matrix elements of three possible QW structures for emitting 1.3 μm wavelength are given.     

Improved electrical properties using SrTiO3/Y2O3 bilayer dielectrics for MIM capacitor applications

In this paper, we show that the capacitance–voltage linearity of MIM structures can be enhanced using SrTiO₃ (STO)/Y₂O₃ dielectric bilayers. The C(V) linearity is significantly improved by combining two dielectric materials with opposite permittivity-voltage responses. Three STO/Y₂O₃ stacks with different thicknesses were realized and compared to a 20 nm STO single layer structure. We observed that an increase in the Y₂O₃ thickness leads to an improvement in the voltage linearity, while maintaining an overall capacitance density greater than 10 fF/μm².     

New approach for forming bulk-heterojunction solar cells comprising a π-conjugated polymer and C60

A new approach for high-efficiency polymer solar cells utilizing a BHJ active layer consisting of poly(3-hexylthiophene) (P3HT) as a donor and buckminsterfullerene, C₆₀ as an acceptor was demonstrated. P3HT/C₆₀ BHJ films were made possible by in situ formation of C₆₀ from solubilized addends, C₆₀–CpCO₂R (R = Hex, Oct, and EHex) by retro Diels–Alder reaction at, or above, 100 °C. These cells exhibit enhanced performances compared to as-prepared P3HT/C₆₀ BHJ films, showing better morphology.     

Integrating thick copper/Black Diamond™ layer in CMOS interconnect process for RF passive components

Thick copper (Cu)/Black Diamond™ (BD) layer up to 4 μm has successfully been integrated in CMOS interconnect process to improve the quality of on-chip RF passive components. It is shown that BD film is easy to crack when its thickness is up to 4 μm. However, by inserting one or few layers of dielectric material, BloK™, the stress in the entire dielectric film stack can be reduced. Although the reduction of the tensile stress of the stack is insignificant, the inserted BloK™ layer effectively prevents cracking from happening in the film stack. Spiral inductors have been integrated in developed Cu/BD (4 μm) top-metal-layer. Both Q value and resonate frequency of developed inductors are improved comparing to the inductors fabricated in previous top-metal-layer with 1 μm Cu/SiO₂ stack.     

Pentacene organic field-effect transistors with polymeric dielectric interfaces: Performance and stability

Low-voltage pentacene organic field-effect transistors (OFETs) with different gate dielectric interfaces are studied and their performance in terms of electrical properties and operational stability is compared. Overall high electrical performance is demonstrated at low voltage by using a 100 nm-thick high-κ gate dielectric layer of aluminum oxide (Al₂O₃) fabricated by atomic layer deposition (ALD) and modified with hydroxyl-free low-κ polymers like polystyrene (PS), divinyltetramethyldisiloxane-bis(benzocyclobutene) (BCB) (Cyclotene™, Dow Chemicals), and as well as with the widely used octadecyl-trichlorosilane (OTS). Devices with PS and BCB dielectric surfaces exhibit almost similar electrical performance with high field-effect mobilities, low subthreshold voltages, and high on/off current ratios. The higher mobility in pentacene transistors with PS can be correlated to the better structural ordering of pentacene films, as demonstrated by atomic force microscopy (AFM) images and X-ray diffraction (XRD). The devices with PS show good electrical stability under bias stress conditions (V_GS = V_DS = −10 V for 1 h), resulting in a negligible drop (2%) in saturation current (I_DS) in comparison to that in devices with OTS (12%), and to a very high decay (30%) for the devices with BCB.