Plasma Etching for Sub-45-nm TaN Metal Gates on High-k Dielectrics

Etching of TaN gates on high-k dielectrics (HfO₂ or HfAlO) is investigated using HBr/Cl₂ chemistry in a decoupled plasma source (DPS). The patterning sequence includes 248-nm lithography, plasma photoresist trimming, etching of a SiN-SiO₂ hard mask, and photoresist stripping, followed by TaN etching. TaN etching is studied by design of experiment (DOE) with four variables using a linear model with interactions. It is found that at a fixed substrate temperature and wafer chuck power, etch critical dimensions (CD) gain decreases with decreasing HBr/Cl₂ flow rate ratio and pressure and with increasing source power and total gas flow rate. Based on these DOE findings, subsequent optimization is performed and a three-step etching process is developed; a main feature of the process is progressively increasing HBr/Cl₂ flow rate ratio. The optimized process provides etch CD gain within 2 nm and gate profile close to vertical and reliable etch-stop on high-k dielectric. This process is successfully applied to the fabrication of the 40-nm HfAlO/TaN gate stack p-MOSFETs with good electrical parameters     

Reactor characterization for a process to etchSi3N4 formed on thin SiO2

A plasma etching process for patterning LPCVD (low-pressure chemical vapor deposition) Si₃N₄ which has been formed on thin thermally grown SiO₂ has been developed and characterized with an Applied Materials 8110 batch system using 100-mm-diameter silicon wafers. To fulfill the primary process objectives of minimal critical dimension (CD) loss (~0.08 μm), vertical profiles after etch, retention of some of the underlying thermal SiO₂, and batch etch uniformity, the reactor has been characterized by evaluating the effects of variation of reactor pressure (15 to 65 mTorr), O₂ concentration by flow rate (30 to 70%) of an O₂/CHF₂ mixture, and DC bias voltage (-200 to -550 V). Analysis of the resulting etch rate, etch uniformity, dimensional, and profile data suggests that satisfactory processing may be achieved at low reactor pressure (~25 mTorr), 50-60% O₂ by flow rate in O₂/CHF₃, and low DC bias (-200 to -250 V)     

Effect of a Two-Step Recess Process Using Atomic Layer Etching on the Performance of In0.52Al0.48As/In0.53Ga0.47As p-HEMTs

The characteristics of 0.15- mum InAlAs/InGaAs pseudomorphic high-electron mobility transistors (p-HEMTs) that were fabricated using the Ne-based atomic layer etching (ALET) technology and the Ar-based conventional reactive ion etching (RIE) technology were investigated. As compared with the RIE, the ALET used a much lower plasma energy and thus produced much lower plasma-induced damages to the surface and bulk of the In_0.52AI_0.48As barrier and showed a much higher etch selectivity (~70) of the InP spacer against the In_0.52Al_0.48As barrier. The 0.15-mum InAlAs/InGaAs p-HEMTs that were fabricated using the ALET exhibited improved G_m,max (1.38 S/mm), I_ONn/I_OFF(1.18X10⁴), drain-induced barrier lowering (80 mWV), threshold voltage uniformity (V_th,avg = -190 mV and alpha = 15 mV), and ftau (233 GHz), mainly due to the extremely low plasma-induced damage in the Schottky gate area.     

Fabrication of 0.15-μm Γ-Shaped Gate In0.52Al0.48As/In0.6Ga0.4As Metamorphic HEMTs Using DUV Lithography and Tilt Dry-Etching Technique

An In_0.52Al_0.48As/In_0.6Ga_0.4 As metamorphic high-electron mobility transistor (MHEMT) with 0.15-mum Gamma-shaped gate using deep ultraviolet lithography and tilt dry-etching technique is demonstrated. The developed submicrometer gate technology is simple and of low cost as compared to the conventional E-beam lithography or other hybrid techniques. The gate length is controllable by adjusting the tilt angle during the dry-etching process. The fabricated 0.15-mum In_0.52Al_0.48As/In_0.6Ga_0.4As MHEMT using this novel technique shows a saturated drain-source current of 680 mA/mm and a transconductance of 728 mS/mm. The f_T and f_max of the MHEMT are 130 and 180 GHz, respectively. The developed technique is a promising low-cost alternative to the conventional submicrometer E-beam gate technology used for the fabrication for GaAs MHEMTs and monolithic microwave integrated circuits     

Reactive ion etching of Ta-Si-N diffusion barriers in CHF3+O2

Reactive ion etching of Ta₃₆Si₁₄N₅₀ diffusion barrier layers was performed in CHF₃+O₂ plasmas. Etch depths and rates were determined as a function of etch gas composition, cathode power, and etching time. Etching proceeds only after an initial delay which depends on gas composition and cathode power. This delay is attributed to the presence of a native surface oxide which must first be removed before etching can commence. Maximum etch rate was attained at 62.5% O₂ concentration, which also corresponds to minimum delay     

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited Al2O3 as Gate Dielectric

High-performance inversion-type enhancement-mode n-channel In_0.53Ga_0.47As MOSFETs with atomic-layer-deposited (ALD) Al₂O₃ as gate dielectric are demonstrated. The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general. A 0.5-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 8 nm shows a gate leakage current less than 10^-4 A/cm² at 3-V gate bias, a threshold voltage of 0.25 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V. The midgap interface trap density of regrown Al₂O₃ on In_0.53Ga_0.47As is ~1.4 x 10¹²/cm² ldr eV which is determined by low-and high-frequency capacitance-voltage method. The peak effective mobility is ~1100 cm² / V ldr s from dc measurement, ~2200 cm²/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 0.5-1.0-MV/cm effective electric field.     

H2/O2 plasma on polysilicon thin-filmtransistor

It is reported for that H₂ plasma followed by O₂ plasma is more effective for passivating grain boundary states in polysilicon thin film. Polysilicon thin-film transistors (TFTs) made after H₂/O₂ plasma treatment can exhibit a turn-on threshold voltage of -0.1 V, a subthreshold swing of 0.154 V/decade, an ON/OFF current ratio I_on/I_off over 1×10⁸, and an electron mobility of 40.2 cm² /V-s     

Mobility study on RIE etched silicon surfaces usingSF6/O2 gas etchants

A methodology for the measurement of the inversion layer mobility on trench gate structures, which allows independent measurement of the sidewall and bottom surface mobilities, is described. Using this method, the inversion layer mobility has been experimentally studied for trenches formed using the SF₆/O₂ method on diffused base regions of power UMOSFETs. The effect of several post RIE surface treatments on the surface mobility is reported. The measured sidewall mobilities have been found to be comparable to those previously reported for other RIE etchants. These results are of interest for the design of devices using the trench gate (UMOS) technology     

Plasma damage and photo-annealing effects of thin gate oxides andoxynitrides during O2 plasma exposure

Plasma-induced damage effects of oxides and oxynitrides are studied using metal-oxide-semiconductor (MOS) test capacitors in an O ₂ plasma environment inside a capacitive-coupled parallel plate RF etcher. Damage to both covered and sidewall-exposed samples are compared. As expected, it was found that as the exposure time was increased, more damage to the oxide was observed. Furthermore, N₂ O-samples showed better immunity to O₂-plasma damage than the thermally grown O₂ samples during O₂ plasma exposure. However, the edge-intensive sidewall-exposed structures showed surprisingly less damage than the fully covered structures after a fixed plasma exposure time. This reduced damage effect for the sidewall-exposed structures is believed to be due to an in situ annealing as the result of the photoelectron injection by low-energy UV light interacting with the substrate. The in situ annealing does not occur in the fully covered structure since the low-energy UV light is blocked by the thick polysilicon gate. The results indicate that plasma damage evaluation using fully covered capacitors alone cannot be used to predict the actual damage in CMOS integrated circuits where there are almost always exposed thin oxide structures     

Transformer coupled plasma dielectric etch for 0.25 μm technologies

Manufacturable etch processes for 0.18 μm technology TEOS bi-level contacts and vias (TEOS or TEOS/FOX/TEOS) are demonstrated in a low pressure high density reactor. Good CD control and high yields are demonstrated for structures down to 0.25 μm. In the process regimes used, the photoresist etch rate and the selectivity to underlayer are correlated with the amount of free fluorine in the plasma. The same TCP 9100 reactor can be used for low k polymer (Silk™ from Dow Chemical) etching with in situ hardmask open. A compromise between hard mask facetting and bowing has to be made unless passivating gases are added to an O₂/N₂ chemistry. For several architectures, initial results show potential integration with Cu.     

Effects of controlled texturization of the crystalline Si surfaceon the SiO2/Si effective barrier height

A two-stage plasma etch texturination process to control the level of crystalline silicon surface roughness has been investigated. Initially, a Cl₂ plasma etch is used to produce a very rough Si surface. This is followed by an isotropic SF₆ plasma etch, whose etch time is used to reduce and control the level of surface roughness created by the previous step. Oxides grown on texturized Si surfaces with short SF₆ etch times exhibit lower effective SiO₂/Si barrier height and greater electron injection enhancement than those with longer SF₆ etch times     

MOS characteristics of ultrathin SiO2 prepared byoxidizing Si in N2O

MOS characteristics of ultrathin gate oxides prepared by furnace oxidizing Si in N₂O have been studied. Compared to control oxides grown in O₂, N₂O oxides exhibit significantly improved resistance to charge trapping and interface state generation under hot-carrier stressing. In addition, both charge to breakdown and time to breakdown are improved considerably. MOSFETs with N₂O gate dielectrics exhibit enhanced current drivability and improved resistance to g_m degradation during channel hot-electron stressing     

A Comparative Study of HfTaON/SiO2 and HfON/SiO2 Gate Stacks With TaN Metal Gate for Advanced CMOS Applications

The electrical characteristics of a novel HfTaON/SiO₂ gate stack, which consists of a HfTaON film with a dielectric constant of 23 and a 10-Aring SiO₂ interfacial layer, have been investigated for advanced CMOS applications. The HfTaON/SiO₂ gate stack provided much lower gate leakage current against SiO₂ , good interface properties, excellent transistor characteristics, and superior carrier mobility. Compared to HfON/SiO₂, improved thermal stability was also observed in the HfTaON/SiO₂ gate stack. Moreover, charge-trapping-induced threshold voltage V _th instability was examined for the HfTaON/SiO₂ and HfON/SiO₂ gate stacks. The HfTaON/SiO₂ gate stack exhibited significant suppression of the V_th instability compared to the HfON/SiO₂, in particular, for nMOSFETs. The excellent performances observed in the HfTaON/SiO₂ gate stack indicate that it has the potential to replace conventional SiO₂ or SiON as gate dielectric for advanced CMOS applications     

n+/p+ Gate Bulk FinFETs With Locally Separated Channel Structure for Sub-50-nm DRAM Cell Transistors

We proposed a new p⁺/n⁺ poly-Si gate bulk fin-type field-effect transistor that has two channel fins separated locally by a shallow trench filled with oxide or p⁺ polygate. Key device characteristics were investigated by changing the n⁺ poly-Si gate length La, the material filling the trench, and the width and length of the trench at a given gate length L_g. It was shown that the trench filled with p⁺ poly-Si gate should not be contacted with the source/drain diffusion region to achieve an excellent I_on/I_off (> 1010) that is suitable for sub-50-nm dynamic random access memory cell transistors. Based on the aforementioned device structure, we designed reasonable Ls/Lg and channel fin width W_cfin at given L_g 's of 30, 40, and 50 nm.     

Impact of CF4 Plasma Treatment on GaN

We present a systematic study of the impact of CF₄ plasma treatment on GaN. It was found that CF₄ plasma etches GaN at a slow rate and yields a smooth etched surface. The effect of CF₄ plasma on electrical characteristics of GaN metal-semiconductor field-effect-transistor structures shows that the CF₄ plasma introduces acceptors into the near surface region of the GaN, which depletes mobile electrons. It was further demonstrated that leakage current of AlGaN/GaN (or GaN) Schottky diodes can be significantly suppressed by proper CF₄ plasma treatment. These unique properties of CF₄ plasma can be utilized for the advanced processing of GaN transistors.     

Characteristics of Self-Aligned Gate-First Ge p- and n-Channel MOSFETs Using CVD HfO2 Gate Dielectric and Si Surface Passivation

The electrical properties of p- and n-MOS devices fabricated on germanium with metal-organic chemical-vapor-deposition HfO₂ as gate dielectric and silicon passivation (SP) as surface treatment are extensively investigated. Surface treatment prior to high-K deposition is critical to achieve small gate leakage currents as well as small equivalent oxide thicknesses. The SP provides improved interface quality compared to the treatment of surface nitridation, particularly for the gate stacks on p-type substrate. Both Ge p- and n-MOSFETs with HfO₂ gate dielectrics are demonstrated with SP. The measured hole mobility is 82% higher than that of the universal SiO₂/Si system at high electric field (~0.6 MV/cm), and about 61% improvement in peak electron mobility of Ge n-channel MOSFET over the CVD HfO₂ /Si system was achieved. Finally, bias temperature-instability (BTI) degradation of Ge MOSFETs is characterized in comparison with the silicon control devices. Less negative BTI degradation is observed in the Ge SP p-MOSFET than the silicon control devices due to the larger valence-band offset, while larger positive BTI degradation in the Ge SP n-MOSFET than the silicon control is characterized probably due to the low-processing temperature during the device fabrication     

MetamorphicIn0.53Ga0.47As/In0.52Al0.48As HEMTs on germanium substrates

We report for the first time the successful epitaxial growth and processing of high-performance metamorphic high electron mobility transistors (HEMTs) on Ge substrates, with a transconductance of 700 mS/mm and a saturation channel current of 650 mA/mm. To reduce parasitic capacitances due to the conductive substrate, a dry etch method based on CF₄ and O₂ reactive ion etching (RIE) is developed for selective substrate removal. Devices with 0.2 μm gate length display an increase of the extrinsic cut-off frequency f_T from 45 GHz before, to 75 GHz after substrate removal, whereas the maximum oscillation frequency f_max increases from 68 GHz to 95 GHz. Based on this excellent rf performance level, in combination with the highly selective thinning process, we think that Ge as a sacrificial substrate is a promising candidate for the integration of thinned individual HEMTs with passive circuitry on low-cost substrates. This could result in low-cost advanced hybrid systems for mass-market millimeter wave applications     

Yttrium- and Terbium-Based Interlayer on SiO2 and HfO2 Gate Dielectrics for Work Function Modulation of Nickel Fully Silicided Gate in nMOSFET

Novel yttrium- and terbium-based interlayers (Y_IL and Tb_IL, respectively) on SiO₂ and HfO₂ gate dielectrics were employed for NMOS work function Phi_m modulation of undoped nickel fully silicided (Ni-FUSI) gate. Bandedge Ni-FUSI gate Phi_m of ~4.11 and ~4.07 eV was obtained by insertion of ultrathin (~1 nm) Y_IL and Tb_IL, respectively, on the SiO₂ gate dielectric in a gate-first process (with 1000 degC anneal). NiSi Phi_m on SiO₂ could also be tuned between the Si midgap and the conduction bandedge E_C by varying the interlayer thickness. The achievement of NiSi Phi_m around 4.28 eV on the HfO₂ gate dielectric using interlayer insertion makes this an attractive Phi_m modulation technique for Ni-FUSI gates on SiO₂ and high-k dielectrics     

Influence of Hydrogen Incorporation on the Reliability of Gate Oxide Formed by Using Low-Temperature Plasma Selective Oxidation Applicable to Sub-50-nm W-Polymetal Gate Devices

This letter reveals the physical and electrical properties of silicon dioxide (Si02) formed by the plasma selective oxidation (plasma selox) using 02 and H2 gas mixture, which is applicable to sub-50-nm tungsten-polymetal gate memory devices without capping nitride film. Metal-oxide-semiconductor capacitors with gate oxide formed by the plasma selox at the process temperature in the range of 400degC-700degC showed much better time-dependent dielectric-breakdown characteristics than those formed by the conventional thermal selox at 850degC. On the other hand, in the case of very low temperature (25degC) plasma selox, the gate oxide degradation such as initial breakdown was found. It turned out to be due to the excessive hydrogen and water incorporation into the SiO₂ layer through thermal desorption spectroscopy measurements.     

MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration ofCMOS technologies

Advances in lithography and thinner SiO₂ gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta₂O₅ , have been suggested as a substitute for SiO₂ as the gate material beyond t_ox≈25 Å. However, the Si-Ta ₂O₅ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO₂(10 Å)-Ta₂O₅ (MOCVD-50 Å)-SiO₂ (LPCVD-5 Å) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents