A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

Cascaded repeaters are indispensable circuit elements in conventional on-chip clock distribution networks due to heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters cause significant jitter and skew problems in clock distribution networks when they are affected by power supply switching noise generated by digital logic blocks located on the same die. In this letter, we present a new three-dimensional (3-D) stacked-chip star-wiring interconnection scheme to make a clock distribution network free from both on-chip and package-level power supply noise coupling. The proposed clock distribution scheme provides an extremely low-jitter and low-skew clock signal by replacing the cascaded repeaters with lossless star-wiring interconnections on a 3-D stacked-chip package. We have demonstrated a 500-MHz input/output (I/O) clock delivery with 34-ps peak-to-peak jitter and a skew of 11ps, while a conventional I/O clock scheme exhibited a 146-ps peak-to-peak jitter and a 177-ps skew in the same power supply noise environment     

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking

An inductive-coupling programmable bus for NAND flash memory access in solid state drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuit-layout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 ?m CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8.     

A 100-Gb/s throughput ATM switch MCM with a 320-channel paralleloptical I/O interface

For an ATM switch system, we have developed a 100-Gb/s input/output (I/O) throughput optical I/O interface ATM switch multichip module (MCM) that has 320-ch optical I/O ports. This MCM is fabricated using ceramic (MCM-C) technology and very-small highly-parallel O/E and E/O optical converters. It uses 0.25-μm complementary metal oxide semiconductors (CMOS) ATM switch large scale integrations (LSIs) and has a total I/O throughput of up to 160 Gb/s. A prototype module with total I/O throughput of 100 Gb/s has been partially assembled using eight optical I/O interface blocks, each composed of a 40-ch O/E converter and a 40-ch E/O converter; the data rate per channel is from dc to 700 Mb/s. Using this module we developed an optical I/O interface ATM switch system and confirmed the operation of the optical interface     

Direct current to 34.1-Gb/s, 19-Gb/s/cm/sup 3/ low-jitter parallel optical interconnecting module for high-speed memory test systems

A protocol-free parallel optical interconnecting module is introduced as a solution to solve memory test system transmission bottlenecks. The optical transmission system flexibly suited for a memory test system is reviewed and discussed. A parallel optical module capable of transmitting from dc to 34.1Gb/s (4.267 Gb/s /spl times/8 ch) has been developed. A data transmission throughput density per unit volume of 19 Gb/s/cm/sup 3/ is achieved. A random jitter of less than 3-ps root-mean-square is also achieved. Furthermore, high-density optical connector, high-density optical fiber cable, fiber guides, and cable management/reinforcement members suited for mechanical requirements of the memory test system have been developed.     

40-Gb/s tandem electroabsorption modulator

In this letter, we have developed a tandem electroabsorption modulator with an integrated semiconductor optical amplifier that is capable of both nonreturn-to-zero and return-to-zero (RZ) data transmission at 40 Gb/s. The tandem modulator consists of a broad-band data encoder and a narrow-band pulse carver. The pulse carver is able to produce 5-ps pulses with more than 20 dB of extinction. The on-chip semiconductor optical amplifier provides up to 8.5 dB of fiber-to-fiber gain and enables the modulator to be operated with zero insertion loss. Devices have been realized with greater than 40-GHz bandwidth, and 13-dB dynamic extinction for a 2.5-V swing. For optimized designs bandwidths of nearly 60 GHz: have been realized. Using these devices penalty free RZ data transmission over a 100-kin dispersion compensated fiber link has been demonstrated with a received power sensitivity of -29 dBm     

64-Gb/s highly reliable network switch (RHiNET-2/SW) using paralleloptical interconnection

RHiNET-2/SW is a network switch that enables high-performance optical network based parallel computing system in a distributed environment. The switch used in such a computing system must provide high-speed, low-latency packet switching with high reliability. Our switch allows high-speed 8-Gb/s/port optical data transmission over a distance of up to 100 m, and the aggregate throughput is 64 Gb/s. In RHiNET-2/SW, eight pairs of 800-Mb/s×12-channel optical interconnection modules and a one-chip CMOS ASIC switch LSI (a 784-pin BGA package) are mounted on a single compact board. To enable high-performance parallel computing, this switch must provide high-speed, highly reliable node-to-node data transmission. To evaluate the reliability of the switch, we measured the bit error rate (BER) and skew between the data channels. The BER of the signal transmission through one I/O port was better than 10^-11 at a data rate of 800 Mb/s ×10 b with a large timing-budget margin (870 ps) and skew of less than 140 ps. This shows that RHiNET-2/SW can provide high-throughput, highly reliable optical data transmission between the nodes of a network-based parallel computing system     

A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions

A quarter-rate sampling receiver with a 2-tap decision feedback equalizer (DFE) is implemented in 90-nm CMOS technology for low-power I/O links. An analog sampling and soft-decision technique is introduced to relax the timing critical feedback path of the DFE. The shortened critical path enables better power performance. Error rates are below the measurement capability of 10^-12 with 2³¹-1 PRBS at 6 Gb/s, with an 80-mV differential launch amplitude through a channel with 6.2-dB attenuation at 3 GHz. The receiver draws 4.08 mA from a 1.0-V supply     

A process-independent, 800-MB/s, DRAM byte-wide interface featuringcommand interleaving and concurrent memory operation

An 800-MB/s/pin byte-wide interface DRAM is described that meets the bandwidth requirements for modern microprocessor systems. Clock recovery and I/O circuitry perform to specification across multiple DRAM manufacturers' processes. The clock-recovery circuitry is described in depth for areas that are sensitive to power-supply noise. I/O circuitry for preserving signal integrity in high-speed bussed systems is described. Design methodology that enables rapid simulation and verification of the design in each fabrication process is discussed. Logic that enables interleaved transactions with concurrent operation is detailed. Computer-aided-design tools for large aspect merged logic/memory are discussed. Last, measured results are summarized showing clock jitter, setup and hold timing, and period versus V_dd operation     

All-optical payload envelope detection for variable length 40-gb/s optically labeled packets

We demonstrate a new technique to all-optically identify the precise temporal locations and durations of the payloads of optical packets consisting of a variable length 40-Gb/s return-to-zero payload and 10-Gb/s nonreturn-to-zero label. The all-optically generated payload envelope signal can be used to erase the original optical label and rewrite a new label. The recovered payload envelope has 300-ps rise time and edge root-mean-square average jitter of 30 ps over a 10-dB dynamic range of input optical packet power. These numbers indicate that this technique enables the use of very short guard bands between payloads. The technique is demonstrated using optical semiconductor devices that are straightforward to monolithically integrate on a single chip.     

Evaluation of 4-Gbit/s optical fiber transmission distance with direct and external modulation

Transmission characteristics for a recently modulated measured distributed-feedbacked (DFB) laser and an externally modulated DFB laser using a Ti:LiNbO/sub 3/, Mach-Zehnder modulator at 4 Gb/s are discussed. The transmission characteristics are estimated by an advanced eye-pattern analysis method. The maximum measured fiber dispersion with a directly modulated laser is 100 to 140 ps/nm when the chirp power penalty is 1 dB. However, for external modulation, there is no power penalty after transmission over a 2220-ps/nm dispersive fiber. This confirms that external modulation has superior transmission characteristics. The modulation scheme for 4-Gb/s systems in terms of these results is discussed.<>     

Payload-envelope detection and label-detection integrated photonic circuit for asynchronous variable-length optical-packet switching with 40-gb/s RZ payloads and 10-gb/s NRZ labels

A photonic integrated circuit that performs 40-Gb/s payload-envelope detection (PED) and 10-Gb/s label detection for asynchronous variable-length optical-packet switching is demonstrated. The circuit consists of an InP photonic integrated device combined with electronic GaAs and InP devices on a carrier. Asynchronous variable-length optical packets with 40-Gb/s return-to-zero (RZ) payloads and 10-Gb/s non-RZ (NRZ) labels are processed by the circuit. The circuit outputs a PED electrical signal that represents the temporal location of the payload and a 10-Gb/s electrical signal representing the optical label. The optical label is detected error free. The PED signal has a rise/fall time of 3-ns and 150-ps jitter. The PED signal was also used to erase and rewrite the optical labels error free.     

A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link

A quad-channel 0.6-3.2 Gb/s/channnel transceiver using eight independent phase-locked loops (PLLs) shows a 1-ps rms random jitter performance without interchannel interference. The PLL employs a folded starved inverter with high supply/substrate noise immunity and an analog coarse-tuning scheme for both seamless frequency acquisition and N-fold voltage-controlled-oscillator (VCO) gain reduction. A fixed-interval charge pumping is adopted for wide pumping-current range and large jitter tolerance. A wide-range delayed-locked loop (DLL) is utilized as a clock and reset generator for an elastic buffer. The transceiver, implemented in a 0.18-/spl mu/m CMOS technology, operates across a 30-in FR-4 backplane up to 3.2 Gb/s/ch with a bit-error rate of less than 10/sup -13/.     

Optical I/O Technology for Tera-Scale Computing

This paper describes both a near term and a long term optical interconnect solution, the first based on a packaging architecture and the second based on a monolithic photonic CMOS architecture. The packaging-based optical I/O architecture implemented with 90 nm CMOS transceiver circuits, 1 × 12 VCSEL/detector arrays and polymer waveguides achieves 10 Gb/s/channel at 11 pJ/b. A simple TX pre-emphasis technique enables a potential 18 Gb/s at 9.6 pJ/b link efficiency. Analysis predicts this architecture to reach less than 1 pJ/b at the 16 nm CMOS technology node. A photonic CMOS process enables higher bandwidth and lower energy-per-bit for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides and polycrystalline germanium (Ge) detectors into a CMOS logic process. Experimental results for the photonic CMOS ring resonator modulators and Ge detectors demonstrate performance above 20 Gb/s and analysis predicts that photonic CMOS will eventually enable energy efficiency better than 0.3 pJ/b with 16 nm CMOS. Optical interconnect technologies such as these using multi-lane communication or wavelength division multiplexing have the potential to achieve TB/s interconnect and enable platforms suitable for the tera-scale computing era.     

A 10-Gb/s (1.25 Gb/s×8)4×2 0.25-μm CMOS/SIMOX ATMswitch based on scalable distributed arbitration

This paper presents the design and implementation of a scalable asynchronous transfer mode switch. We fabricated a 10-Gb/s 4×2 switch large-scale integration (LSI) that uses a new distributed contention control technique that allows the switch LSI to be expanded. The developed contention control is executed in a distributed manner at each switch LSI, and the contention control time does not depend on the number of connected switch LSI's. To increase the LSI throughput and reduce the power consumption, we used 0.25-μm CMOS/SIMOX (separation by implanted oxygen) technology, which enables us to make 221 pseudo-emitter-coupled-logic I/O pins with 1.25-Gb/s throughput. In addition, power consumption of 7 W is achieved by operating the CMOS/SIMOX gates at -2.0 V. This consumption is 36% less than that of bulk CMOS gates (11 W) at the same speed at -2.5 V. Using these switch LSI's, an 8×8 switching multichip module with 80-Gb/s throughput was fabricated with a compact size     

A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pininterface

A 2.5-V, 72-Mbit DRAM based on packet protocol has been developed using (1) a rotated hierarchical I/O architecture to reduce power noise and to minimize the chip-size penalty associated with an 8-bit prefetch architecture implemented with 16 internal banks and 144 I/O lines, (2) a delay-locked-loop circuit using a high-speed and small-swing differential clock to achieve the peak bandwidth of 2.0 GByte/s in a single chip with low noise sensitivity, and (3) a flexible column redundancy scheme to efficiently increase redundancy coverage using a shifted I/O line scheme for multibank architecture     

RF interconnect for multi-gbit/s board-level clock distribution

With clock distribution of over 1 GHz, problems associated with clock skew, power consumption, and timing jitter are becoming critical for determining the processing speed of high-performance digital systems, especially for multi-processor systems. Conventional digital clock distribution interconnection has a severe power consumption problem for GHz clock distribution because of the transmission line losses, as well as exhibiting difficult signal integrity problems due to clock skew, clerk jitter and signal reflection. To overcome conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, the optical clock distribution is found to be bulky, hard to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. In this paper, a multi-Gbit/s clock distribution scheme to minimize power consumption, skew, and jitter, based on RF interconnect technology, especially for the medium clock frequency region from 200 MHz to 10 GHz, and interconnection line lengths of from 10 cm to 3 m, is proposed. A quantitative comparison is made between the guided optical, the free-space optical, the conventional digital, and the proposed RF interconnections for board-level clock distribution relative to power consumption and speed. The proposed board-level clock distribution with 32-fan-outs has successfully demonstrated less than 22-ps skew and less than 3-ps jitter at 2 GHz. The estimated power consumption of the clock link for the proposed clock distribution has been shown to be about 320 mW. Furthermore, the proposed clock receiver using the RF clock distribution scheme has demonstrated less than 2-ps dead time and 3-ps skew time     

一个13位8兆采样率流水线模数转换器

A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier （SHA） is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers （opamps） are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW （including I/O drivers） when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm^2, including I/O pads.     

A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rateSDRAM with a 40-mW DLL for a 256-MByte memory system

A 64-Mbit bidirectional data strobed, double-data-rate SDRAM achieves a peak bandwidth of 2.56 GByte/s on a 64-bit-channel, 256-MByte memory system at V_cc=3.3 V and T=25°C. The circuit features are: (1) a bidirectional data strobing scheme to eliminate the clock-related skews of I/O data in a multimodule system, (2) a low-power delay-locked loop having a wide range of locking frequency (40-160 MHz) with fast access time and minimal variations, and (3) a twisted data bussing architecture with minimized loading difference between I/O data paths and small chip-size overhead associated with the 2-bit prefetch operation     

An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8:4 Multiplexed Data-Transfer Scheme

Three circuit techniques for an 8.1-ns column-access 1.6-Gb/s/pin 512-Mb DDR3 SDRAM using 90-nm dual-gate CMOS technology were developed. First, an 8:4 multiplexed data-transfer scheme, which operates in a quasi-4-bit prefetch mode, achieves a 3.17-ns reduction in column-access time, i.e., from 11.3 to 8.13 ns. Second, a dual-clock latency counter reduces standby power by 22% and cycle time from 1.7 to 1.2 ns. Third, a multiple-ODT-merged output buffer enables selection of five effective-resistance values Rtt (20, 30, 40, 60, and 120 Omega) without increasing I/O capacitance. Based on these techniques, 1.6-Gb/s/pin operation with a 1.36-V power supply and a column latency of 7 was accomplished     

A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18- ${rm mu}hbox{m}$ CMOS Technology

With a new 1/8-rate linear phase detector (PD), a 5-Gbit/s clock and data recovery (CDR) circuit is implemented in a digital 0.18- ${rm mu}hbox{m}$ CMOS technology. The outputs of the PD have much wider pulse than those of the conventional linear PDs. Thus, the design of circuits such as the PD and charge becomes much easier, and the maximum data rate is no longer limited by the speed of phase detection. The CDR shows 6.8-ps rms and 57.4-ps peak-to-peak jitter in the recovered clock and $10^{-12}$ bit error rate for $2^{31}-1$ pseudorandom binary-sequence input while consuming 144 mW from a 1.8-V supply.