Tradeoff between mobility and subthreshold characteristics in dual-channel heterostructure n- and p-MOSFETs

The mobility and subthreshold characteristics of TiN-gate, dual-channel heterostructure MOSFETs consisting of strained-Si-Si/sub 0.4/Ge/sub 0.6/ on relaxed Si/sub 0.7/Ge/sub 0.3/ are studied for strained-Si cap layer thicknesses ranging from 3 to 10 nm. The thinnest Si cap sample (3 nm) yields the lowest subthreshold swing (80 mV/dec) and the highest hole mobility enhancement (2.3X at a vertical effective field of 1 MV/cm). N-MOSFETs show the expected electron mobility enhancement (1.8X) for 10- and 5-nm-thick Si cap samples, which reduces to 1.6X for an Si cap thickness of 3 nm. For Si cap and gate oxide thicknesses both equal to 1 nm, simulations predict a moderate degradation in p-MOSFET subthreshold swing, from 73 to 85 mV/dec, compared to that for the Si control.     

Scalability of strained-Si nMOSFETs down to 25 nm gate length

Strained-Si nMOSFETs with a standard polysilicon gate process were fabricated down to 25 nm gate length with well-behaved characteristics and small difference in short channel effects. The performance enhancement degrades linearly as the gate length becomes shorter, due to not only the parasitic resistance but also heavy halo implant. Thus the key integration issues are how to manage threshold difference and As diffusion without excess doping. With comparable doping and well controlled parasitic resistance, up to 45% improvement in drive current is predicted for sub-50 nm gate length strained-Si nMOSFETs on the Si/sub 0.8/Ge/sub 0.2/ substrate. In this work approximately 45% enhancement is in fact demonstrated for 35 nm gate length devices, through advanced channel engineering and implementation of metal gates.     

应变硅n-MOSFET中电子迁移率的增强及其温度特性

采用减压化学气相淀积(RPCVD)技术在弛豫Si_(1-x)Ge_x虚拟衬底上赝晶生长应变硅层,以其为沟道材料制造得到的应变硅n-MOSFET表现出显著的性能提升。研究了通过改变Si_(1-x)Ge_x中Ge的摩尔组分x以改变硅帽层中的应变以及在器件制造流程中通过控制热开销来避免应变硅层发生弛豫等关键问题。在室温下,相对于体硅器件,应变硅器件表现出约87%的低场电子有效迁移率增强,在相同的过驱动电压下,饱和漏端电流增强约72%。在293 K到353 K的温度范围内研究了反型层电子有效迁移率和饱和漏端电流随温度的变化,实验结果表明,当温度升高时应变硅材料的电子迁移率增强倍数保持稳定。     

Implementation of both high-hole and electron mobility in strained Si/strained Si/sub 1-y/Ge/sub y/ on relaxed Si/sub 1-x/Ge/sub x/ (x

Jongwan Jung Lee  M.L. Shaofeng Yu Fitzgerald  E.A. Antoniadis  D.A. 《Electron Device Letters, IEEE》2003,24(7):460-462

Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs

Large differences in the experimentally observed strain-induced threshold-voltage shifts for uniaxial and biaxial tensile-stressed silicon (Si) n-channel MOSFETs are explained and quantified. Using the deformation potential theory, key quantities that affect threshold-voltage (electron affinity, bandgap, and valence band density of states) are expressed as a function of strain. The calculated threshold-voltage shift is in agreement with uniaxial wafer bending and published biaxial strained-Si on relaxed-Si/sub 1-x/Ge/sub x/ experimental data , and explains the technologically important observation of a significantly larger (>4x) threshold-voltage shift for biaxial relative to uniaxial stressed MOSFETs. The large threshold shift for biaxial stress is shown to result from the stress-induced change in the Si channel electron affinity and bandgap. The small threshold-voltage shift for uniaxial process tensile stress is shown to result from the n/sup +/ poly-Si gate in addition to the Si channel being strained and significantly less bandgap narrowing.     

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si/sub 1-x/Ge/sub x/ S/D) technology. Experimental results on Si/sub 1-x/Ge/sub x/ S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si/sub 1-x/Ge/sub x/ is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si/sub 1-x/Ge/sub x/ and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si/sub 1-x/Ge/sub x/ S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes.     

BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates

Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.     

Mobility enhancement in surface channel SiGe PMOSFETs with HfO/sub 2/ gate dielectrics

We report for the first time drive current enhancement and higher mobilities than the universal mobility for SiO/sub 2/ on Si in compressively strained Si/sub 1-x/Ge/sub x/-on-Si surface channel PMOSFETs with HfO/sub 2/ gate dielectrics, for gate lengths (L/sub G/) down to 180 nm. Thirty six percent drive current enhancement was achieved for Si/sub 0.8/Ge/sub 0.2/ channel PMOSFETs compared to Si PMOSFETs with HfO/sub 2/ gate dielectric. We demonstrate that using Si/sub 1-x/Ge/sub x/ in the channel may be one way to recover the mobility degradation due to the use of HfO/sub 2/ on Si.     

On the threshold Voltage of strained-Si-Si/sub 1-x/Ge/sub x/ MOSFETs

The threshold voltage shifts (/spl Delta/V/sub t(SS)/ relative to V/sub t/ of Si-control devices) in strained-Si-Si/sub 1-x/Ge/sub x/ (SS) CMOS devices are carefully examined in terms of the shifted two-dimensional energy subbands and the modified effective conduction- and valance-band densities of states. Increased electron affinity as well as bandgap narrowing in the SS layer are shown to be the predominant components of /spl Delta/V/sub t(SS)/, whereas the density-of-state terms tend to be relatively small but not insignificant. The study reveals, for both n-channel and p-channel SS MOSFETs, important physical insights on the varied surface potential at threshold, defined by energy quantization as well as the strain, and on the shifted flat-band voltage that is also part of /spl Delta/V/sub t(SS)/. Models for /spl Delta/V/sub t(SS)/ dependent on the Ge content (x), with comparisons to published data, are presented and used to show that redesign of channel doping in the SS nMOSFET to increase the significantly reduced V/sub tn(SS)/ for off-state current control tends to substantively diminish the inherent SS CMOS relative speed enhancement, e.g., by more than 40% for x=0.20. Interestingly, the SS pMOSFET model predicts small increases in the magnitude of V/sub tp(SS)/.     

应变Si1-xGex沟道PMOSFET空穴局域化研究

为充分利用应变 Si Ge材料相对于 Si较高的空穴迁移率 ,研究了 Si/Si Ge/Si PMOSFET中垂直结构和参数同沟道开启及空穴分布之间的依赖关系。在理论分析的基础上 ,以数值模拟为手段 ,研究了栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分及厚度、缓冲层厚度及衬底掺杂浓度对阈值电压、交越电压和空穴分布的影响与作用 ,特别强调了 δ掺杂的意义。模拟和分析表明 ,栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分、衬底掺杂浓度及 δ掺杂剂量是决定空穴分布的主要因素 ,而 Si Ge层厚度、缓冲层厚度和隔离层厚度对空穴分布并不敏感。最后总结了沟道反型及空穴分布随垂直结构及参数变化的一般规律 ,为优化器件设计提供了参考。     

Scaling and strain dependence of nanoscale strained-Si p-MOSFET performance

Self-consistent fullband Monte Carlo simulations based on nonlocal empirical pseudopotential band structures including spin-orbit splitting are employed to estimate the on-current in nanoscale strained-Si p-MOSFETs. Effective gate lengths from L/sub eff/ = 75 nm down to L/sub eff/ = 25 nm and strain levels corresponding to germanium contents of up to x = 0.4 in the relaxed Si/sub 1-x/Ge/sub x/ substrate are considered. It is found that the on-current continuously increases for growing substrate germanium contents. The strain-induced performance enhancement moderately decreases with scaling, but the improvement at L/sub eff/ = 25 nm still attains 20% for x = 0.4. In contrast to strained-Si n-MOSFETs, increasing the substrate germanium content beyond x = 0.2 is essential for p-MOSFET performance improvement by strain in the sub 0.1 /spl mu/m regime. However, even for x = 0.4 the on-current in a strained-Si p-MOSFET is still smaller than in a corresponding unstrained-Si n-MOSFET.     

Study of nickel silicide contact on Si/Si/sub 1-x/Ge/sub x/

The properties of nickel silicide formed by depositing nickel on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer are compared with that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer formed by depositing Ni directly on p/sup +/-Si/sub 1-x/Ge/sub x/ layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer. In addition, small junction leakage current is also observed for nickel silicide on a Si/p/sup +/-Si/sub 1-x/Ge/sub x//n-Si diode. In summary, with a Si consuming layer on top of the Si/sub 1-x/Ge/sub x/, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on the Si/sub 1-x/Ge/sub x/ layer.     

Effect of substrate biasing on Si/SiGe heterostructure MOSFETs for low-power circuit applications

We have investigated the effect of substrate biasing on the subthreshold characteristics and noise levels of Si/Si/sub 1-x/Ge/sub x/ (x=0,0.15,0.3) heterostructure MOSFETs. A detailed analysis of the dependence of threshold voltage, off-state current, and low-frequency noise level on the substrate-source (V/sub bs/) biasing showed that SiGe heterostructure MOSFETs offer a significant speed advantage, an extended subthreshold operation region, a reduced noise level, and reduced bulk potential sensitivity compared to Si bulk devices. These experimental results demonstrate that SiGe heterostructure MOSFETs render a promising extension to the CMOS technologies at the low-power limit of operation, eventually making the micropower implementation of radio frequency (RF) functions feasible.     

Hole transport in UTB MOSFETs in strained-Si directly on insulator with strained-Si thickness less than 5 nm

Hole transport is studied in ultrathin body (UTB) MOSFETs in strained-Si directly on insulator (SSDOI) with a Si thickness down to 1.4 nm. In these Ge-free SSDOI substrates, the Si is strained in biaxial tension with strain levels equivalent to strained-Si on relaxed SiGe, with Ge contents of 30 and 40% Ge. The hole mobility in SSDOI decreases slowly for Si thicknesses above 4 nm, but drops rapidly below that thickness. Relative to silicon-on-insulator control devices of equal thickness, SSDOI displays significant hole mobility enhancement for Si film thicknesses above 3.5 nm. Peak hole mobility is improved by 25% for 40% SSDOI relative to 30% SSDOI fabricated by the same method, demonstrating the benefits of strain engineering for 3.1-nm-thick UTB MOSFETs.     

Application of silicon-germanium in the fabrication of ultra-shallow extension junctions for sub-100 nm PMOSFETs

This work summarizes the results of several experiments to investigate the potential applications of Silicon-Germanium alloy in the fabrication of shallow source/drain (S/D) extension Junctions for deep submicron PMOS transistors. Two approaches were used for the fabrication of p/sup +/-Si/sub 1-x/Ge/sub x//n-Si heterojunctions. In the first approach, high dose Ge ion implantation followed by boron implantation into Si was used to form very shallow p/sup +/-Si/sub 1-x/Ge/sub x//n-Si junctions (x/spl les/0.2). In the second approach, thin Ge films were deposited onto Si substrates by conventional low pressure chemical vapor deposition. This was followed by boron implantation into the Ge and thermal annealing to co-diffuse Ge and B atoms into Si and form p/sup +//n heterojunctions. The electrical characteristics of the heterojunction diodes were comparable to those of conventional Si (homo) junctions. Secondary ion mass spectrometry (SIMS) concentration-depth profiles indicate that dopant segregation in the Si/sub 1-x/Ge/sub x/ regions resulted in the formation of ultra-shallow and abrupt junctions that could be used as S/D extensions for sub-100 nm CMOS generations. PMOS transistors fabricated using these techniques exhibit superior short-channel performance compared to control devices, for physical gate lengths down to 60 nm.     

A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.     

采用SiGe虚拟衬底高迁移率应变硅材料的制备和表征

研究了生长在弛豫Si0.79Ge0.21/梯度Si1-xGex/Si虚拟衬底上的应变硅材料的制备和表征,这一结构是由减压外延气相沉积系统制作的.根据双晶X射线衍射计算出固定组分SiGe层的Ge浓度和梯度组分SiGe层的梯度,并由二次离子质谱仪测量验证.由原子力显微术和喇曼光谱测试结果得到应变硅帽层的表面粗糙度均方根和应变度分别为2.36nm和0.83%;穿透位错密度约为4×104cm-2.此外,发现即使经受了高热开销过程,应变硅层的应变仍保持不变.分别在应变硅和无应变的体硅沟道上制作了nMOSFET器件,并对它们进行了测量.相对于同一流程的体硅MOSFET,室温下观测到应变硅器件中电子的低场迁移率显著增强,约为85%.     

Threshold voltage reduction model for buried channel PMOSFETs using quasi-2-D Poisson equation

A quasi-two-dimensional (2-D) threshold voltage reduction model for buried channel pMOSFETs is derived. In order to account for the coexistence of isoand anisotype junctions in a buried channel structure, we have incorporated charge sharing effect in the quasi-2-D Poisson model. The proposed model correctly predicts the effects of drain bias (V/sub DS/), counter doping layer thickness (x/sub CD/), counter doping concentration (N/sub CD/), substrate doping concentration (N/sub sub/) and source/drain junction depth (x/sub j/), and the new model performs satisfactorily in the sub-0.1 /spl mu/m regime. By using the proposed model on the threshold voltage reduction and subthreshold swing, we have obtained the process windows of the counter doping thickness and the substrate concentration. These process windows are very useful for predicting the scaling limit of the buried channel pMOSFET with known process conditions or systematic design of the buried channel pMOSFET.     

A logic nanotechnology featuring strained-silicon

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.     

High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.