High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.     

Modeling study of the impact of surface roughness on silicon and Germanium UTB MOSFETs

We outlined a simple model to account for the surface roughness (SR)-induced enhanced threshold voltage (V/sub TH/) shifts that were recently observed in ultrathin-body MOSFETs fabricated on <100> Si surface. The phenomena of enhanced V/sub TH/ shifts can be modeled by accounting for the fluctuation of quantization energy in the ultrathin body (UTB) MOSFETs due to SR up to a second-order approximation. Our model is then used to examine the enhanced V/sub TH/ shift phenomena in other novel surface orientations for Si and Ge and its impact on gate workfunction design. We also performed a calculation of the SR-limited hole mobility (/spl mu//sub H,SR/) of p-MOSFETs with an ultrathin Si and Ge active layer thickness, T/sub Body/<10 nm. Calculation of the electronic band structures is done within the effective mass framework via the Luttinger Kohn Hamiltonian, and the mobility is calculated using an isotropic approximation for the relaxation time calculation, while retaining the full anisotropy of the valence subband structure. For both Si and Ge, the dependence of /spl mu//sub H,SR/ on the surface orientation, channel orientation, and T/sub Body/ are explored. It was found that a <110> surface yields the highest /spl mu//sub H,SR/. The increasing quantization mass m/sub z/ for <110> surface renders its /spl mu//sub H,SR/ less susceptible with the decrease of T/sub Body/. In contrast, <100> surface exhibits smallest /spl mu//sub H,SR/ due to its smallest m/sub z/. The SR parameters, i.e. autocorrelation length (L) and root-mean-square (/spl Delta//sub rms/) used in this paper is obtained from the available experimental result of Si<100> UTB MOSFETs, by adjusting these SR parameters to obtain a theoretical fit with experimental data on SR-limited mobility and V/sub TH/ shifts. This set of SR parameters is then employed for all orientations of both Si and Ge devices.     

On the modeling of surface roughness limited mobility in SOI MOSFETs and its correlation to the transistor effective field

In this paper, we discuss in detail the modeling of surface roughness (SR) scattering in single- and double-gate silicon-on-insulator (SOI) MOSFETs, where the conventional formulation based on the expected value of the electric field cannot be used. By reconsidering the Ando's original approach, we show that a model based on the eigenfunction derivatives at the Si-oxide interface can be naturally extended to SOI MOSFETs, and, furthermore, we also derive a formulation based on appropriate integrals of the eigenfunctions in the silicon film, which must replace the expected value of the field used in bulk MOSFETs. All the analytical identities used in the derivation of the model have been verified by using numerically calculated eigenvalues and wavefunctions. Our results indicate that, in ultrathin-film SOI MOSFETs, the effective field is no longer a good metric for the SR scattering and, furthermore, SR scattering affects the total mobility even at lower inversion densities than it does in bulk transistors.     

Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters

Electron and hole mobility in HfO/sub 2//metal gate MOSFETs is deeply studied through low-temperature measurements down to 4.2 K. Original technological splits allow the decorrelation of the different scattering mechanisms. It is found that even when charge trapping is negligible, strong remote coulomb scattering (RCS) due to fixed charges or dipoles causes most of the mobility degradation. The effective charges are found to be located in the HfO/sub 2/ near the SiO/sub 2/ interface within 2 nm. Experimental results are well reproduced by RCS calculation using 7/spl times/10/sup 13/ cm/sup -2/ fixed charges at the HfO/sub 2//SiO/sub 2/ interface. We also discuss the role of remote phonon scattering in such gate stacks. Interactions with surface soft-optical phonon of HfO/sub 2/ are clearly evidenced for a metal gate but remain of second order. All these remote interactions are significant for an interfacial oxide thickness up to 2 nm, over which, these are negligible. Finally, the metal gate (TiN) itself induces a modified surface-roughness term that impacts the low to high effective field mobility even for the SiO/sub 2/ gate dielectric references.     

Electron mobility in an AlGaN/GaN two-dimensional electron gas. I. Carrier concentration dependent mobility

The transport properties of two-dimensional electron gas (2-DEG) at the AlGaN/GaN interface were studied by characterizing the 2-DEG mobility dependence on carrier concentration, n/sub s/, and temperature. High-quality AlGaN/GaN heterostructures were grown, and heterostructure field effect transistors (HFETs) using a Fat FET geometry were fabricated. Measurements of 2-DEG mobility were performed by magnetoresistance and capacitance-conductance. In order to understand the dominant transport factors, the mobility was modeled using different scattering mechanisms and compared to our results. It is found that mobility dependence on n/sub s/ shows a bell-shape behavior over the whole temperature range. For low n/sub s/ the mobility is dominated by Coulomb interaction from interface charge, and at high n/sub s/ the mobility is dominated by interface roughness. Using previously reported experimental values of interface charge and interface roughness in our modeling, we show good agreement with mobility measurement results. Scattering from interface states in AlGaN/GaN heterostructures, seems to be related to the high polarization field in the heterointerface. At temperatures higher than 200K polar optical phonon scattering dominates the transport, yet both interface charge and roughness affect the mobility at the low and high n/sub s/, respectively.     

Impact of a Nonideal Metal Gate on Surface Optical Phonon-Limited Mobility in High- κ Gated MOSFETs

The effects of surface phonon scattering in an nMOSFET with a high-k gate insulator and a nonideal metal gate are examined. The nonideal metal gate model depends on three parameters: (1) the density of electrons in the gate; (2) the electron effective mass; and (3) the high-frequency dielectric constant associated with the choice of gate metal. The impact of these parameters on surface optical (SO) mobility is demonstrated using TiN as an example. For the selected choice of parameters and Landau damping limits, the results indicate that SO phonon scattering does not seem to play a significant role in the mobility degradation of TiN/HfO₂ MOSFETs for the entire range of sheet concentration.     

Improving strained-Si on Si1-xGex deepsubmicron MOSFETs performance by means of a stepped doping profile

We have made use of a stepped doping profile to improve the performance of strained-Si ultra-short MOSFETs. Electron mobility curves are calculated by a Monte Carlo simulator including electron quantization and Coulomb scattering, in addition to phonon and surface roughness scattering. In the first part of the paper, the effect of Coulomb scattering due to both interface charges and bulk impurities is carefully analyzed. We show that the strain enhances the Coulomb-limited mobility due to the interface-trapped charges as a consequence of a better screening of these charges by mobile carriers. However, we also show that this improvement in the Coulomb-limited mobility does not occur if the Coulomb scattering is due to bulk doping impurities, since they share the same physical spare with the carriers, and therefore the screening is the same for the same inversion charge concentration. Nevertheless, we have shown that the use of a stepped doping profile bypasses this inconvenience. The introduction of a low doped layer below the oxide reduces the scattering produced by the bulk ionized impurities, enhancing Coulomb-limited mobility in deep-submicron devices. On the other hand, we have seen (by using MINIMOS-NT) that the use of the low doped silicon layer significantly improves the drain current while degrade the turn-off behavior of very short-channel devices only moderately. This design provides the possibility of taking full advantage of the great reduction in phonon scattering produced by the strain in the Si layer in these MOSFETs     

Influence of high channel doping on the inversion layer electron mobility in strained silicon n-MOSFETs

In this letter, we investigate the dependence of electron inversion layer mobility on high-channel doping required for sub-50-nm MOSFETs in strained silicon (Si), and we compare it to co-processed unstrained Si. For high vertical effective electric field E/sub eff/, the electron mobility in strained Si displays universal behavior and shows enhancement of 1.5-1.7/spl times/ compared to unstrained Si. For low E/sub eff/, the mobility for strained Si devices decreases toward the unstrained Si data due to Coulomb scattering by channel dopants.     

The influence of HfO2 film thickness on the interface state density and low field mobility of n channel HfO2/TiN gate MOSFETs

The influence of HfO₂ thickness (1.6 to 3nm) on interface state density and low field mobility in HfO₂/TiN gate n channel MOSFETs have been studied by analyzing experimental data from charge pumping, split CV, DC I_d-V_g, pulsed I_d-V_g and Y-function methods. It is found that there is no HfO₂ thickness dependence on the interface state density, whereas there is continuous electron mobility degradation with HfO₂ thickness. The devices exhibited no detectable fast transient charge trapping, allowing the relative contributions of phonon and Coulomb scattering to be examined over temperature. The dependence of the low field mobility on temperature from 50 K to 400 K indicates HfO₂ remote phonon scattering as the dominant cause of the mobility degradation.     

Temperature dependence of channel mobility in HfO/sub 2/-gated NMOSFETs

The degradation mechanisms of effective electron channel mobility in HfO/sub 2/-gated nMOSFETs have been studied by analyzing experimental data at various temperatures from 120 to 320 K. The major finding is that, while significant Coulomb scattering plays an important role in causing the observed mobility degradation, it does not account for all of the degradation; rather, it requires an extra phonon scattering mechanism, beyond that arising from the phonons in the Si substrate, to explain our experimental results. This extra phonon scattering mechanism has been found to exhibit relatively weak temperature dependence, and is attributed to the soft optical phonons in the HfO/sub 2/ layer.     

Ballistic transport in high electron mobility transistors

A general ballistic FET model that was previously used for ballistic MOSFETs is applied to ballistic high electron mobility transistors (HEMTs), and the results are compared with experimental data for a sub-50 nm InAlAs-InGaAs HEMT. The results show that nanoscale HEMTs can be modeled as an intrinsic ballistic transistor with extrinsic source/drain series resistances. We also examine the "ballistic mobility" concept, a technique proposed for extending the drift-diffusion model to the quasi-ballistic regime. Comparison with a rigorous ballistic model shows that under low drain bias the ballistic mobility concept, although nonphysical, can be used to understand the experimental phenomena related to quasi-ballistic transport, such as the degradation of the apparent carrier mobility in short channel devices. We also point out that the ballistic mobility concept loses validity under high drain bias. The conclusions of this paper should be also applicable to other nanoscale transistors with high carrier mobility, such as carbon nanotube FETs and strained silicon MOSFETs.     

High-/spl kappa//metal-gate stack and its MOSFET characteristics

We show experimental evidence of surface phonon scattering in the high-/spl kappa/ dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN metal-gate electrode is effective in screening phonon scattering in the high-/spl kappa/ dielectric from coupling to the channel under inversion conditions, resulting in improved channel electron mobility. We then show that other metal-gate electrodes, such as the ones with n+ and p+ work functions, are also effective in improving channel mobilities to close to those of the conventional SiO/sub 2//poly-Si stack. Finally, we demonstrate this mobility degradation recovery translates directly into high drive performance on high-/spl kappa//metal-gate CMOS transistors with desirable threshold voltages.     

A field-effect electron mobility model for SiC MOSFETs including high density of traps at the interface

Besides its favorable physical properties, high performant MOSFETs (metal-oxide-semiconductor field-effect transistors) fabrication in silicon carbide (SiC) remains an open issue due to their low channel mobility values. The effect of charge trapping and the scattering at interface states have been invoked as the main reasons for mobility reduction in SiC thermal oxidized MOS gated devices. In this paper, we propose a compact electron mobility model based on the well-established Lombardi mobility model to reproduce the mobility degradation commonly observed in these SiC devices. Using 2D electrical simulations along with the proposed model and taking into account interface traps Coulomb scattering, the experimental field-effect mobility of 4H-SiC MOSFET devices has been fitted with a good agreement.     

Bias-temperature instabilities of polysilicon gate HfO/sub 2/ MOSFETs

Bias-temperature instabilities (BTI) of HfO/sub 2/ metal oxide semiconductor field effect transistors (MOSFETs) have been systematically studied for the first time. NMOS positive BTI (PBTI) exhibited a more significant V/sub t/ instability than that of PMOS negative BTI (NBTI), and limited the lifetime of HfO/sub 2/ MOSFETs. Although high-temperature forming gas annealing (HT-FGA) improved the interface quality by passivating the interfacial states with hydrogen, BTI behaviors were not strongly affected by the technique. Charge pumping measurements were extensively used to investigate the nature of the BTI degradation, and it was found that V/sub t/ degradation of NMOS PBTI was primarily caused by charge trapping in bulk HfO/sub 2/ rather than interfacial degradation. Deuterium (D/sub 2/) annealing was found to be an excellent technique to improve BTI immunity as well as to enhance the mobility of HfO/sub 2/ MOSFETs.     

Numerical analysis of the self-heating effect in SGOI with a double step buried oxide

To reduce the self-heating effect of strained Si grown on relaxed SiGe-on-insulator(SGOI) n-type metal-oxide-semiconductor field-effect transistors(nMOSFETs),this paper proposes a novel device called double step buried oxide(BOX) SGOI,investigates its electrical and thermal characteristics,and analyzes the effect of self-heating on its electrical parameters.During the simulation of the device,a low field mobility model for strained Si MOSFETs is established and reduced thermal conductivity resulting from phonon boundary scattering is considered.A comparative study of SGOI nMOSFETs with different BOX thicknesses under channel and different channel strains has been performed.By reducing moderately the BOX thickness under the channel,the channel temperature caused by the self-heating effect can be effectively reduced.Moreover,mobility degradation,off state current and a short-channel effect such as drain induced barrier lowering can be well suppressed.Therefore,SGOI MOSFETs with a thinner BOX under the channel can improve the overall performance and long-term reliability efficiently.     

Physics-Based Modeling of Hole Inversion-Layer Mobility in Strained-SiGe-on-Insulator

The hole inversion-layer mobility of strained-SiGe homo- and heterostructure-on-insulator in ultrathin-body MOSFETs is modeled by a microscopic approach. The subband structure of the quasi-2-D hole gas is calculated by solving the 6times6koarrldrpoarr Schrodinger equation self-consistently with the electrostatic potential. The model includes four important scattering mechanisms: optical phonon scattering, acoustic phonon scattering, alloy scattering, and surface-roughness scattering. The model parameters are calibrated by matching the measured low-field mobility of two particularly selected long-channel pMOSFET cases. The calibrated model reproduces available channel-mobility measurements for many different strained-SiGe-on-insulator structures. For the silicon-on-insulator MOS structures with unstrained-Si channels, the silicon-thickness dependence resulting from our model for the low-field channel mobility agrees with previous publications.     

Fabrication and mobility characteristics of SiGe surface channel pMOSFETs with a HfO/sub 2//TiN gate stack

This paper describes an extensive experimental study of TiN/HfO/sub 2//SiGe and TiN/HfO/sub 2//Si cap/SiGe gate stacked-transistors. Through a careful analysis of the interface quality (interface states and roughness), we demonstrate that an ultrathin silicon cap is mandatory to obtain high hole mobility enhancement. Based on quantum mechanical simulations and capacitance-voltage characterization, we show that this silicon cap is not contributing any silicon parasitic channel conduction and degrades by only 1 /spl Aring/ the electrical oxide thickness in inversion. Due to this interface optimization, Si/sub 0.72/Ge/sub 0.28/ pMOSFETs exhibit a 58% higher mobility at high effective field (1 MV/cm) than the universal SiO/sub 2//Si reference and a 90% higher mobility than the HfO/sub 2//Si reference. This represents one of the best hole mobility results at 1 MV/cm ever reported with a high-/spl kappa//metal gate stack. We thus validate a possible solution to drastically improve the hole mobility in Si MOSFETs with high-/spl kappa/ gate dielectrics.     

A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.     

Modeling and Data for Thermal Conductivity of Ultrathin Single-Crystal SOI Layers at High Temperature

Simulations of the temperature field in silicon-on-insulator (SOI) and strained-Si transistors can benefit from experimental data and modeling of the thin silicon layer thermal conductivity at high temperatures. This paper develops algebraic expressions to account for the reduction in thermal conductivity due to the phonon–boundary scattering for pure and doped silicon layers and presents the experimental data for 50-nm-thick single-crystal silicon layers at high temperatures. The model applies to the temperature range of 300–1000 K for silicon layer thicknesses from 10 nm to 1$muhboxm$(and even bulk), which agrees well with the experimental data. In addition, the algebraic model has an excellent agreement with both the experimental data and predictions of thin-film thermal conductivity based on thermal conductivity integral and Boltzmann transport equation. The analytical thermal modeling and ISE-TCAD electrothermal simulations confirm that both the electrical and thermal performances of SOI transistor can be largely affected if the reduced thermal conductivity of the silicon due to phonon boundary scattering is not properly taken into consideration.     

Relationship between empirical and theoretical mobility models insilicon inversion layers

The theoretical and empirical expressions most commonly used for modeling the variation of the low field surface mobility of MOSFETs are discussed. It is shown that both approaches may be reconciled, and a new physical definition of the parameters of the empirical model is presented, In particular, we propose an analytical formula of the factor &thetas;₂ characterizing the quadratic dependence of the reciprocal mobility on the inversion charge. Both the formula and experiment agree and show that &thetas;₂ does not only depend on the surface roughness scattering term, but also on phonon scattering