A Highly Reliable Memory Subsystem Design Employing SECDED, Column Sparing, and Paging

This paper develops a reliability model for a paged memory system wherein the pages of memory are physically distributed among several arrays of memory chips. Any of the available pages can be used to satisfy the required memory capacity. This paper also develops a reliability model for a page or block of memory words imbedded in an array. The model assumes that memory chips have failure modes that are catastrophic to a row, to a column, to the whole physical array, or to individual bits. Spare columns or data lines are used to enhance reliability. SECDED (Single Error Correction, Double Error Detection) provides the hard-fault detection mechanism and complete fault coverage for soft faults such as 1-bit upsets. A highly reliable memory system design is described that implements a paging scheme, uses a SECDED code for hard fault detection and isolation, and uses three levels of sparing to recover from failures. The significance of this paper is that it considers failure modes associated with interfacing a memory chip into an array of memory chips. These failure modes have an impact beyond the boundaries of an individual chip; they affect the entire physical array and must be considered in the reliability model. When this is done the reliability model permits trading off page size and array size with reliability.     

The future is in the PC cards

The growing use of IC memory cards, with their small size and low power consumption, in key roles in all sorts of handheld equipment is discussed. Three events that have propelled the credit-card-sized descendants of the original battery-packed memory cards are discussed. They are the development of a standard for 68-pin personal computer cards, known as PC cards, that allows them to act as peripherals, such as modems and network ports, as well as storage devices; the development of flash-type nonvolatile memory chips of very high capacity; and the emergence of palmtop and notebook computers     

A Software Technique for Diagnosing and Correcting Memory Errors

A software diagnostic that eliminates 2-bit and some 3-bit errors is described. The diagnostic procedure tests memory for errors that cannot be corrected by ECC (error correcting code): single error correct, double error detect. When an uncorrectable error is found, the diagnostic attempts to reduce it to a I-bit error. This is done either by reconfiguring the memory to distribute failing bits across different ECC words or by replacing the failing chip with a spare. The result is that memory cards that previously had to be replaced can now continue to function. Thus, the life of memory cards can be prolonged. The diagnostic can also perform preventive maintenance when run in an alternate mode. In this mode, all combinations of the memory are tested to determine if there is reserve. Reserve is defined as: 1) The capability of reconfiguring the card to obtain another functional state of memory (in addition to the current operational state), or 2) The availability of functional spare chips that have not been used. Preventive maintenance is by replacing cards that have no reserve. Then, memory operation can continue error free.     

A computer-based-design approach to partitioning and mapping of computer logic graphs

A system of design automation computer programs is described which is capable of assigning blocks of a logic design to modules so as to satisfy certain constraints specified on the assignment. System features which enable designer-computer cooperation are discussed, and quality of solutions obtained with the system are compared to manual solutions for the same tasks. Three conclusions are reached. First, these computer programs make it possible to perform partitioning and mapping experiments which were not possible before. Second, for one-level partitions (e.g., logic gates on chips), highly automatic solutions obtained by the system are at least as good as manual solutions and are less costly to obtain. Third, for multilevel partitions (e.g., logic gates on chips on cards) or for mappings, the solutions obtained with the program are again at least as good as manual solutions; furthermore, the system allows a designer to try more alternatives than he could manually, so that he can trade off the time and cost of trying additional alternatives against the value of a better solution.     

Memory on the move

The author describes how, competing for the US $ 11 billion portable electronic device memory market are several venerable but revitalized memory systems as well as new storage technologies: flash memory cards; PC memory cards; and small disk drives. Flashers, a relatively young technology contain one or more nonvolatile solid-state memory chips. They have no moving parts and retain data in the absence of power. Like these, but an industry unto itself, is the PC Card; now almost 10 years old, the business-card-sized memory and application device is heavily used to add functions to mobile computers. The spinners are a completely upgraded group of rotating disk drive systems based on both magnetic and optical technologies     

SoC的存储器Wrapper设计及故障测试

在系统芯片SoC测试中,存储器的可靠性测试是一项非常重要内容.IEEE Std 1500是专门针对嵌入式芯核测试所制定的国际标准,规范了IP核提供者和使用者之间的标准接口.基于此标准完成针对SoC存储器的Wrapper测试壳结构和控制器的设计.以32×8的SRAM为测试对象进行测试验证.结果表明,系统能够准确的诊断出存储器存在故障.     

System of nano-silver inkjet printed memory cards and PC card reader and programmer

This work describes the development of inkjet printed, low-cost memory cards, and complementary pair of memory card reader and card reader/programmer for PCs. This constitutes a complete system that can be used for various applications. The memory cards are manufactured by inkjet printing nano-silver ink on photo paper substrate. The printed memory structures have an initial high resistance that can later be programmed to specific values representing data on the cards, the so called Write Once Read Many (WORM) memories. The memory card reader measures the resistance values of the memory cells and reads it back to the computer by USB connection. Using multiple resistance levels that represent different states it is possible to have a larger number of selectable combinations with fewer physical bits compared to binary coding. This somewhat counters one of the limitations of resistive memory technology that basically each cell needs one physical contact. The number of possible states is related to the resolution of the reader and the stability of the WORM memory.     

Obtaining FPGA soft error rate in high performance information systems

Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. The vulnerability of FPGA-based designs to soft errors is higher than ASIC implementations since the majority of chip real estate is dedicated to memory bits, configuration bits, and user bits. Moreover, Single Event Upsets (SEUs) in the configuration bits of SRAM-based FPGAs result in permanent errors in the mapped design.FPGAs are widely used in the implementation of high performance information systems. Since the reliability requirements of these high performance information sub-systems are very stringent, the reliability of the FPGA chips used in the design of such systems plays a critical role in the overall system reliability. In this paper, we compare and validate the soft error rate of FPGA-based designs used in the Logical Unit Module board of a commercial information system with the field error rates obtained from actual field failure data. This comparison confirms that our analytical tool is very accurate (there is an 81% overlap in FIT rate range obtained with our analytical modeling framework and the field failure data studied). It can be used for identifying vulnerable modules within the FPGA for cost-effective reliability improvement.     

New 3-D Chip Stacking Architectures by Wire-On-Bump and Bump-On-Flex

Two new 3-D chip stacking technologies, wire-on-bump (WOB) and bump-on-flex (BOF), are proposed and demonstrated with their prototypes. The WOB and BOF technologies are for low cost 3-D stacking of memory chips by vertical side interconnections with metal wires and flex-circuits, respectively. These new 3-D chip stacking technologies have benefits such as a shorter signal path and 3-D stackability of an unlimited number of chips compared to wire-bonded chip stacking. In the case of the BOF technology, additional active and passive components can be either surface-mounted onto or embedded into the flex-circuit, which is an added value that other chip stacking technologies have not demonstrated so far. More importantly, the WOB and BOF technologies enable lower cost processes than Si through-via technology, which is thus more suitable for memory chip stacking. This paper describes the detailed processes for our unique chip stacking structures with vertical interconnection methods of the WOB and BOF. Finite-element modeling and thermal cycle (TC) tests are also performed to address their thermo-mechanical reliability.     

Design and analysis of a self-testing-and-repairing random access memory “STAR–RAM” with error correction

This paper presents the philosophy and design of a fault-tolerant dynamically-reconfigurable random access memory (RAM) system with a built-in Self-Testing-And-Repairing “STAR” engine. The STAR engine, supported by SEC–DED capability, provides on-line fault detection, correction, analysis and repair without destroying useful data stored in the memory. Reliability analysis of the presented system has been accomplished using a SMART simulation approach[1], and results show significant reliability enhancement over SEC–DED RAM designs. The memory system employs a hardware parallel address-comparison mechanism for rapid processing of incoming addresses during normal read/write operations to minimize memory access delay. The flexible STAR architecture and the low hardware overhead enables utilization of the proposed approach in VLSI memory chips as well as in WSI and large memory modules.     

基于PXA255 XScale的外部存储器接口设计

在利用ARM微处理器进行实际应用开发时,存储器接口设计是整个应用系统设计的关键。不同的ARM微处理器具有不同的存储器接口,所支持的存储器芯片型号和种类也不尽相同,但在设计方法上却大同小异。文中首先对PXA255微处理器所支持的三类存储器接口设计进行了分析,并以接口设计实例阐明PXA255在进行存储器接口设计时的方法,最后给出了PXA255在实际应用系统中存储器接口设计原理图。     

Current reliability issues and future technologies for systems on silicon – processes, circuits, chip architecture, and design

The progress of silicon technology is opening the era of “systems on silicon” in which a large-scale memory, a CPU, and other logic macros will be integrated on a single chip. These kinds of chips, called system LSIs, have an especially promising future in mobile and multimedia applications but face inherent technical problems related to the reliability of ultrathin oxide film, conflict in the processing of different components, increased gate and subthreshold leakage currents, memory bottlenecks, and design complexity. This paper reviews the system LSIs and then introduces related technologies in processing, circuits, chip architecture, and design. It also discusses the influence of the system LSIs on business strategies.     

源端射频干扰下SRAM的抗扰性分析

目前已有一些在ESD和电磁干扰下存储器行为的表征研究,但对静态随机存取存储器(SRAM)的连续波抗扰度的频率响应特性的研究很少.文章研究了 SRAM在射频电磁干扰下的失效行为与机理.对SRAM芯片进行射频干扰测试发现,SRAM失效行为与其工作模式相关.使用Hspice进行晶体管级仿真.结果表明,SRAM处于数据保持时,...     

Comparison of Memory Chip Organizations vs Reliability in Virtual Memories

Random access memory organizations typically are chosen for maximum reliability, based on the operation of the memory box itself without concern for the remainder of the computing system. This had led to widespread use of the 1-bit-per-chip, or related organization which uses error correcting codes to minimize the effects of failures occurring in some basic unit such as a word or double word (32 to 64 bits). Such memory boxes are used quite commonly in paged virtual memory systems where the unit for protection is really a page (4K bytes), or in a cache where the unit for protection is a block (32 to 128 bytes), not a double word. With typical high density memory chips and typical ranges of failure rates, the 1-bit-per-chip organization can often maximize page failures in a virtual memory system. For typical cases, a paged virtual memory using a page-per-chip organization can substantially improve reliability, and is potentially far superior to other organizations. This paper first describes the fundamental considerations of organization for memory systems and demonstrates the underlying problems with a simplified case. Then the reliability in terms of lost pages per megabyte due to hard failures over any time period is analyzed for a paged virtual memory organized in both ways. Normalized curves give the lost pages per Mbyte as a function of failure rate and accumulated time. Assuming reasonable failure rates can be achieved, the page-per-chip organization can be 10 to 20 times more reliable than a 1-bit-per-chip scheme.     

A comprehensive CAD system for high-performance 300 K-circuit ASIClogic chips

A computer-aided design (CAD) system has been developed to support design of CMOS application-specific integrated circuit (ASIC) logic chips containing more than 300 K equivalent two-input NANDs with 180-ps typical gate delays. The underlying technology is a 0.8-μm, four-level-metal, single-poly CMOS process, with a 0.45-μm nominal effective channel length and 180-ps typical gate delay. Both standard-cell and gate-array circuit libraries are provided, including fixed and growable memory macros. Key new system features are described in the areas of high-level design and synthesis, delay calculation and timing analysis, timing guidance to physical design, physical design, clock construction, and test generation. Early processing results are reported for several test chips, including a 9.7-mm 2-million-transistor chip and a 14.5-mm 300 K-equivalent-gate chip     

一种并行指令Cache的设计与实现

为提高通用微处理器的执行效率,研究了高性能指令Cache的体系结构和设计方法。设计了高速并行指令Cache的系统架构,将Cache体访问与线形地址到物理地址的地址转换并行操作,成功实现一个时钟周期内完成地址转换和指令读出的设计目标。详细设计了Cache体和TLB的逻辑结构,并对相关设计参数进行了精心规划,并在设计中采用了奇偶校验逻辑增加了芯片的可靠性。此结构应用于JX微处理器流片成功,并工作可靠正确。     

Recursive Algorithm for Reliability Evaluation of k-out-of-n:G System

An algorithm for computing recursively the exact system reliability of k-out-of-n systems is proposed. It is simple, easy to implement, fast, and memory efficient. It gives a reliability expression with minimal number of terms, C(k, n) and involves only a few multiplications. The reduction in number of terms and multiplications is over 50 percent compared to some methods. The recursive nature of the algorithm enables one to design easily the number of units in the system to meet a reliability target. An alternative representation of the algorithm which is easy to remember and good for manual computation is given. However, it involves a few more multiplications compared to the original one but fewer than those required with existing methods.     

Modeling testing-strategies for yield enhancement of multichipmodule systems

This paper presents analytic models for evaluating test-strategy (TS) for yield enhancement of systems manufactured using fault-tolerant (FTol) multichip modules (MCM) for massively parallel computing. Several methods for testing FTol-MCM have been proposed, but there is little analytic evaluation. This paper uses a novel Markov model to compute the yield. Unlike a previous method which uses a binomial distribution, our TS can use intermediate tests (Intmed-T). This paper shows an efficient TS with a modest level of redundancy to achieve 100% first-pass MCM yield for a particular system. Two methods using Intmed-T for FTol-MCM are proposed and analyzed. When Intmed-T are used for all mounted chips, FTol-MCM with more than a few chips require known-good chips of at least a 99.9% probability-good for achieving a high yield. An efficient TS with a modest level of redundancy can exist for achieving a 100% first-pass MCM yield for a particular system. A yield-analysis model using the least recently tested (LRT) TS in this paper provides a very good figure-of-merit due to its cost, delivery, number of tests, and reliability benefits for current technology. Extensive parametric results for the analysis show that LRT-TS can be applied to calculate the overall yield for FTol-MCM more accurately and efficiently, thereby improving the system reliability     

非挥发性记忆体Read Disturb测试方法的研究

DDF是一种高容量的NAND Flash。以DDF产品为例,研究和讨论了它的Read Disturb测试方法。受测试时间的限制,只能选择局部的存储区间进行DDF的Read Disturb测试。这样局部区间的测试结果是否能够代表整个芯片的性能,设计了一套实验,对这个课题进行了研究和讨论。依据非挥发性记忆体产品的特性,主要以阈值电压的分布为参考来评价DDF芯片性能的一致性和性能恶化趋势的一致度。最后的实验结果证明了这种测试方法的正确性和合理性。这种分析方法也可以用于其他非挥发性记忆体产品的其他可靠性测试项目的评估。     

一种通过PCI总线配置FPGA的设计方法

在软件无线电领域中,系统必须具有较强的动态重构能力。这里讨论PCI协议特点和FPGA配置过程．给出一种通过PCI总线配置卡上FPGA的设计方法。硬件部分采用CPLD实现读写配置空间、PCI总线时序和FPGA配置时序,软件部分采用WinIO作为驱动程序。设计上简洁、灵活,不依赖专用PCI接口芯片,也不需要下载电缆。实践证明,这种方法便捷可靠。对PCI卡的设计具有很好的参考价值。