High-accuracy and low signal distortion on-chip auto-calibrating architecture for continuous-time filters

A high-accuracy on-chip auto-calibrating architecture is presented to compensate the process and temperature parameter variations in high-linearity continuous-time filter. The on-chip auto-calibrating architecture consists of a clock generating circuit, a voltage comparator, a digital tuning engine, and an analog integrator with similar time-constants as the tuned filter. Discrete capacitor arrays are utilized to tune filter automatically for preserving a high linearity. A fourth-order RC filter for GNSS receivers is fabricated in 0.18 µm CMOS process to verify the performance of proposed tuning architecture. With adjustment, this filter achieves less than 5 % frequency uncertainty. The whole circuit consumes 5.2 mA under a 1.8 V supply and occupies a die area of 0.55 mm². Both the post-layout simulation and measured results indicate that the auto-calibrating architecture is a useful and adequate solution to compensate the errors caused by factors such as fabrication tolerances, changes in operating conditions, parasitic effects and aging.     

VLSI communication interface for time-triggered real-time systems

This paper describes the design of a VLSI communication controller for the time-triggered protocol (TTP/C) as the result of a microelectronics development project done at Carinthia Tech Institute in cooperation with industrial partners. TTP/C is an emerging communication protocol for fault-tolerant real-time systems. Typical applications are safety-critical digital control systems such as drive-by-wire and fly-by-wire. We applied a VHDL-based design flow to implement digital standard cell logic, RAMs, flash memory and analog cells into a 27 mm² chip using 0.35 μ CMOS technology. First fully-tested production samples are available and proved the design to be first time right. At this year’s SAE (Society of Automotive Engineers) World Congress in Detroit, from more than 5000 innovative products presented, the TTP controller IC was nominated as ‘Top Product of the Year’.     

A Phase‐Locked Loop with Embedded Analog‐to‐Digital Converter for Digital Control

A phase‐locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog‐to‐digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power‐down mode while avoiding long wake‐up time. The PLL implemented in a 0.18 µm CMOS process occupies 0.35 mm² active area. From a 1.8 V supply, it consumes 59 mW and 984 µW during the normal and power‐down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.     

A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture

An analog computing-based systolic architecture which employs multiple neuroprocessors for high-speed early vision processing is presented. For a two-dimensional image, parallel processing is performed in the row direction and pipelined processing is performed in the column direction. The mixed analog/digital design approach is suitable for implementation of electronic neural systems. Local data computation is executed by analog circuitry to achieve full parallelism and to minimize power dissipation. Inter-processor communication is carried out in the digital format to maintain strong signal strength across the chip boundary and to achieve direct scalability in neural network size. For demonstration purposes, a compact and efficient VLSI neural chip that includes multiple neuroprocessors for high-speed digital image restoration is designed. Measured results of the programmable synapse, and statistical distribution of measured synapse conductances are presented. Based on these results, system-level analyses at 8-bit resolution are conducted. A 8.0×6.0-mm ² chip from a 1.2-µm CMOS technology can accommodate 5 neuroprocessors and the speed-up factor over the Sun-4/75 SPARC workstation is around 450. This chip achieves 18 Giga connections per second.This research was partially supported by DARPA under Contract MDA 972-90-C-0037 and by TRW Inc., Samsung Electronics Co., Ltd., and NKK Corp.     

Low-Power CMOS Interface for Recording and Processing Very Low Amplitude Signals

In this paper, we describe a low-power low-voltage CMOS very low signal acquisition analog front-end of sensor electronic interfaces. These interfaces are mainly dedicated to biomedical implantable devices. In this work, we focus on the implantable bladder controller. Since the nerve signal has very low amplitude and low frequency, it is, at first fed to a low-voltage chopper amplifier to reduce the flicker (1/f) noise and then amplified with a programmable gain high CMRR instrumentation amplifier. This is followed by an analog signal processing circuit to rectify and bin-integrate (RBI) the amplified signal. The resulting RBI is then converted to digital and transferred to the implant's central processor where information about bladder can be extracted. The numerous analog modules of the system have been implemented in CMOS 0.35 μm, 3.3 V technology. The design, simulation and measurement results of the proposed interface are presented. At supply voltage of 2.2 V the power dissipation is less than 1.4 mW, the input equivalent noise is 56 nV/ $\sqrt {{\text{Hz}}} $ and the error in RBI calculation is less than 0.15%.     

CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design based on current-mode data converters is presented herein. Continuous-time algorithmic converters are chosen to reduce the control circuitry and to obtain a modular design based on a cascade of bit cells. Several circuit structures to implement these cells are presented and discussed. The one that is selected enables a better trade-off speed/power than others previously reported in the literature while maintaining a low area occupation. The resulting multiplier/divider circuit offers a low voltage operation, provides the division result in both analog and digital formats, and it is suitable for applications of low or middle resolution (up to 9 bits) like applications to fuzzy controllers. The analysis is illustrated with Hspice simulations and experimental results from a CMOS multiplier/divider prototype with 5-bit resolution. Experimental results from a CMOS current-mode fuzzy controller chip that contains the proposed design are also included.     

65nm CMOS工艺单收单发IEEE802.11AC芯片的MAC控制器的设计实现

本文提出一种兼容IEEE80211AC SISO的无线局域网SOC芯片,芯片集成模拟前端、数字基带处理、媒体访问控制处理器模块,采用SMIC 65nm 1P6M CMOS工艺实现,测试结果表明,在正常工作条件下能提供较高的吞吐率、灵活的速率选择以及良好的兼容性,在标准IEEE802.11AC SISO模式下,测试所得UDP吞吐率为267M b/s。     

A Mixed-Mode Analog Neural Network Using Current-Steering Synapses

A hardware neural network is presented that combines digital signalling with analog computing. This allows a high amount of parallelism in the synapse operation while maintaining signal integrity and high transmission speed throughout the system. The presented mixed-mode implementation achieves a synapse density of 4 k per mm² in 0.35 μm CMOS. The current-mode operation of the analog core combined with differential neuron inputs reaches an analog precision sufficient for 10 bit parity while running at a speed of 0.8 Teraconnections per second.     

A reconfigurable analog processor using coarse-grained,heterogeneous configurable analog blocks for field programmable mixed-signal processing

A field programmable analog array (FPAA), designed for a reconfigurable analog processor, introduces coarse-grained, heterogeneous configurable analog blocks that improves performance and power consumption. Designed in an SMIC standard 0.18 μm CMOS process, mixed-signal processing can be performed by the assistance of an on-chip MCU and configurable digital blocks. Relative precision of the analog processing is 99.5%. A PID controller is shown as an application example. With a total die area of 11 mm², the maximum power consumption is 17.6 mA with a 3.3 V supply voltage, resulting in a 17× improvement in energy-efficiency over current conventional FPAAs.     

A 0.003-mm2, 0.35-V, 82-pJ/conversion ultra-low power CMOS all digital temperature sensor for on-die thermal management

In this paper, a 0.35 V, 82 pJ/conversion ring oscillator based ultra-low power CMOS all digital temperature sensor is presented for on-die thermal management. We utilize subthreshold circuit operation to reduce power and adopt an all-digital architecture, consisting of only standard digital gates. Additionally, a linearization technique is proposed to correct the nonlinear characteristics of subthreshold MOSFETs. A bulk-driven 1-bit gated digitally controlled oscillator is designed for the temperature sensing node. Also, a 1-bit time-to-digital converter is employed in order to double the fine effective resolution of the sensor. The proposed digital temperature sensor has been designed in a 90-nm regular V _T CMOS process. After a two-point calibration, the sensor has a maximum error of ?0.68 to +0.61 °C over the operating temperature range from 0 to 100 °C, while the effective resolution reaches 0.069 °C/LSB. Under a supply voltage of 0.35 V, the power dissipation is only 820 nW with the conversion rate of 10K samples/s at room temperature. Also, the sensor occupies a small area of 0.003 mm².     

Design of a memristor based fuzzy processor

This paper presents a mixed-signal hybrid CMOS/Nano circuit to implement a fully programmable fuzzy processor that performs the zero-order Sugeno's algorithm. The programmability is incorporated in both the rule base and the membership function generator. Membership functions are stored in a memristor-based crossbar array, whereas digital memory is utilized to form a rule base. Each linguistic value whose shape can be independently chosen is stored in each row of the crossbar. Moreover, the adjacent linguistic values can have any order of overlapping ratio. Consequently, a very powerful and flexible fuzzifier is designed.The analog signal processing blocks are designed in both current and voltage mode to simplify the circuit complexity while the digital circuitry is utilized to add programmability to the whole processor. A fuzzy logic controller with nine rules, two inputs, and one output was successfully simulated using HSPICE with 350 nm technology. Simulation results confirm the proper operation of the processor that can operate up to 10 MFLIPS (Mega Fuzzy Logic Inference Per Seconds) while consuming 3.49 mW (@vdd 3.3v). Furthermore, simulation results show that an equivalent precision of 6-bits is achieved in the output signal generation. The circuit is laid out and it takes an area of approximately 0.614 mm².     

All-digital A/D converter TAD with high-resolution and low-power for sensor/RF digitization

For achieving both high resolution and low power of a sensor/RF interface, time-domain processing using full-digital circuits, which deals with only two voltage levels (i.e., V _in-supply-voltage and ground-level), is presented. In a much broader sense, digital circuits can be used for time-domain processing instead of conventional analog signal processing. In this study, an all-digital 6- to 16-bit adaptive sensor-interface ADC is experimentally evaluated for high-resolution and low-power operation along with high scalability. The circuit architecture is completely digital, using a ring-delay-line (RDL) driven by an input voltage V _in as its power supply. Resolutions can be controlled by setting its conversion time T _cv, resulting in 16 bit (1 kS/s, 34 μW) and 6 bit (1 MS/s, 48 μW) with a prototype IC in a low-cost 0.65-μm (650-nm) digital CMOS, achieving the sensor digitizer (sensor-digitization product) of a pressure sensor ASIC. The all-digital structure has been scaled into a 0.18-μm technology, and the test IC presented a higher performance with 28 μV/LSB (160-kS/s). Finally, as an RF digitization application, the circuit is demonstrated to realize the time-domain processing of an RF signal, working as both mixer and ADC, achieving minimum/maximum detectable sensitivity of 0.7-μVrms/100-mVrms, respectively, for a 40-kHz sine wave at the LNA input terminal of a 0.18-μm digital CMOS one-chip radio-controlled clock receiver IC.     

Low-voltage CMOS circuits for analog iterative decoders

Iterative decoders, including Turbo decoders, provide near-optimal error protection for various communication channels and storage media. CMOS analog implementations of these decoders offer dramatic savings in complexity and power consumption, compared to digital architectures. Conventional CMOS analog decoders must have supply voltage greater than 1 V. A new low-voltage architecture is proposed which reduces the required supply voltage by at least 0.4 V. It is shown that the low-voltage architecture can be used to implement the general sum-product algorithm. The low-voltage analog architecture is then useful for implementing Turbo and low-density parity check decoders. The low-voltage architecture introduces new requirements for signal normalization, which are discussed. Measured results for two fabricated low-voltage analog decoders are also presented.     

A 12-Gb/s HDMI 2.1 quarter-rate transmitter in 28-nm bulk CMOS process

A four-lane 12-Gb/s per lane high-definition multimedia interface (HDMI) 2.1 transmitter is developed in 28-nm bulk CMOS process. To relieve the burden of the generation and distribution of clock, quarter-rate architecture is employed where the duty-cycle and phase spacing errors of multi-phase clock are automatically corrected by analog–digital converter based digital logic. The output driver terminated with 3.3-V supply is implemented only with 1.8- and 1.0-V transistors which are protected from over-voltage stress by double-cascoding with adaptive bias generation. The 4-lane HDMI 2.1 transmitter consumes 12.0-mW/lane at 12-Gb/s and occupies 0.12-mm² active area.     

CMOS folding A/D converters with current-mode interpolation

A CMOS folding and interpolating A/D conversion architecture fully compatible with standard digital CMOS technology is described. Fully-differential, continuous-time, current-mode, open-loop analog circuitry is used to achieve high speed. Results from 125 Ms/s 8-b and 150 Ms/s 6-b prototypes implemented in a digital 1 μm n-well CMOS process are presented. The 8-b (6-b) converter occupies 4 mm² (2 mm²) and dissipates 225 mW (55 mW) from a single 5 V power supply     

H ∞ Control of T-S Fuzzy Singularly Perturbed Systems Using Multiple Lyapunov Functions

In this paper, H _∞ controller synthesis of T-S fuzzy singularly perturbed systems based on fuzzy and non-fuzzy multiple Lyapunov functions is discussed. By assuming some lower bounds for the grades of fuzzy membership functions and using the elimination lemma, the design conditions are presented in the form of linear matrix inequalities (LMIs). Considering ε as the singular perturbation parameter, it is shown that the ε-dependent controller in the absence of disturbances, results in an asymptotically stable closed-loop system, and in the presence of disturbances, satisfies the H _∞-norm condition for all ε∈(0,ε ^?]. The resulting LMIs are feasible for larger values of ε ^? compared to those of the previous methods. Moreover, for the case that the value of ε is not available for feedback, Finsler’s lemma is used to separate the controller gains and the ε-dependent Lyapunov matrix, and to achieve an ε-independent control. An example is presented to illustrate the validity of the design techniques.     

A 1.0-mW, 71-dB SNDR,fourth-order ΣΔ interface circuit for MEMS microphones

In this paper an integrated interface circuit for condenser MEMS microphones is presented. It consists of an input buffer followed by a multi-bit (12-levels), analog, second-order ΣΔ modulator and a fully-digital, single-bit, fourth-order ΣΔ modulator, thus providing a single-bit output signal with fourth order noise shaping, compatible with standard audio chipsets. The circuit, supplied with 3.3 V, exhibits a current consumption of 215 μA for the analog part and 95 μA for the digital part. The measured signal-to-noise and distortion ratio (SNDR) is 71 dB, with an input signal amplitude as large as −1.8 dB with respect to full-scale, obtained thanks to the use of a feed-forward architecture in the analog ΣΔ modulator, which relaxes the voltage swing requirements of the operational amplifiers. The test chip, fabricated in a 0.35-μm CMOS process, occupies an area of 3 mm², including pads.     

Highly-integrated analog baseband for 3G WCDMA featured cellular phones

This paper presents an analog baseband circuit which is fully integrated in a 3G WCDMA digital baseband controller (modem) together with an application (multimedia) processor targeted featured cellular phones. The analog baseband is made by two (I and Q) 8b+ Analog-to-digital converters (ADCs), two (I and Q) 10b digital-to-analog converters with filters, a 10b auxiliary ADC, and a common circuit for the generation of an accurate bandgap reference voltage and biasing currents. To avoid performance degradations caused by crosstalk among the converters or from the nearby digital baseband activity, several design and layout precautions have been taken. All performance are guaranteed in mass production from ?40 to +130 °C. The analog baseband converters are designed at 2.5 V supply in a 65 nm CMOS process with double oxide and MIM capacitor options. Total power consumption and area are 32.8 mW and 1.8 mm², respectively.     

A dual mode UHF EPC Gen 2 RFID tag in 0.18 μm CMOS

A dual mode UHF RFID transponder in 0.18 μm CMOS conforming to the EPC Gen 2 standard is presented. Low voltage design of the analog and digital blocks enables the chip to operate with a 1 V regulated voltage and thus to reduce the power consumption. The novel dual mode architecture enables the chip to work in passive and battery-assisted modes controlled by the reader. A custom Gen 2 based command switches the operation mode of the circuit. By using a special clock calibration method the chip operates from 1.2 to 5 MHz clock frequency. Several low power techniques are employed to reduce the power consumption of the chip which is essential in passive RFID tags. Measurement results show that the chip consumes 12 μW at 1 V supply voltage when it communicates with the reader. The chip is fabricated in 0.18 μm standard CMOS technology and occupies 0.95 mm² die area.     

A Double Sampling 8-Bit, 50 MS/s, 32 mW Pipeline Converter with +6 dB Overdrive Headroom

An 8-bit, 50 MS/s pipeline converter is presented with peak SNR and SFDR of 43.1 dB and 52.5 dB, corresponding to effective number of bits of 6.9. The circuit is implemented in a 0.35 m CMOS process, the core area is 0.36 mm² and its analog and digital current consumptions (including I/O buffers) are 6.2 mA and 4.5 mA from a 3 V supply. The low power consumption is achieved by using two banks of sampling capacitors (double sampling) and a mixed architecture giving 1+1+1+2+3 bits per stage. The mixed architecture means that a full ninth bit cannot be coded, but instead it is a employed as an almost 6 dB overdrive input range. The maximum allowable comparator errors in different architectures are calculated and the benefits of excess redundancy are discussed.