ISAAC: a symbolic simulator for analog integrated circuits

The symbolic simulator ISAAC (interactive symbolic analysis of analog circuits) is presented. The program derives all AC characteristics for any analog integrated circuit (time-continuous and switched-capacitor, CMOS, JFET, and bipolar) as symbolic expressions in the circuit parameters. This yields analytic formulas for transfer functions, CMRR (common-mode rejection ratio), PSRR (power-supply rejection ratio), impedances, noise, etc. Two novel features are included in the program. First, the expressions can be simplified with a heuristic criterion based on the magnitudes of the elements. This yields interpretable formulas showing only the dominant terms. Second, the explicit representation of mismatch terms allows the accurate calculation of second-order effects, such as the PSRR. ISAAC provides analog designers with more insight into the circuit behavior than do numerical simulators and is a useful tool for instruction or designer assistance. Moreover, it generates complete analytic AC circuit models, which are used for automatic sizing in a nonfixed topology analog module generator. The program's capabilities are illustrated with several examples. The efficiency is established by a dedicated sparse-matrix algorithm     

Generalized Simulation-Based Posynomial Model Generation for Analog Integrated Circuits

This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. Both the coefficient set as well as the exponent set of the posynomial expression, for some performance as a function of the design variables, are determined based on performance data extracted from SPICE simulation results with device-level accuracy. Techniques from design of experiments (DOE) are used to generate an optimal set of sample points to fit the models. We will prove that the optimization problem formulated for this problem typically corresponds to a non-convex problem, but has no local minima. The presented method is capable of generating posynomial performance expressions for both linear and nonlinear circuits and circuit characteristics. This approach allows to automatically generate an accurate sizing model that can be used to compose a geometric program that fully describes the analog circuit sizing problem. The automatic generation avoids the time-consuming nature of hand-crafted analytic model generation. Experimental results illustrate the capabilities of the presented modeling technique.     

Variability aware SVM macromodel based design centering of analog circuits

Design centering is the term used for a procedure of obtaining enhanced parametric yield of a circuit despite the variations in device and design parameters. The process variability in nanometer regimes manifest into variations in these devices and design parameters. During design space exploration of analog circuits, a methodology to find design-instances with better yield is necessitated; this would ensure that the circuit will function as per specifications after fabrication, even with impact of statistical variations. We need to evaluate circuit performance for a given instance of a circuit-design identified by possessing a set of nominal values of device-design parameters. A lot of instances need be searched, having different sizes for a given circuit topology. HSPICE is very compute intensive. Instead, we employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits of different sizing during yield optimization loops. These performance macromodels are found to be as accurate as SPICE and at the same time, time-efficient for use in sizing of analog circuits with optimal yield. Process variability aware SVM macromodels are first trained and then used inside the Genetic algorithm loops for design centering of different circuits, subsequently resulting into sized-circuit instances having optimal yield. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. The application of this design centering approach as process variability analysis tool is illustrated on various circuits e.g. two stage op amp, voltage controlled oscillator and mixer circuit with layouts drawn into 90?nm UMC technology (Euro-practice).     

Analog circuit optimization system based on hybrid evolutionary algorithms

This paper investigates a hybrid evolutionary-based design system for automated sizing of analog integrated circuits (ICs). A new algorithm, called competitive co-evolutionary differential evolution (CODE), is proposed to design analog ICs with practical user-defined specifications. On the basis of the combination of HSPICE and MATLAB, the system links circuit performances, evaluated through electrical simulation, to the optimization system in the MATLAB environment, once a circuit topology is selected. The system has been tested by typical and hard-to-design cases, such as complex analog blocks with stringent design requirements. The results show that the design specifications are closely met, even in highly-constrained situations. Comparisons with available methods like genetic algorithms and differential evolution, which use static penalty functions to handle design constraints, have also been carried out, showing that the proposed algorithm offers important advantages in terms of optimization quality and robustness. Moreover, the algorithm is shown to be efficient.     

一种分析模拟电路中互连线的新方法

互连线在高性能模拟集成电路中的影响已变得越来越不可忽视,部分元等效电路法（Partial Element Circuit,PEEC）是一种分析互连线的有效模型,常用方法是再用SPICE等数值模拟软件对PEEC模型进行分析。文中提出的用符号分析法模拟PEEC模型以及其它电路元器件,具有大大降低运算量等优点。基于这一点开发出一套交互式程序,使得包括考虑互连线影响的模拟电路的设计、验证和优化变得更容易、更有效率。     

ARIADNE: A constraint-based approach to computer-aided synthesis and modeling of Analog integrated circuits

The ARIADNE approach to computer-aided synthesis and modeling of analog circuits is presented. It is a mathematical approach based on the use of equations. Equations are regarded as constraints on a circuit's design space and analog circuit design is modeled as a constraint satisfaction problem. To generate and efficiently satisfy constraints, advanced computational techniques such as constraint propagation, interval propagation, symbolic simulation, and qualitative simulation are applied. These techniques cover design problems such as topology construction, modeling, nominal analysis, tolerance analysis, sizing and optimization of analog circuits. The advantage of this approach is the clear separation of design knowledge from design procedures. Design knowledge is modeled in declarative equation-based models (DEBMs). Design procedures are implemented into general applicable CAD tools. The ARIADNE approach closely matches the reasoning style applied by experienced designers. The integration of synthesis and modeling into one frame and the clear separation of design knowledge from design procedures eases the process of extending the synthesis system with new circuit topologies, turning it into an open design system. This system can be used by both inexperienced and experienced designers in either interactive or automated mode.     

基于Matlab带阻滤波器电路设计及参数寻优

各种滤波器电路在模拟电路设计中经常出现,由于在实际工程中,电阻、电容的值均连续,因此在设计电路时,电路参数计算繁冗且计算量大,并且手工计算出的结果并非是一个最优解,文中借助Matlab的计算功能,根据带阻滤波器的传递函数,建立了相应的标准电路模型以及参数最优化模型,最后使用Matlab中的数学工具箱编写出相应的求解程序,可以快速得到符合要求的电路参数,大幅提高了设计效率,有较强的实用性。     

Operational-amplifier compilation with performance optimization

A method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described. By merging circuit and layout design into a single design process, analog circuits can be optimally designed taking layout parasitics fully into account. Using the method, a CMOS operational-amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A procedural layout technique is employed to generate a compact and practical layout. A nonlinear optimization method for device sizing which relies on the results of simulations based on the circuit extracted from the layout is applied. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density     

一种基于数模控制的高压电源模块辅助电源

对传统拓扑结构应用于高压辅助电源设计中的缺点进行分析,提出了一种新型的数模控制宽输入高压辅助电源设计方案。对该方案进行了原理分析,较全面地评估了单片机控制辅助电源启动电路、PWM控制电路、反激主电路、变压器等模块的设计参数。最后,采用该方案,设计了一款实验电路。仿真和实验电路测试结果表明,该方案满足设计要求。     

Implementation of Multi-Valued Logic Gates Using Full Current-Mode CMOS Circuits

In this paper, a novel multi-valued logic gate set is designed by using only current-mode CMOS circuits. The gate set consists of min, max, inverter, literal, and cyclic operators based on a current-mode, versatile, novel threshold topology. They are shown to exhibit better static and dynamic behavior and consume less area compared to previous MVL design topologies and binary-logic counterparts. The gate circuits are investigated in terms of analog design aspects, such as mismatch and noise. The proposed topology is compared to previous topologies in terms of attainable radix and DC characteristics. A radix-8 multiplex function and a radix-8 full-adder circuit is designed to demonstrate the advantages of new current-mode multi-valued logic circuits.     

Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area

The reliability of analog integrated circuits becomes a major concern for the semiconductor industry as technology continuously scales. Among the many contributing factors, manufacturing process induced parameter variations and lifetime operational-condition-dependent transistor aging are two major hurdles limiting the reliability of analog circuits. Process variations mainly influence the parametric yield value of the fresh circuits, while transistor aging due to physical effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), will cause another yield loss during circuit lifetime. In the past decades, the two issues were mainly studied separately by various communities, but analog designers nowadays need an accurate yet efficient method to analyze and optimize their circuits during the design phase, to ensure a more robust design tolerant of such joint effects.This paper proposes an efficient method for sizing of analog circuits for reliability. It is based on the analysis and optimization of the fresh worst-case distance value for each circuit performance, which can be used to characterize the robustness of circuits considering process variations and aging effects in terms of x-sigma. The fresh and aged sizing rules as well as the maximum area constraints are checked during the optimization. The trade-off between the circuit lifetime and the price we pay in terms of layout area is studied in detail. According to the result of this trade-off analysis, a longer circuit lifetime requires more total area to be spent in layout, and designers can ensure the circuit robustness with certain layout area consumption.     

An effective thermal circuit model for electro-thermal simulation of SOI analog circuits

A physics-based thermal circuit model is developed for electro-thermal simulation of SOI analog circuits. The circuit model integrates a non-isothermal device thermal circuit with interconnect thermal networks and is validated with high accuracy against finite element simulations in different layout structures. The non-isothermal circuit model is implemented in BSIMSOI to account for self-heating effect (SHE) in a Spice simulator, and applied to electro-thermal simulation of an SOI cascode current mirror constructed using different layouts. Effects of layout design on electric and thermal behaviors are investigated in detail. Influences of BOX thickness are also examined. It has been shown that the proposed non-isothermal approach is able to effectively account for influences of layout design, self-heating, high temperature gradients along the islands, interconnect temperature distributions, thermal coupling, and heat losses via BOX and interconnects, etc., in SOI current mirror structures. The model provides basic concepts and thermal circuits that can be extended to develop an effective model for electro-thermal simulation of SOI analog ICs.     

A fuzzy logic based approach for parametric optimization of MOS operational amplifiers

In this work, we have used the concept of fuzzy logic to build a CAD tool for the parametric optimization of MOS operational amplifiers (op-amps). In order to capture human intentions to express the requirements for a particular application, e.g. minimize power, maximize gain, etc., each of the performance specifications of a given topology is assigned a membership function to measure the degree of fulfillment of the objectives and the constraints. A number of objectives are optimized simultaneously by assigning weights to each of them representing their relative importance, and then by clustering them to form the objective function, which is solved by Powell's direct search algorithm. After optimization, the program creates a SPICE netlist of the circuit topology for the verification of the design. Initially, this approach was used for parametric optimization of simple bipolar and MOS circuits, e.g. current mirrors, gain stages, differential amplifiers, etc. Encouraged by these results, it was applied to much more complex blocks, such as op-amps. The design results obtained from our optimization program showed an excellent agreement with those obtained from SPICE simulation for the op-amp topologies considered in this work.     

Γ (Gamma): A SaaS-enabled fast and accurate analog design System

With ever increasing demand for lower power consumption, lower cost, and higher performance, designing analog circuits to meet design specifications has become an increasing challenging task, Analog circuit designers must, on one hand, have intimate knowledge about the underlining silicon process technology׳s capability to achieve the desired specifications. They must, on the other hand, understand the impact of tweaking circuits to satisfy a given specification on all circuit performance parameters. Analog designers have traditionally learned to tackle design problems with numerous circuit simulations using accurate circuit simulators such as SPICE, and have increasingly relied on trial-and-error approaches to reach a converging point. However, the increased complexity with each generation of silicon technology and high dimensionality of searching for solutions, even for some simple analog circuits, have made the trial-and-error approach extremely inefficient, causing long design cycles and often missed deadlines. Novel rapid and accurate circuit evaluation methods that are tightly integrated with circuit search and optimization methods are needed to aid design productivity.Furthermore, the current design environment with fully distributed licensing and supporting structures is cumbersome at best to allow efficient and up-to-date support for design engineers. With increasing support and licensing costs, fewer and fewer design centers can afford it. Cloud-based software as a service (SaaS) model provides new opportunities for CAD applications. It enables immediate software delivery and update to customers at very low cost. SaaS tools benefit from fast feedback and sharing channels between users and developers and run on hardware resources tailored and provided for them by the software vendor. On the downside, web-based tools are expected to perform in a very short turn-around schedule and be always responsive.This paper presents a list of innovations that come together to a new class of analog design tools: 1). Lookup table-based approach (LUT) to model complex transistor behavior provides both the necessary accuracy and speed essential for repeated circuit evaluations. 2). The proposed system architecture tight integrate the novel LUT approach with novel system level functions to allow further significantly better accuracy/speed tradeoff and faster design convergence with designer׳s intent. 3). Incorporating use inputs at key junctures of the design process allows the tool to better capture designer׳s intent and improve design convergence. 4). The combination of high accuracy and faster evaluation time make it possible to incorporate SaaS features, such as short solution space navigation steps and crowdsourcing, into the tool. This allows sharing of server-side resources between many users. Instead of fully automating a signoff circuit optimization process, the proposed tool provides effective aid to analog circuit designers with a dash-board control of many important circuit parameters with several orders faster in computation time than SPICE simulations.     

Accurate circuit model of interdigital capacitor and itsapplication to design of new quasi-lumped miniaturized filters withsuppression of harmonic resonance

A general-purpose circuit model of a microstrip interdigital capacitor (IDC) is presented in this paper for use in the design of new quasi-lumped miniaturized filters. This computer-aided-design-oriented model is developed as a versatile admittance π-network with the short-open calibration technique that we have recently proposed for accurate parameter extraction of a circuit from its physical layout. This technique is self-contained in our method of moments, which accounts for frequency dispersion and fringing effects. A J-inverter topology is further conceived to explicitly formulate the coupling behavior of three types of IDC's. This model provides a unique way for the IDC-related circuit synthesis and optimization based on the accurate equivalent-circuit network extracted from the field theory algorithm. It is validated theoretically and experimentally through an example of a line resonator connected with two IDC's. The proposed scheme is used in the design and optimization of new low-loss miniaturized quasilumped integrated circuits, namely, two types of three-pole direct-coupled bandpass filters. Our measured and predicted results show interesting features of the proposed filter structure such as size reduction and suppression of harmonic resonance if the line resonator is attached by series-connected equivalent inductance     

模拟电子电路虚拟实验平台的设计与实现

提出了用于模拟电子电路实验教学的虚拟实验平台，该平台可以实现模拟电子电路实验实际操作与计算机模拟分析相结合的实验教学方式，同时应用虚拟仪器技术对电路进行测试和故障查找，从而培养学生应用EDA技术设计电路系统和实际操作的能力。     

Enhanced analog “yields” cost-effective systems-on-chip

As device feature sizes of analog MOS circuits are reduced to the deep-submicron ranges, the effect of process variability on circuit performance and reliability is magnified. Yield is becoming more and more critical and statistical methods are required to simulate the effect of process variability to enable circuit designers to “design-in” quality through circuit robustness. More work is needed particularly in the areas of modeling and statistical CAD of submicron, low-voltage mixed-signal ICs. The characterization work needed to tune models to specific VLSI technology, implementation into the SPICE and APLAC simulators, and use in design and optimization of analog and digital VLSI circuits