折叠式共源共栅运算放大器的0.6μm CMOS设计

折叠式共源共栅结构的运算放大器不仅能提高增益、增加电源电压噪声抑制能力,而且在输出端允许自补偿.基于0.6μm CMOS工艺,验证了一种折叠共源共栅的运算放大器的参数指标.理论计算和实际分析相结合,仿真结果达到设计指标要求.     

一种低压低功耗CMOS折叠-共源共栅运算放大器的设计

本文设计了一种低压低功耗CMOS折叠一共源共栅运算放大器.该运放的输入级采用折叠-共源共栅结构,可以优化输入共模范围,提高增益;由于采用AB类推挽输出级,实现了全摆幅输出,并且大大降低了功耗.采用TSMC 0.18μm CMOS工艺,基于BSIM3V3 Spice模型,用Hspice对整个电路进行仿真,结果表明:与传统结构相比,此结构在保证增益、带宽等放大器重要指标的基础上,功耗有了显著的降低,非常适合于低压低功耗应用.目前,该放大器已应用于14位∑-△模/数转换电路的设计中.     

一种低压低功耗CMOS折叠-共源共栅运算放大器的设计

设计了一种低压低功耗CMOS折叠-共源共栅运算放大器。该运放的输入级采用折叠-共源共栅结构,可以优化输入共模范围,提高增益;由于采用AB类推挽输出级,实现了全摆幅输出,并且大大降低了功耗。采用TSMC 0.18μmCMOS工艺,基于BSIM3V3 Spice模型,用HSpice对整个电路进行仿真,结果表明:与传统结构相比,此结构在保证增益、带宽等放大器重要指标的基础上,功耗有了显著的降低,非常适合于低压低功耗应用。目前,该放大器已应用于14位∑-Δ模/数转换电路的设计中。     

一个自偏压互补折叠式共源共栅放大器的设计

对传统CMOS折叠式共源共栅运算放大器进行分析和总结,利用自偏压互补折叠技术实现了一种高性能CMOS自偏压互补折叠式共源共栅运算放大器。这个设计消除了6个外部偏置电压,减小了供电电压,并且提高了输出摆幅和开环增益,同时,使用这个方案还可以使芯片面积、功耗、偏置部分对噪声和串扰的灵敏度降低,最后描述了设计过程并给出了设计的仿真结果,证实该结构的可行性。     

一种基于前馈补偿技术的高性能CMOS运算放大器

基于传统CMOS折叠共源共栅运算放大器的分析和总结,应用前馈补偿技术,实现了一种高性能CMOS折叠共源共栅运算放大器,不仅保证了高开环增益,而且还大大减小了运放的输入失调电压。设计采用TSMC 0.35μm混合信号CMOS工艺实现,采用Hspice进行仿真,仿真结果表明运放的直流开环增益为95 dB,输入失调电压为0.023 mV,负载电容为2pF时的相位裕度为45.5°。     

一种用于DRSSADC电路的积分器设计

介绍了一种用于DRSSADC(dual-ramp-single-slop analog to digital converter)电路的积分器设计,该积分器电路采用全差分结构,主要包含了折叠共源共栅运算放大器和改进型开关电路。在分析积分器原理的基础上,主要讲述了改进型开关电路和折叠共源共栅运算放大器的设计。在0.35μm CMOS工艺下,3V电源电压,对折叠共源共栅运算放大器进行了HSPICE仿真。仿真结果表明,该电路的直流增益64.5dB、单位增益带宽7MHz,相位裕度85°,功耗仅为87.5μW,适用于DRSSADC。     

一种高速轨对轨折叠式共源共栅运算放大器设计

介绍了一种低电压、低功耗、动态摆幅大、高频带的运算放大器,电路采用恒定跨导的轨对轨输入级,偏置电路采用折叠共源共栅电流镜结构,采用0．35uM CMOS工艺实现,有较好的兼容性,可应用于基带数字通信芯片设计及其相关领域。     

一种高单位增益带宽CMOS全差分运算放大器

设计并讨论了一种高单位增益带宽CMOS全差分运算放大器。由于折叠共源共栅结构电路具有相对高的单位增益带宽以及开关电容共模反馈电路稳定性好、对运放频率特性影响小等优点,故设计的放大器采用了折叠共源共栅结构以及开关电容共模反馈电路技术,并达到了高单位增益带宽的设计目的。基于TSMC0·25μmCMOS工艺,仿真结果表明,在2·5V的单电源电压下,运算放大器的直流开环增益为70dB,单位增益带宽为500MHz。     

一种采用增益增强方法的CMOS全差分运算放大器

设计了一种全差分、增益增强CMOS运算放大器。该放大器由三个折叠式共源共栅运算放大器组成，可用于12位40MHz采样频率的流水线A／D转换器。详细分析了折叠式共源共栅运算放大器中由增加增益增强电路产生的零极点对。该放大器在0.35μm CMOS工艺中开环增益为112dB，单位增益带宽为494MHz。     

一种高速CMOS全差分运算放大器

设计并讨论了一种高速CMOS全差分运算放大器.设计中采用了折叠共源共栅结构、连续时间共模反馈以及独特的偏置电路,以期达到高速及良好的稳定性.基于TSMC 0.25 μ m CMOS工艺,仿真结果表明,在2.5V的单电源电压下,运算放大器的直流开环增益为71.9dB,单位增益带宽为495MHz(CL=0.5pF),建立时间为24ns,功耗为3.9mW.     

单电源运放的偏置原因分析与偏置方法

运放是模拟电路中的核心元件,近些年来单电源运放因其正常工作时只需提供单路电源的独特优点而应用日益广泛。但是单电源运放的设计却比双电源运放复杂。因此对单电源运放偏置的原因进行了深入的研究,并分析比较了各种不同偏置方法的特点,从而为正确分析和设计单电源运放偏置电路提供依据。     

共源共栅CMOS运算放大器的分析与设计

本文描述了一个共源共栅差分输入级、电流镜偏置输出级结构的两级CMOS运放,它对常规运放的电源电压抑制比、增益、输出驱动能力、噪声、失调等有显著的改善。文中对运放的工作原理及设计技术等进行了详细的叙述,并采用标准CMOS工艺进行了投片试制和采用SPICE进行了电路模拟。结果令人满意,达到了设计指标,证明了设计理论的正确性。该运放已成功地应用于开关电容滤波器芯片的制造。     

Variability aware SVM macromodel based design centering of analog circuits

Design centering is the term used for a procedure of obtaining enhanced parametric yield of a circuit despite the variations in device and design parameters. The process variability in nanometer regimes manifest into variations in these devices and design parameters. During design space exploration of analog circuits, a methodology to find design-instances with better yield is necessitated; this would ensure that the circuit will function as per specifications after fabrication, even with impact of statistical variations. We need to evaluate circuit performance for a given instance of a circuit-design identified by possessing a set of nominal values of device-design parameters. A lot of instances need be searched, having different sizes for a given circuit topology. HSPICE is very compute intensive. Instead, we employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits of different sizing during yield optimization loops. These performance macromodels are found to be as accurate as SPICE and at the same time, time-efficient for use in sizing of analog circuits with optimal yield. Process variability aware SVM macromodels are first trained and then used inside the Genetic algorithm loops for design centering of different circuits, subsequently resulting into sized-circuit instances having optimal yield. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. The application of this design centering approach as process variability analysis tool is illustrated on various circuits e.g. two stage op amp, voltage controlled oscillator and mixer circuit with layouts drawn into 90?nm UMC technology (Euro-practice).     

A multiplexed switched capacitor filter bank

A technique is introduced which allows several integrator capacitors to be multiplexed onto a single operational amplifier. As a result, the op amp can be shared by several switched capacitor filter channels, drastically reducing the number of op amps required for filter banks. Twenty second-order filters have been implemented in a circuit using only two op amps and 2.5 mm/SUP 2/. The design of this system is presented and its performance is discussed. Some loss of signal energy is shown to occur during the multiplexing operations, which reduces filter Q. Causes of this charge loss are described, and its effects on performance are modeled. The design of the op amp used is presented, which incorporates a new system of input stage biasing and differential to single-ended conversion, as well as other features.     

A high precision micropower operational amplifier

An operational amplifier configuration implemented as a true micropower high precision op amp is described. It includes a well controlled and predictable DC biasing network that is insensitive to variations in temperature, supply voltages, and process. Also, it permits single supply operation. Excellent DC precision characteristics, comparable to or better than the very best precision op amps currently available, are realized yet at micropower levels. By simply increasing the biasing currents, a version of this design operates in general purpose applications without any degradation in its high precision characteristics. Thus, the AC performance levels of general purpose op amps are attained at a fraction of supply current. This device is fabricated using a standard bipolar IC process; an ion-implanted JFET is added to simplify biasing.     

A high-frequency fully differential BiCMOS operational amplifier

A high-frequency fully differential BiCMOS operational amplifier design for use in switched-capacitor circuits is presented. The operational amplifier is integrated in a 3.0-GHz, 2-μm BiCMOS process with an active die area of 1.0 mm×1.2 mm. This BiCMOS op amp offers an infinite input resistance, a DC gain of 100 dB, a unity-gain frequency of 90 MHz with 45° phase margin, and a slew rate of 150 V/μs. The differential output range is 12 V. The circuit is operated from a ±5-V power supply and dissipates 125 mW. The op amp is unity-gain stable with 7 pF of capacitive loading at each output. The op amp is a two-stage, pole-split frequency compensated design that uses a PMOS input stage for infinite input resistance and an n-p-n bipolar second stage for high gain and high bandwidth. The frequency compensation network serves both the differential- and common-mode amplifiers so the differential- and common-mode amplifier dynamics are similar. A dynamic switched-capacitor common-mode feedback scheme is used to set the output common-mode level of the first and second stages     

Design for testability of embedded integrated operationalamplifiers

The operational amplifier (op amp) is one of the most encountered analog building blocks. In this paper, the problem of testing an integrated op amp is treated. A new low-cost vectorless test solution, known as oscillation test, is investigated to test the op amp. During the test mode, the op amps are converted to a circuit that oscillates and the oscillation frequency is evaluated to monitor faults. The tolerance band of the oscillation frequency is determined using a Monte Carlo analysis taking into account the nominal tolerance of all important technology and design parameters. Faults in the op amps under test which cause the oscillation frequency to exit the tolerance band can therefore be detected. Some Design for Testability (DfT) rules to rearrange op amps to form oscillators are presented and the related practical problems and limitations are discussed. The oscillation frequency can be easily and precisely evaluated using pure digital circuitry. The simulation and practical implementation results confirm that the presented techniques ensure a high fault coverage with a low area overhead     

Bandwidth optimization of a low power,high speed CMOS current op amp

A current op amp with a differential output and a single-ended input can be configured from a single second generation current conveyor and an output stage with a differential floating current source. Owing to a very simple basic configuration with a single dominant pole, this design combines a high bandwidth with a high open loop gain. In this paper we present the basic configuration, derive the fundamental equations for the performance of the op amp, and describe some design considerations with respect to an optimization of the op amp for a high bandwidth. Simulation results are given from a commercially available 2µm CMOS process resulting in an open loop differential gain of 94dB and a gain-bandwidth product of 128M H z at a supply voltage of 3V and a supply current of 25µA. The design has been experimentally verified through a test circuit and experimental results from this confirm the expected behaviour.     

增益增强型CMOS运算放大器的自动优化算法

在增益增强型运算放大器优化中采用了自动设计方法,此方法在电路性能方程式和自适应遗传优化算法基础上对电路性能指标进行优化。该放大器在0.18μm CM O S工艺条件下中开环增益为92.1 dB,单位增益带宽积为1.78 GH z,相位裕度为55.1°和0.2%建立时间为1.27 ns,同时说明此优化设计方法的有效性。     

Compact High Gain CMOS Op Amp Design using Comparators

This paper discusses the design of high gain, general purpose op amps. The op amp is based on a novel cascaded design using comparators and with structural simplicity approaching that of digital circuits. Ideally, the design tool presented here can be used to optimize gain and CMRR independent of the other op amp performance parameters. The designed op amp has 140 dB open-loop gain and 43 MHz unity gain frequency (GBW) in Berkeley Spice3f Level-2 simulation. The circuit is implemented using a 2.0 m nwell CMOS process through MOSIS. The op amp is self-biased and requires only power supplies of ±2.5 V. It occupies an area of 113 m×474 m.