Optimization of threshold voltage window under tunneling program/erase in nanocrystal memories

This paper analyzes solutions to improve the program/erase (P/E) window for nanocrystal (NC) memory cells, by means of the model presented in our previous work . The limited threshold voltage (V/sub T/) window typically observed in the Fowler-Nordheim (FN) programming regime for NC memories was shown to be a direct consequence of the lack of any conduction and /spl epsi/ mismatch between the tunnel and the interpoly-oxide at steady-state. This condition can be avoided when tunnel oxide conduction is due to direct tunneling, but to assure sufficiently short P/E times very thin oxides are required, sacrificing cell nonvolatility. The use of alternative materials for interpoly dielectric, gate and NC is investigated. Finally, barrier engineering is presented as a valid way to improve the available V/sub T/ window.     

Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell

Read disturb-induced erase-state threshold voltage instability in a localized trapping storage Flash memory cell with a poly-silicon-oxide-nitride-oxide-silicon (SONOS) structure is investigated and reported. Our results show that positive trapped charge in bottom oxide generated during program/erase (P/E) cycles play a major role. Both gate voltage and drain voltage will accelerate the threshold voltage (V/sub t/) drift. Hot-carrier caused disturb effect is more severe in a shorter gate length device at low temperature. A model of positive charge-assisted electron tunneling into a trapping nitride is proposed. Influence of channel doping on the V/sub t/ drift is studied. As the cell is in an "unbiased" storage mode, tunnel detrapping of positive oxide charges is responsible for the threshold voltage shift, which is insensitive to temperature.     

High SCR design for one-transistor split-gate full-featured EEPROM

A high source-coupling ratio design for full-featured EEPROM composed of one-transistor split-gate cells with a cell area of less than 22 F/sup 2/ is proposed. This is in contrast to a traditional cell that requires an extra select transistor and is not area economic when compared to the new design cell. In this design, the cell adopts poly-poly Fowler-Nordheim tunneling to erase, and an inhibited source voltage is used for the unselected cell to achieve bit erase. It has demonstrated excellent program and erase disturb margins and passed 300 k program/erase (P/E) cycling test. It was found that after P/E cycling stress, the cell gains a better erase disturb immunity.     

Metal nanocrystal memory with high-/spl kappa/ tunneling barrier for improved data retention

A nonvolatile memory (NVM) with metal nanocrystal (NC) embedded in high-/spl kappa/ dielectrics is proposed. With the larger work function of the metal NC compared to that of silicon NC, the metal NC memory exhibits the better data retention characteristic. The theoretical analysis showing the effect of the electron barrier height on tunneling current density is also presented to support the importance of work function engineering of the NC in NVM structure. The other electrical characteristics such as the programming transient and data endurance are also studied and described in this paper.     

Capacitance–voltage characteristics of P3HT:PCBM bulk heterojunction solar cells with ohmic contacts and the impact of single walled carbon nanotubes on them

Capacitance–voltage (C–V) characteristics of P3HT:PCBM devices of two different thicknesses are correlated with current density–voltage (J–V) characteristics. The rising portion of the C–V characteristics coincides with the exponential current density below the built-in voltage. The negative capacitance (NC) of these devices is a low frequency phenomenon and it occurs in trap-free space charge limited current (SCLC) regime. The onset frequencies of NC for devices with and without SWNTs also do not follow direct relation with effective mobility. The NC in thin devices has non-monotonic change with voltage for thin devices showing that interface state kinetics can be the reason for its occurrence. The NC of thick devices, on the other hand, increases monotonically with voltage showing that bulk properties dominate in these. Addition of SWNTs to these devices for efficiency improvement does not modify their built-in voltage. Also, the SWNTs do not affect the forward NC behaviour. However, the devices containing SWNTs show NC in reverse bias also which has different frequency dependence with voltage. The reverse bias NC is attributed to the large non-linear reverse current by charge injection into the additional energy levels introduced by SWNTs.     

Low Voltage Flash Memory Cells Using SiGe Quantum Dots for Enhancing F-N Tunneling

提出了一种用于半导体闪速存储器单元的新的Si/SiGe量子点/隧穿氧化层/多晶硅栅多层结构,该结构可以实现增强F-N隧穿的编程和擦除机制.模拟结果表明该结构具有高速和高可靠性的优点.测试结果表明该结构的工作电压比传统NAND结构的存储器单元降低了4V.采用该结构能够实现高速、低功耗和高可靠性的半导体闪速存储器.     

基于SiGe量子点实现增强F-N隧穿的低压闪速存储器

提出了一种用于半导体闪速存储器单元的新的Si/SiGe量子点/隧穿氧化层/多晶硅栅多层结构,该结构可以实现增强F-N隧穿的编程和擦除机制.模拟结果表明该结构具有高速和高可靠性的优点.测试结果表明该结构的工作电压比传统NAND结构的存储器单元降低了4V.采用该结构能够实现高速、低功耗和高可靠性的半导体闪速存储器.     

Simulated analysis for InGaP/GaAs heterostructure-emitter bipolar transistor with InGaAs/GaAs superlattice-base structure

A novel InGaP/GaAs heterostructure-emitter bipolar transistor (HEBT) with InGaAs/GaAs superlattice-base structure is proposed and demonstrated by two-dimensional analysis. As compared with the traditional HEBT, the studied superlattice-base device exhibits a higher collector current, a higher current gain of 246, and a lower base–emitter (B–E) turn-on voltage of 0.966 V at a current level of 1 μA, attributed to the increased charge storage of minority carriers in the InGaAs/GaAs superlattice-base region by tunneling behavior. The low turn-on voltage can reduce the operating voltage and collector–emitter offset voltage for low power consumption in circuit applications.     

Optimization of Si NC/P3HT Hybrid Solar Cells

Silicon nanocrystals (Si NCs) are shown to be an electron acceptor in hybrid solar cells combining Si NCs with poly(3‐hexylthiophene) (P3HT). The effects of annealing and different metal electrodes on Si NC/P3HT hybrid solar cells are studied in this paper. After annealing at 150 °C, Si NC/P3HT solar cells exhibit power conversion efficiencies as high as 1.47%. The hole mobility in the P3HT phase extracted from space‐charge‐limited current measurements of hole‐only devices increases from 2.48 × 10^?10 to 1.11 × 10^?9 m² V^?1 s^?1 after annealing, resulting in better transport in the solar cells. A quenching of the open‐circuit voltage and short‐circuit current is observed when high work function metals are deposited as the cathode on Si NC/P3HT hybrid devices.     

A novel P-channel nitride-trapping nonvolatile memory device with excellent reliability properties

A novel P-channel nitride trapping nonvolatile memory device is studied. The device uses a P/sup +/-poly gate to reduce gate injection during channel erase, and a relatively thick tunnel oxide (>5 nm) to prevent charge loss. The programming is carried out by low-power band-to-band tunneling induced hot-electron (BTBTHE) injection. For the erase, self-convergent channel erase is used to expel the electrons out of nitride. Experimental results show that this p-channel device is immune to read disturb due to the large potential barrier for hole tunneling. Excellent P/E cycling endurance and retention properties are demonstrated. This p-channel device shows potential for high-density NAND-type array application with high-programming throughput (>10 Mb/sec).     

Comprehensive study on a novel bidirectional tunnelingprogram/erase NOR-type (BiNOR) 3-D flash memory cell

In this paper a recently proposed bidirectional tunneling program/erase (P/E) NOR-type (BiNOR) flash memory is extensively investigated. With the designated localized p-well structure, uniform Fowler-Nordheim (FN) tunneling is first fulfilled for both program and erase operations in NOR-type array architecture to facilitate low power applications. The BiNOR flash memory guarantees excellent tunnel oxide reliability and is provided with fast random access capability. Furthermore, a three-dimensional (3D) current path in addition to the conventional two-dimensional (2D) conduction is proven to improve the read performance. The BiNOR flash memory is thus promising for low-power, high-speed, and high-reliability nonvolatile memory applications     

Measurement of ultralow gate tunneling currents using floating-gate integrator technique

We report for the first time that a gate tunneling current measurement sensitivity better than 3/spl times/10/sup -22/ A has been achieved by using a floating-gate integrator technique. The technique involves monitoring the charge change in the floating-gate integrated with an on-chip op-amp and an on-chip feedback capacitor. We used this technique to study the stress-induced leakage current (SILC) and its cycling dependence of 70 /spl Aring/ oxides in the direct tunneling region at oxide voltage as low as 1.9 V. The technique has been validated through correlation to direct measurement on MOSFET arrays and theoretical calculations. The measured SILC current is modeled with an Inelastic trap-assisted tunneling model.     

Memory characterization of SiGe quantum dot flash memories with HfO/sub 2/ and SiO/sub 2/ tunneling dielectrics

In this study, we have developed a SiGe dot floating-gate flash memory with high-K dielectric (HfO/sub 2/) tunneling oxide. Using SiGe dots and HfO/sub 2/ tunneling oxide, a low program/erase voltage can be achieved, along with good endurance and charge retention characteristics as compared to the SiGe dots with a SiO/sub 2/ tunneling oxide. We have also examined the impact of Ge concentration in the SiGe dots on charge retention time. This demonstrates that the SiGe dots with HfO/sub 2/ tunneling oxide can be used as the floating gate to replace SiGe dots with SiO/sub 2/ tunneling oxide and have a high potential for further scaling of floating gate memory devices.     

The relaxation phenomena of positive charges in thin gate oxideduring Fowler-Nordheim tunneling stress

In this study, new relaxation phenomena of positive charges in gate oxide with Fowler-Nordheim (FN) constant current injections have been investigated and characterized. It was found that the magnitudes of applied gate voltage shifts (ΔV_FN) during FN injections, after positive charges relaxed or discharged, have a logarithmic dependence with the relaxation time for both injection polarities. The results can derive the relationship of transient discharging currents, that flow through the oxides after removal of the stress voltage, with the relaxation time. We have shown that the current has a 1/f dependence for both injection polarities which can be also derived from the tunneling front model. The effects of oxide fields (lower than the necessary voltage for FN tunneling) and wafer temperatures (373 and 423 K) for the relaxation of positive charges are also studied     

Zn_(1-x)Cd_xSe/ZnS量子阱材料的共振遂穿特性研究

本文通过对共振隧穿电流密度随外加偏压及应力而变的依赖关系的理论研究,模拟了Zn1-xCdxSe/ZnS共振隧穿电流密度随外加偏压及应力的变化曲线.给出了等效电阻系数随外加偏压及应力而变的依赖关系,得出了介观压阻系数与外应力的变化符合线性关系的结论.这些结论为将机械信号转换为电学信号的介观效应器件的设计提供了理论指导.     

红外焦平面读出电路片上驱动电路设计

线列红外焦平面读出电路在正常工作时需要提供多路数字脉冲和多路直流偏置电压。本文基于0.5 μm CMOS工艺设计了一款驱动电路芯片,为电容负反馈放大型（CTIA）读出电路（ROIC）提供驱动信号。电路芯片采用带隙基准电路产生低噪声低温漂的直流偏置电压,采用数字逻辑电路生成CLK1,CLK2,RESET等八路数字脉冲。仿真及测试结果表明：驱动电路芯片输出的数字脉冲及偏置电压符合设计值,可驱动CTIA型线列红外焦平面读出电路稳定工作。     

Resonant tunneling through rare earth arsenide, semimetal quantum wells

Resonant tunneling is observed in double barrier resonant tunneling diodes (RTDs) with semi-metallic ErAs quantum wells. Magnetic field dependence distinguishes two different resonant channels. From the thickness dependence of the voltage for resonant tunneling the dispersion of the channels is found to be hole-like. The dispersion agrees well with the theory that identifies the two channels with m_j = ±1/2 and m_j = ±3/2, hole states.     

肖特基栅型共振隧穿晶体管的制作研究

已研制成了肖特基栅共振隧穿晶体管,在双势垒结构上蒸发铂金形成栅。通过调制准二维电子积累层的面积进而达到控制隧穿电流的目的。并对发射极正反接电压不同而出现的不同调制现象进行了分析。     

Polarity dependent gate tunneling currents in dual-gate CMOSFETs

Polarity dependence of the gate tunneling current in dual-gate CMOSFETs is studied over a gate oxide range of 2-6 nm. It is shown that, when measured in accumulation, the I_g versus V_g characteristics for the p⁺/pMOSFET are essentially identical to those for the n⁺/nMOSFET; however, when measured in inversion, the p⁺/pMOSFET exhibits much lower gate current for the same |V_g|. This polarity dependence is explained by the difference in the supply of the tunneling electrons. The carrier transport processes in p⁺/pMOSFET biased in inversion are discussed in detail. Three tunneling processes are considered: (1) valence band hole tunneling from the Si substrate; (2) valence band electron tunneling from the p⁺-polysilicon gate; and (3) conduction band electron tunneling from the p⁺-polysilicon gate. The results indicate that all three contribute to the gate tunneling current in an inverted p⁺/pMOSFET, with one of them dominating in a certain voltage range     

Asymmetrical current conduction across a 50 A Thick aluminium gallium nitride polarisation barrier

Rectification by a 50 Aring (5 nm) thick aluminium gallium nitride (AlGaN) polarisation barrier with maximum voltage swing of 27 V is demonstrated. In order to achieve a large voltage swing, the device is constructed with a 3000 Aring (300 nm) thick undoped gallium nitride (GaN) space charge layer adjacent to the barrier to enable a large voltage drop before the advent of impact ionisation breakdown. The spontaneous and piezoelectric polarisation discontinuities at the AlGaN/GaN interfaces determine the band profiles and the thermally assisted tunneling flux of electrons through the barrier. The 3.24 MV cm ^-1 electric field across the 50 Aring thick barrier at low bias enables efficient tunneling of electrons, despite the large effective electron mass of 0.19. The effective barrier seen by electrons changes from triangular to trapezoidal for one direction of bias and enhances the asymmetry effect. The demonstrated device characteristics show that wide band-gap polarisation barriers can potentially be used as the basic components of high-power microwave limiters