MRAM Cell Technology for Over 500-MHz SoC

This paper describes newly developed magnetic random access memory (MRAM) cell technology suitable for high-speed memory macros embedded in next-generation system LSIs: a two-transistor one-magnetic tunneling junction (2T1MTJ) cell structure, a write-line-inserted MTJ, and a 5T2MTJ cell structure. The 2T1MTJ cell structure makes it possible to significantly improve the write margin and accelerate the operating speed to 200 MHz. Its high compatibility with SRAM specifications and its wide write margin were confirmed by measuring 2T1MTJ MRAM test chips. Although the cell structure requires a small-writing-current MTJ, the current can be reduced to 1mA using the newly developed write-line-inserted MTJ. Further development to reduce the current down to 0.5 mA is required to obtain a cell area of 1.9 mum², which is smaller than the SRAM cell area, in the 0.13-mum CMOS process. The 5T2MTJ cell structure also enables random-access operation over 500 MHz because the sensing signal is amplified in each cell. Random access time of less than 2 ns can be achieved with SPICE simulation when the magnetic resistance is 5 kOmega and the magnetoresistive (MR) ratio is more than 70%     

Clocking design and analysis for a 600-MHz Alpha microprocessor

Design, analysis, and verification of the clock hierarchy on a 600 MHz Alpha microprocessor is presented. The clock hierarchy includes a gridded global clock, gridded major clocks, and many local clocks and local conditional clocks, which together improve performance and power at the cost of verification complexity. Performance is increased with a windowpane arrangement of global clock drivers for lowering skew and employing local clocks for time borrowing. Power is reduced by using major clocks and local conditional clocks. Complexity is managed by partitioning the analysis depending on the type of clock. Design and characterization of global and major clocks use both an AWEsim-based computer-aided design (CAD) tool and SPICE. Design verification of local clocks relies on SPICE along with a timing-based methodology CAD tool that includes data-dependent coupling, data-dependent gate loads, and resistance effects     

A 500-MHz CRT video driver using a linear array

A 500-MHz monolithic video driver integrated circuit (IC) for next-generation leading CRT (cathode ray tube) displays with 4 Mpixels or more is presented. The IC has a 320-mA output current amplifier, a video gain controller, a buffered input multiplexer, and a sample-and-hold bias circuit. Using new open-loop amplifier architecture and novel complementary-bipolar circuitry design, the driver IC with bandwidth f_B of 500 MHz is fabricated. It is economically implemented by a 2.5-μm commercially available linear array with a transistor f_T of 4 GHz. Its f _B/f_T ratio (a figure of merit of the driver circuit design) is three times larger than that of the latest conventional design. The driver IC and power transistors are intended to realize a high-output (50·V_p-p), wideband (300 MHz) CRT video amplifier characterized by good output voltage stability (<1%) without high-voltage output feedback for DC restoration     

DC-coupled IF stage design for a 900-MHz ISM receiver

This paper presents a DC-coupled 900-MHz ISM band RF front-end for a short-range wireless receiver. The front-end, fabricated in a 0.5-/spl mu/m CMOS process, is intended as a test vehicle to verify the proposed DC-coupled topology. In this topology, a low-frequency feedback circuit suppresses the DC offset and low-frequency noise at the mixer output. The DC-coupled topology is compared with traditional AC coupling. We show that there is a tradeoff between bandwidth and midband loss in a fully integrated AC-coupled system. The proposed DC-coupling technique does not impose this tradeoff. The DC-coupled topology was verified via simulation and measurements from the test vehicle.     

A 2.1-MHz crystal oscillator time base with a current consumptionunder 500 nA

A micropower crystal oscillator module for watch applications is presented. The integrated circuit is encapsulated with a 2.1-MHz crystal in a miniature vacuum package to reduce parasitic effects. The circuit comprises frequency tuning with a resolution of ±3 s/year [±0.1 parts per million (ppm)] and auxiliary circuits. A single output delivers a signal of 16 384 Hz with a frequency stability of ±2 ppm over the temperature range (-10 to 70°C). The oscillator core has two complementary active MOSFET's and amplitude stabilization in order to get both low power consumption and high stability. New coupling and biasing circuits between the oscillator and the dynamic frequency dividers allow to achieve a current consumption under 0.5 μA for a supply voltage between 1.8 and 3.5 V     

The architectures and design of a 20-MHz real-time DSP chip set

A set of four real-time 20-MHz digital signal processor (DSP) chips has been designed, fabricated, and tested. The chips include a 64-tap programmable FIR (finite impulse response) filter, a 1024-tap binary filter and template matcher, a 64-tap rank-value filter, and an eight-line 512-pixel video line delay. The circuits were implemented in a 1.5-μm CMOS process and are fully functional with a 20-MHz clock rate. The processors have reconfigurable windows to allow processing on both one-dimensional and two-dimensional data. The FIR filters can be used in multiprocessor systems to increase the window size and the data precision     

The design of a 3-V 900-MHz CMOS bandpass amplifier

A new bandpass amplifier which performs both functions of low-noise amplifier (LNA) and bandpass filter (BPF) is proposed for the application of 900-MHz RF front-end in wireless receivers. In the proposed amplifier, the positive-feedback Q-enhancement technique is used to overcome the low-gain low-Q characteristics of the CMOS tuned amplifier. The Miller-capacitance tuning scheme is used to compensate for the process variations of center frequency. Using the high-Q bandpass amplifier in the receivers, the conventional bulky off-chip filter is not required. An experimental chip fabricated by 0.8-μm N-well double-poly-double-metal CMOS technology occupies 2.6×2.0 mm² chip area. Under a 3 V supply voltage, the measured quality factor is tunable between 2.2 and 44. When the quality factor is tuned at Q=30, the measured center frequency of the amplifier is tunable between 869-893 MHz with power gain 17 dB, noise figure 6.0 dB, output 1 dB compression point at -30 dBm, third-order input intercept point at -14 dBm, and power dissipation 78 mW     

并行FDTD和IBM BlueGene/L巨型计算机结合求解电大尺寸的电磁问题

高性能巨型计算机的快速发展正在改变着人们在计算电磁学方面的一些传统观念,特别是IBM BlueGene/L巨型计算机的出现使计算电磁学所解决的问题尺寸和时间发生了巨大的变化.IBM BlueGene/L巨型计算机可以包括多达65,536处理器和 32 TB 内存,更重要的是由于它所使用的特殊体系结构使它在4000个处理器时时域有限差分程序的并行效率仍然在百分之九十左右.测试显示,在单个CPU速度接近的情况下,一台奔腾4计算机上运行五十二天的工作量在一个包含有4000个处理器的BlueGene/L巨型计算机上仅需10min左右.虽然普通的PC机群与单个处理器相比也能快速地求解相对大的问题,但是无论是使用千兆 Ethernet、Foundry、Myrinet或者Infiniband,普通PC机群的效率都会在处理其数量超过几十个的时候快速下降.为了验证并行时有预先差分程序的正确性,我们使用并行时域有限差分程序在巨型计算机IBM BlueGene/L上模拟一个144单元的对偶极化Vivaldi阵列的抛物面天线馈源.     

A single-chip 900-MHz spread-spectrum wireless transceiver in1-μm CMOS. I. Architecture and transmitter design

A single-chip transceiver for frequency-hopped code division multiple access (CDMA) in the 900 MHz industrial, scientific and medical (ISM) band is implemented in 1-μm CMOS. It combines a digital frequency synthesizer, a double quadrature upconverter, an integrated oscillator, and a power amplifier with variable output. Data modulates a carrier hopping at 20 kHz with quaternary frequency-shift keying (4-FSK). At an output power level of +3 dBm, the harmonics and spurious tones lie at -52 dBc or below. When active, the transmitter drains 100 mA from 3 V     

Analogue-computer model for a gallium-arsenide l.s.a. diode

A 1-dimensional analogue-computer model of an l.s.a. diode is described. The model yields new results concerning space-charge growth and decay. Investigations of the output power dependence on the load resistance are made. In addition to n0/f = constant, a constant n0R product is necessary for constant time dependence.     

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

This work describes a 500-MHz compiled eDRAM macro offered in a 90-nm logic-based process. The macro architecture is optimized for high bandwidth while enabling compilation in bank and data-word dimensions. A direct write scheme simultaneously improves random bank cycle time and row access time without signal loss. The benefits of ground sensing, reference cells, and bitline twisting was reviewed. A variable stage pipeline extends the macro bandwidth while offering flexibility in clock frequencies. The redundancy system is modified to support direct write and piping. Finally, BIST was enhanced to utilize electrically blown fuses, enabling one-touch test and repair. Hardware results was presented.     

Architecture and design of a portable protocol tester

The architecture and design of a new generation portable protocol tester that includes most of the capabilities of dedicated protocol test systems and all of the capabilities of commercial portable testers are discussed. The general tester environment and model of the system under test as viewed by the protocol tester are presented. A conceptual model of a protocol tester that captures its main functional requirements is proposed, and the basic performance requirement is presented. The design and structure of a protocol tester that provides the functional and performance capabilities described are outlined. The implementation utilizes custom VLSI multiprocessors and a special-purpose multiprocessing operating system to allow active and passive testing of more than one system simultaneously. The testing software on each processor is organized as a single process consisting of protocol and test entities with event occurrences being implemented as procedure calls aided by hardware subprocessors. All testing methodologies defined by the ISO, including the ferry method, can be implemented and standardized conformance test suites supported. Suggestions for future extensions to the design are offered     

Sensor-based design of a Delta parallel robot

This paper proposes a sensor-based design methodology in order to design a Delta robot with guaranteed accuracy performance for a dedicated sensor-based controller. This sensor-based design methodology takes into account the accuracy performance of the controller in the design process in order to find optimal geometric parameters of the robot. Three types of controllers are envisaged to be applied to the Delta robot, leading to three different optimal designs: leg-direction-based visual servoing, line-based visual servoing and image moment visual servoing. Based on these three controllers, positioning error models taking into account the error of observation coming from the camera are developed, and the controller singularities are analyzed. Then, design optimization problems are formulated in order to find the optimal geometric parameters and relevant parameters of the camera for the Delta robot for each type of controller. Prototypes of Delta robots have been manufactured based on the obtained optimum design parameters in order to test the performance of the pair {robot-controller}.     

Characteristics of a gallium-arsenide travelling-wave amplifier with Schottky-barrier contacts

Experimental results of the dependence of small-signal gain on bias voltages, applied to Schottky-barrier contacts which are r.f. input and output terminals of a gallium-arsenide travelling-wave amplifier are reported. In the optimum bias condition, a maximum net gain of 10 dB at 6.6 GHz in d.c. operation has been observed.     

Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallelcomparison and parity check functions

A 1.5-ns-access 500-MHz synonym hit RAM has been developed using 0.25-μm CMOS technology, which is the macro-cell to be used in microprocessor chips. We have proposed a virtual cache system with a synonym hit RAM, which achieves both high speed and large capacity because it solves the synonym problem that occurs with large-capacity cache systems. In this system, the RAM macro needs 576-bit parallel comparison and parity check functions. The configuration used achieves testability and low-power dissipation of large 576-bit data output. Moreover, the dynamic-NOR with a dynamic-inverter and sense-amplifier activation pulse generator are essential for reducing the comparison delay     

Analysis and design of a half-bridge parallel resonant converter

A half-bridge parallel resonant converter (PRC) is analyzed in detail for both continuous-conduction-mode and discontinuous-conduction-mode operations to provide more straightforward and easy-to-use design tools. Closed-form solutions are derived for the PRC operating under steady-state conditions. Theoretical results obtained are presented in the form of normalized design graphs. They could be directly utilized in designing a half-bridge PRC, having up to 2:1 input voltage variation. They do not necessitate converting the obtained ratings, depending on the input voltage and load variations, to check the worst case values. A design example of a 500 kHz 150 W offline switching power supply is given for both modes of operation, and it is implemented for experimental verification.<>     

Strategy for power-efficient design of parallel systems

Application studies in the areas of image- and video-processing indicate that between 50%-80% of the power cost in these systems is due to data storage and transfers. This is especially true for multiprocessor realizations because conventional parallelization methods ignore the power cost and focus only on performance. However, the power consumption also heavily depends on the way a system is parallelized. To reduce this dominant cost, we propose to address the system-level storage organization for the multidimensional signals as a first step in mapping these applications, before the parallelization or partitioning decisions (in particular, before the hardware/software (HW/SW) partitioning, which is traditionally done too early in the design trajectory). Our methodology is illustrated on a parallel quadtree-structured difference pulse-code modulation video codec     

A 80-MHz bandpass ΔΣ modulator for a 100-MHz IFreceiver

A fully differential fourth-order bandpass ΔΣ modulator is presented. The circuit is targeted for a 100-MHz GSM/WCDMA-multimode IF-receiver and operates at a sampling frequency of 80 MHz. It combines frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an intermediate frequency of 100 MHz to a digital intermediate frequency of 20 MHz. The modulator is based on a double-delay single-op amp switched-capacitor (SC) resonator structure which is well suited for low supply voltages. Furthermore, the center frequency of the topology is insensitive to different component nonidealities. The measured peak signal-to-noise ratio is 80 and 42 dB for 270 kHz (GSM) and 3.84-MHz (WCDMA) bandwidths, respectively. The circuit is implemented with a 0.35-μm CMOS technology and consumes 56 mW from a 3.0-V supply     

Architecture design for ATM statistical multiplexers

Both high-speed packet switches and statistical multiplexers are critical elements in the ATM (asynchronous transfer mode) network. Many switch architectures have been proposed and some of them have been built, but relatively fewer statistical multiplexer architectures have been investigated to date. It has been considered that multiplexers are a special kind of switches which can be implemented with similar approaches. The main function of a statistical multiplexer, however, is to concentrate traffic from a number of input ports to a comparatively smaller number of output ports; ‘switching’ in the sense that a cell must be delivered to a specific output port is often not required. This implies that the channel grouping design principle, in which more than one path is available for each virtual circuit connection, can be applied in the multiplexer. We show that this technique reduces the required buffer memory and increases the system performance significantly. The performances of three general approaches for implementing an ATM statistical multiplexer are studied through simulations with various bursty traffic assumptions. Based on the best performing approach (sharing output channels and buffers), we propose two architecture designs to implement a scalable statistical multiplexer that is modularly decomposed into many smaller multiplexers by using a novel grouping network.