共查询到20条相似文献,搜索用时 10 毫秒
1.
A new readout circuit involving two-step current-mode background suppression is studied for two-dimensional long wavelength infrared (2D LWIR) focal plane arrays. The simple pixel circuit has a very small skimming error of less than 0.3%, low noise characteristics for an adequate calibration range, and a long integration time of 2 ms. 相似文献
2.
A readout circuit involving a time-based pixel-level ADC is studied for two-dimensional long wavelength infrared focal plane arrays (2-D LWIR FPAs). The integration time of each pixel can be optimised individually and automatically. Using a time-based pixel-level ADC with two-step background suppression, the signal-to-noise ratio and dynamic range can be improved to 88.8 and 95.1 dB, respectively. 相似文献
3.
Infrared focal plane arrays (IRFPAs) are rapidly increasing in size. It is shown here that for large FPAs a considerable shift in the operating point occurs, which, if not reduced, introduces unacceptably large nonuniformity in the array response. This shift results because of the variable voltage drop across the HgCdTe active layer, due to its finite distributed resistance. A new analytical two-dimensional (2-D) model to estimate the operating point shift of individual detectors of long wavelength infrared (LWIR) HgCdTe focal plane array (FPA) is presented. Avoiding this operating point shift requires an optimized grid pattern 相似文献
4.
A novel capacitance scaling technique is proposed to reduce on-chip capacitor area using a dual-path self-biased current-mode filter. The capacitor multiplier is obtained by the relative ratio of charge-pump currents I/sub cp2//(I/sub cp2/-I/sub cp1/), rather than the scaling ratio I/sub cp2//I/sub cp1/. Compared with the original current-mode filter, the demonstrated loop filter of 250 pF capacitance is achieved with only 25 pF (90% die area saving), and the resistor area is reduced by 50% owing to reuse of the degenerated resistor R/sub G/. 相似文献
5.
Linear and switching techniques are currently adopted to implement current-mode power stages. Pulsewidth modulation (PWM) is usually employed with the switching technique for both industrial and audio applications. In this paper, the Sigma-Delta modulation is considered as an alternative to the PWM in devising a switching current-mode power stage suitable for audio amplification. The proposed modulator is analyzed and simulated. The whole system was realized on an experimental breadboard. The results carried out on the prototype are reported and discussed. The electrical characterization presents interesting features in terms of linearity, noise, and power efficiency. 相似文献
6.
针对复杂背景下红外弱小目标图像背景抑制难题,提出了一种基于曲面拟合的双向扩散滤波红外背景抑制新算法。采用高斯Facet模型拟合邻域图像曲面,采用综合方向导数梯度(IDDG)算子描述拟合图像的灰度特征,进而对双向扩散滤波进行改进,并将其与IDDG算子相结合,发展出了具有解析形式的改进的双向扩散滤波算法,给出了该算法关键参数的自适应选取方法。与传统的背景抑制算法相比,本文算法对图像灰度特征的描述更准确,并能据此在前向扩散和后向扩散之间自适应地切换,从而实现了在抑制背景杂波的同时增强目标能量,且能够克服传统算法处理椒盐噪声方面的缺陷。理论分析与仿真实验表明,本文算法对包含强纹理结构的复杂背景杂波具有良好的抑制作用和稳健的适应作用,对于信噪比为0.8的图像,可获得21.6的信噪比增益。 相似文献
7.
Weihsing Liu Shen-Iuan Liu Shui-Ken Wei 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2005,52(3):145-148
Compact, accurate and low-power analog CMOS circuits for current-mode division and pseudo-exponential function generation are presented, based on a new variable transresistance amplifier. Experimental results of the circuits fabricated in a 0.5-/spl mu/m 2P2M n-well CMOS process show better than 0.3% total harmonic distortion. Measured power is less than 0.22 mW at 100-MHz bandwidth and /spl plusmn/1.5-V supply voltages. 相似文献
8.
Serdar Menekay Rıza Can Tarcan Hakan Kuntman 《Analog Integrated Circuits and Signal Processing》2009,60(3):237-248
In this paper, a method to reduce the second order effects on the circuit performances caused by the small sized MOS transistors
is proposed. A current mode square-root circuit, a squarer/divider circuit and a multiplier/divider circuit are designed using
this method. Proposed circuits have been simulated with SPICE simulator using 0.35 μm CMOS technology parameters. The main
advantages of the proposed circuit are reduced errors of the output current function, a smaller area on the chip, possibility
of controlling the output current with the control voltage, operation at higher frequencies and more efficient power consumption.
As a result, it can be considered as a useful building block for IC designer. 相似文献
9.
A high injection, large dynamic range, stable detector bias, small area and low power consumption CMOS readout circuit with background current suppression and correlated double sampling (CDS) for a high-resolution infrared focal plane array applications is proposed. The detector bias error in this structure is less than 0.1 mV. The input resistance is ideally zero, which is important to obtain high injection efficiency. Unit-cell occupies 10 μm× 15 μm area and consumes less than 0.4 mW power. Charge storage... 相似文献
10.
A novel building block is described, termed FCS (floating current source), which may serve as class A output stage for CFAs (current-mode feedback amplifiers). It is capable of driving a grounded load with a bipolar signal, and yields a feedback current equal to the output current over a wide frequency range. Its possible range of application covers MOSFET amplifiers employed in analog signal processing and current-operated control systems. An internal interconnection converts the FCS into a CCII-. Another novel CCII- configuration employs a push-pull folded cascode and may serve as noninverting input stage for a standard amplifier configuration. Finally, a feedback-stabilized CCII- and a CFA are described, both employing the FCS as output stage. 相似文献
11.
提出了一种基于FPGA实现的新型2-D卷积器结构.该结构占用硬件资源少,外部带宽只需1pixels/clock.与传统的卷积器相比,不仅资源耗用减少95%以上,并且可以依据系统实时性要求调整吞吐率,带来了系统设计的灵活性.在Altera EP4SGX230KF40FPGA上实现结果表明,对于5×5大小的图像卷积,达到90Mpixels/s的吞吐率,满足大多数图像处理系统的实时性要求. 相似文献
12.
采用新的算法在对PDF417二维码进行解码时,将二维条码的单元模块宽度的求取和二维码码字的提取分割开来进行,很好地改进了传统的基于条码边缘图像的识别算法中由于各种原因出现的边缘检测不全、伪边缘干扰和边缘噪声污染所引起的码字丢失、错码、误码等问题.在同等条件下,可以比较精确地提取出图像码字.给出了实验结果. 相似文献
13.
Chun-Ming Chang Tai-Shan Liao Tai-Yung Yu En-Shang Lin Cheng-Hao Teng Chun-Li Hou 《International Journal of Electronics》2013,100(1):23-30
Two novel universal current-mode filters using unity-gain current followers (CFs) and voltage followers (VFs) are presented. The first one, employing three CFs, one VF, two grounded capacitors and two resistors, has two inputs and three outputs. The second one, employing only two CFs, one VF, two grounded capacitors and two resistors, has four inputs and a single output. Both proposed circuits oOEer the following advantageous features: universal current-mode filter realization from the same configuration, no requirements of component matching conditions, employment of two grounded capacitors ideal for integration, employment of two virtually grounded resistors good for voltage control, easy adjustment of ω0/Q and ω0 through separate virtually grounded resistors and low active and passive sensitivity performance. 相似文献
14.
S. Maheshwari 《International Journal of Electronics》2013,100(11):995-1003
This paper presents some new current mode first order all-pass sections with grounded components employing a modified current conveyor. The new circuits are ideal for current-mode cascading by possessing high output impedance. As an application of the circuits, a new quadrature oscillator is also given. The theory is validated through PSPICE simulation using 0.5μ CMOS parameters. 相似文献
15.
G. R. Reddy P. Sathyanarayana M. N. S. Swamy 《Circuits, Systems, and Signal Processing》1991,10(2):163-173
A few applications of a separable Hartley-like (CAS-CAS) transform in two-dimensional (2-D) signal processing is presented. The applications discussed include (i) the interpolation of signals, (ii) the computation of Hilbert transform, and (iii) the complex cepstrum computation. The computational advantage of the proposed methods over the algorithms using 2-D FFT are discussed. 相似文献
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17.
The three-dimensional (3D), wideband, bistatic ground penetrating radar (GPR) scatter response of rough, realistic ground is efficiently and accurately simulated using a hybrid high resolution 3D and large area two-dimensional (2D) finite difference time domain (FDTD) model. The 3D computation carefully models the transmitting and receiving antennas, while the 2D FDTD models wave propagation between the antennas and the scattering by the soil below them. The FDTD soil model considers realistic frequency dependent (dispersive) soil with Gaussian height variations. The modeling results are compared to experiments performed with the Geo-Centers, Inc., Newton, MA, commercially available GPR system used for mine detection. Despite the simplicity of the 2D model, the results of the simulation and the experiment agree quite well 相似文献
18.
Typically,infrared detectors require cryogenic cooling to limit dark current w hich is directly dependent on Auger generation-recombination mechanism and highly influential in Hg Cd Te-narrow band gap material.The Auger suppressed architectures have an advantage over conventional detectors allow ing operation at elevated temperatures200 K.Architecture w ith combination of exclusion and extraction heterojunctions has been proposed to low er Auger contribution.The paper presents a new long-w ave(≈10μm)infrared Hg Cd Te architecture w ith graded gap/doping interfaces and extra barrier located in exclusion heterojunction to suppress dark current for high operating temperature conditions.Proper barrier implementation reduces dark current by more than 20 A/cm2for room temperature operation. 相似文献
19.