Surface plasma treatments enabling low temperature direct bonding

Plasma activations for wafer bonding have been investigated for their ability to induce strong bonding even at low temperature treatment. Generally occurring with plasma treatment, revelation of many bonding defects (e.g. bubbles, voids,...) during (200–500°C) low temperature annealing is an important issue. In this paper, we will focus on bonding energy and quality enhancement obtained after reactive ion etch or microwave plasma treatment, under various atmospheres. Effects of a short plasma treatment on Si and SiO₂ surfaces are highlighted hereafter. Low-density layers around bonding interfaces have been characterized by interfacial X-ray reflectivity. Evolution of these layers through subsequent annealing are discussed to help in understanding mechanisms involved through such plasma treatments.     

Wafer-level bonding and direct electrical interconnection of stacked 3D MEMS by a hybrid low temperature process

The presented fabrication technology enables the direct integration of electrical interconnects during low temperature wafer bonding of stacked 3D MEMS and wafer-level packaging. The low temperature fabrication process is based on hydrophilic direct bonding of plasma activated Si/SiO₂ surfaces and the simultaneous interconnection of two metallization layers by eutectic bonding of ultra-thin AuSn connects. This hybrid wafer-level bonding and interconnection technology allows for the integration of metal interconnects and multiple materials in stacked MEMS devices. The process flow is successfully validated by fabricating test structures made out of a two wafer stack and featuring multiple ohmic electrical interconnects.     

Gold metallizations for eutectic bonding of silicon wafers

Gold eutectic bonding of silicon wafers is a good candidate for wafer level vacuum packaging of vibrating MEMS: in this paper we investigated several e-beam evaporated metallizations stacks including a titanium adhesion layer, an optional diffusion barrier (Ni or Pt) and a gold film for eutectic bonding on Si and SiO₂/Si wafers. Interdiffusion in the multilayers for annealing temperatures (380–430°C) larger than the Au–Si eutectic temperature (363°C) and times corresponding to a bonding process was characterized by RBS, roughness and resistivity measurements. Au/Pt/Ti and Au/Ti/SiO₂ were found to have the best characteristics for bonding. This was confirmed by bonding experiments.

     

Gold metallizations for eutectic bonding of silicon wafers

Gold eutectic bonding of silicon wafers is a good candidate for wafer level vacuum packaging of vibrating MEMS: in this paper we investigated several e-beam evaporated metallizations stacks including a titanium adhesion layer, an optional diffusion barrier (Ni or Pt) and a gold film for eutectic bonding on Si and SiO₂/Si wafers. Interdiffusion in the multilayers for annealing temperatures (380–430°C) larger than the Au–Si eutectic temperature (363°C) and times corresponding to a bonding process was characterized by RBS, roughness and resistivity measurements. Au/Pt/Ti and Au/Ti/SiO₂ were found to have the best characteristics for bonding. This was confirmed by bonding experiments.     

Low temperature Si/Si wafer direct bonding using a plasma activated method

Manufacturing and integration of micro-electro-mechanical systems (MEMS) devices and integrated circuits (ICs) by wafer bonding often generate problems caused by thermal properties of materials. This paper presents a low temperature wafer direct bonding process assisted by O₂ plasma. Silicon wafers were treated with wet chemical cleaning and subsequently activated by O₂ plasma in the etch element of a sputtering system. Then, two wafers were brought into contact in the bonder followed by annealing in N₂ atmosphere for several hours. An infrared imaging system was used to detect bonding defects and a razor blade test was carried out to determine surface energy. The bonding yield reaches 90%–95% and the achieved surface energy is 1.76 J/m² when the bonded wafers are annealed at 350 °C in N₂ atmosphere for 2 h. Void formation was systematically observed and elimination methods were proposed. The size and density of voids greatly depend on the annealing temperature. Short O₂ plasma treatment for 60 s can alleviate void formation and enhance surface energy. A pulling test reveals that the bonding strength is more than 11.0 MPa. This low temperature wafer direct bonding process provides an efficient and reliable method for 3D integration, system on chip, and MEMS packaging.     

Improved crystalline structure and H2S sensing performance of CuO-Au-SnO2 thin film using SiO2 additive concentration

In situ SiO₂-doped SnO₂ thin films were successfully prepared by liquid phase deposition. The influence of SiO₂ additive as an inhibitor on the surface morphology and the grain size for the thin film has been investigated. These results show that the morphology of SnO₂ film changes significantly by increasing the concentration of H₂SiF₆ solution which decreases the grain size of SnO₂. The stoichiometric analysis of Si content in the SnO₂ film prepared from various Si/Sn molar ratios has also been estimated. For the sensing performance of H₂S gas, the SiO₂-doped Cu-Au-SnO₂ sensor presents better sensitivity to H₂S gas compared with Cu-Au-SnO₂ sensor due to the fact that the distribution of SiO₂ particles in grain boundaries of nano-crystallines SnO₂ inhibited the grain growth (<6 nm) and formed a porous film. By increasing the Si/Sn molar ratio, the SiO₂-doped Cu-Au-SnO₂ gas sensors (Si/Sn = 0.5) exhibit a good sensitivity (S = 67), a short response time (t_90% < 3 s) and a good gas concentration characteristic (α = 0.6074). Consequently, the improvement of the nano-crystalline structures and high sensitivity for sensing films can be achieved by introducing SiO₂ additive into the SnO₂ film prepared by LPD method.     

Flexible integration of MEMS and IC for low-cost production of wireless sensor nodes

In this paper, we proposed a flexible process for size-free MEMS and IC integration with high efficiency for MEMS ubiquitous applications in wireless sensor network. In this approach, MEMS and IC can be fabricated individually by different wafers. MEMS and IC known-good-dies (KGD) are temporarily bonded onto carrier wafer with rapid and high-accurate self-alignment by using fine pattern of hydrophobic surface assembled monolayer and capillary force of H₂O; and then KGD are de-bonded from carrier wafer and transferred to target wafer by wafer level permanent bonding with plasma surface activation to reduce bonding temperature and load force. By applying above 2-step process, size of both wafer and chip could be flexible selected. Besides, CMOS processed wafer or silicon interposer can be used as the target wafer. This approach offers us excellent process flexibilities for low-cost production of wireless sensor nodes.     

Direct bonding with on-wafer metal interconnections

A low temperature direct bonding process with encapsulated metal interconnections was proposed. The process can be realized between silicon wafers or silicon and glass wafers. To establish well-insulated electric connection, sputtered aluminum film was patterned between a bottom thermal SiO₂ and a top PE-SiO₂; the consequential uneven wafer surface was planarized through a chemical mechanical polishing (CMP) step. Benefit from this smooth surface finish, direct bonding is achieved at room temperature, and a general yielding rate of more than 95% is obtained. Test results confirmed the reliability of the bonding. The main advantages of this new technology are its electric connectivity, low thermal stress and hermeticity. This process can be utilized for the packaging of micro electro mechanical system (MEMS) devices or the production of SOI wafers with pre-fabricated electrodes and wires.     

Simulation of SiO2-based piezoresistive microcantilevers

This article uses finite element design for optimization of piezoresistive Si covered SiO₂ microcantilevers. The maximum resistance changes were systematically investigated by varying piezoresistor geometries and doping concentration. Our simulation results show that both cantilever deflection displacement and ΔR/R change decrease when the thickness of piezoresistors increases; the highest sensitivity can be obtained when the piezoresistor length is approximately 2/5 of the SiO₂ cantilever length; increase of both Si width and leg width result in decrease in cantilever deflection and sensitivity; the sensitivity of cantilevers with lower doping concentrations is more significant than those with higher doping concentrations. Temperature control is critical for thin piezoresistor in lowering the S/N ratio and increasing the sensitivity.     

Micromachined SiO<Subscript>2</Subscript> microcantilever for high sensitive moisture sensor

Ultra-sensitive and selective moisture sensors are needed in various industries for processing control or environmental monitoring. As an outstanding sensor platform, surface-stress sensing microcantilevers have potential application in moisture detection. To enlarge the deflection of the microcantilever under surface stress induced by specific reactions, a new SiO₂ microcantilever is developed which features a much lower Young’s modulus than conventional Si or SiN_x microcantilevers. For comparing SiO₂ cantilever with Si cantilevers, a model of the cantilever sensor is given by using both analysis and simulation, resulting in good agreement with the experimental data. The results demonstrate the SiO₂ cantilever can achieve a much higher sensitivity than the Si cantilever. In order to fabricate this device, a new fabrication process using isotropic combined with anisotropic dry etching to release the SiO₂ microcantilever beam by ICP (Inductively Coupled Plasma) was developed and investigated. This new process not only obtains a high etch rate at 9.1 μm/min, but also provides good profile controllability, and a flexibility of device design. Attributed to the high sensitivity, a significant deflection amplitude of the surface modified SiO₂ microcantilever was observed upon exposure to 1% relative humidity. The SiO₂ cantilevers are promising for inexpensive and highly sensitive moisture detection.     

Device for oxide dots fabrication with copper wire as cathode probe

A device has been fabricated to perform large area local oxidation with copper wire (thickness 7 μm) as cathode probe. Ability of this device was studied, by silicon oxide (SiO₂) dots fabrication on silicon (Si) surface and patterning of model microorganism, Mycobacterium smegmatis on the predetermined positions (oxide dots) with preferable surface monolayer. Positive patterning of Mycobacterium smegmatis attained on the fabricated substrate due to the charge difference between SiO₂ dot and Si surface, which was confirmed by atomic force microscopy and scanning electron microscopy (SEM) analysis. This device shows possibilities of overcoming the inherent limitations of large area local oxidation by AFM.     

Micro-mixer device with deep channels in silicon using modified RIE process: fabrication,packaging and characterization

In the present work, silicon based micromixer microfluidic devices have been fabricated in silicon substrates of 2-inch diameter. These devices are of 2-input and 1-output port configuration bearing channel depth in the range 80–280 µm. Conventional reactive ion etching (RIE) process used in integrated circuit fabrication was modified to get reasonably high silicon etch rate (~1.2 µm/min). It was anticipated that devices with channel depth in excess of 150 µm would become weak and susceptible to breakage. For such devices, a bonded pair of silicon having a 0.5 µm SiO₂ at the bonded interface was used as the starting substrate. The processed silicon wafer bearing channels was anodically bonded to a Corning^® 7740 glass plate of identical size for fluid confinement. Through-holes for input/output ports were made either in Si substrate or in glass plate before carrying out anodic bonding. Micro-channels were characterized using stylus and optical profiler. Surface roughness of the channel was observed to increase with increasing channel depth. The devices were packaged in a polycarbonate housing and pressure drop versus flow rate measurements were carried out. Reynolds number and friction factor were calculated for devices with 82 µm deep channels. It was observed that up to 25 sccm of gas and 10 ml/min of liquid, the flow was laminar in nature. It is envisaged that using bonded silicon wafer pair and combination of RIE and wet etching, it is possible to get an etch stop at the SiO₂ layer of the bonded silicon interface with much smaller value of surface roughness rendering smooth channel surface.     

Post micromachining of MPW based CMOS–MEMS comb resonator and its mechanical and thermal characterization

In recent years micro electro mechanical system (MEMS) based micro resonant sensors have been given a lot of attention due to their potential as a platform for the development of many novel physical, chemical, and biological sensors. That is why this paper covers post processing of the structures fabricated through Multi-Project-Wafer using 0.35 µm MIMOS CMOS technology with particular focus on dry etching of Si and SiO₂ from the front side of CMOS–MEMS chip that is optimized using aluminum coated carrier wafer and achieved results are debris free as compared to photoresist coated carrier wafer. The device is etched through from the front side to avoid parasitic capacitances and squeeze film damping by keeping minimum size of the die. The etching of SiO₂ as well as deep Si etch-through using the same plasma etcher (SS110A Tegal) is successfully demonstrated in this work. Finally, after the successful post CMOS micromachining of the device, resonance frequency i.e. 8164 Hz and quality factor i.e. 51.34, is determined. The joule heating effect due to the passing of current through the central shuttle of the device is characterized. The maximum temperature close to the anchors of the comb resonator where the piezoresistors are located is determined through temperature coefficient of resistance measurement using PE-4RF type probe station and it is found to be 37.62 °C.     

A microtranslation table with scratch-drive actuators fabricated from silicon-on-insulator wafer

From a silicon-on-insulator (SOI) wafer, a microtranslation table with scratch-drive actuator (SDA) has been fabricated. The device Si layer of SOI wafer is etched to form the plate of SDA, which is partially connected to the handle Si substrate by the SiO₂ layer. Dicing the handle Si substrate, a microtranslation table with the SDA array has been fabricated. Placing the microtranslation table upside down on the other Si substrate on which a thin conductive film is patterned for the electrical connection, the microtranslation table is moved by the SDA without carrying a metal wire. The moving velocity of 45.5 μm/s has been obtained by applying the voltage of 120 V at the operating frequency of 500 Hz.     

Humidity sensing properties of mesoporous iron oxide/silica composite prepared via hydrothermal process

Mesoporous Fe₂O₃/SiO₂ composites with various Fe/Si molar ratios were synthesized via hydrothermal route and then studied as humidity sensor materials. The best result is obtained for the sample with a Fe/Si molar ratio of 0.5, which exhibits high humidity sensitivity, rapid response and recovery, small hysteresis and excellent linearity. The impedance of the sensor varies more than four orders of magnitude during the whole relative humidity (RH) from 11 to 95%. The response time and recovery time of the sensor is about 20 and 40 s, respectively. These results make our product a good candidate in fabricating high performance humidity sensors.     

Low-cost polymer microfluidic device for on-chip extraction of bacterial DNA

A polymer microfluidic device for on-chip extraction of bacterial DNA has been developed for molecular diagnostics. In order to manufacture a low-cost, disposable microchip, micropillar arrays of high surface-to-volume ratio (0.152 μm⁻¹) were constructed on polymethyl methacrylate (PMMA) by hot embossing with an electroformed Ni mold, and their surface was modified with SiO₂ and an organosilane compound in subsequent steps. To seal open microchannels, the organosilane layer on top plane of the micropillars was selectively removed through photocatalytic oxidation via TiO₂/UV treatment at room temperature. As a result, the underlying SiO₂ surface was exposed without deteriorating the organosilane layer coated on lateral surface of the micropillars that could serve as bacterial cell adhesion moiety. Afterwards, a plasma-treated PDMS substrate was bonded to the exposed SiO₂ surface, completing the device fabrication. To optimize manufacturing throughput and process integration, the whole fabrication process was performed at 6 inch wafer-level including polymer imprinting, organosilane coating, and bonding. Preparation of bacterial DNA was carried out with the fabricated PDMS/PMMA chip according to the following procedure: bacterial cell capture, washing, in situ lysis, and DNA elution. The polymer-based microchip presented here demonstrated similar performance to Glass/Si chip in terms of bacterial cell capture efficiency and polymerase chain reaction (PCR) compatibility.     

MEMS封装中全Cu3Sn焊点组织演变及剪切性能

对Cu/Sn+Sn/Cu结构进行了低温键合,在不同的键合时间下制备焊点,分析了键合时间对焊点界面组织演变的影响和全Cu₃Sn焊点制备过程中界面反应机理,对焊点的剪切性能进行了分析和研究。结果表明,随着键合时间的增加,Cu₆Sn₅逐渐变成扇贝状并不断长大。键合时间达到90 min时,Sn完全被消耗,继续增加键合时间,Cu₃Sn以Cu₆Sn₅的消耗为代价不断长大,最终全部转变成Cu₃Sn。随着加载速率的增加,全Cu₃Sn焊点的抗剪切强度值逐渐减小,焊点界面两侧Cu₃Sn界面处沿晶断裂占焊点断裂模式的比例越来越大,因为这种沿晶断裂的抗剪切能力较小,所以焊点的抗剪切强度随着加载速率的增加而下降。     

Etching processes for High Aspect Ratio Micro Systems Technology (HARMST)

 This paper reports on the development of a dry etching based HARMS-Technology which will offer the potential to manufacture micro-engines, micro-turbines, micro-sensors, micro-actuators, and electronic circuits onto a single silicon IC chip. This technology is based on the highly anisotropic and selective dry etching of Si-monocrystals. The suitability of reactive ion etching for the fabrication of micro electro mechanical systems (MEMS) has been evaluated by characterising the change of lateral dimensions vs. depth in etching deep structures in silicon. Fluorine, chlorine and bromine containing gases have provided the basis for this investigation. A conventional planar RIE (Reactive Ion Etching) reactor has been used, in some cases with magnetic field enhancement or ICP (Inductive Coupled Plasma) Source and low substrate temperature. For reactive ion etching based on Cl₂ or Cl₂/HBr plasma a slightly “positive” (top wider than bottom) slope is achieved when etching structures with a depth of several 10 μm, whereas a “negative” slope is obtained when etching with an SF₆/CCl₂F₂ based plasma. Pattern transfer with vertical walls is obtained for reactive ion etching based on SF₆ (with O₂ added) when maintaining the substrate at low temperature (in range ≈−100 °C). Further optimisation of plasma chemistries and reactive ion etching procedures should result in runouts in the order or 0.1 μm/100 μm depth in Si as well as in organic materials. Etching processes for HARMST is demonstrated in the realisation in Si microturbine. Axes or stators (nonmoving parts) are etched into the initial Si-wafer. The movable parts (rotors, beams, etc.) are prepared from electro-chemically etched Si-membranes with defined thicknesses that, all movable parts are created lithographically on the SiN_xO_y surface. This is followed by dry etching the mono-crystalline Si-membrane down to the SiN_xO_y sacrificial layer on the back side of the membrane by an RIE-process. The wafer with the movable parts is flipped onto the wafer with the already etched axis and then positioned and centred. The SiN_xO_y-sacrificial layer is then dissolved by a chemical wet or vapour etch process. Subsequent bonding with a Pyrex glass wafer seals the parts. Received: 30 October 1995/Accepted: 20 May 1996     

Low temperature wafer bonding for thin silicon film transfer

In this work, we investigate the low temperature (<200 °C) wafer bonding using wet chemical surface activation and we demonstrate high bonding strength sufficient to achieve the transfer of a thin silicon film of thickness less than 400 nm on top of another silicon wafer using spin-on-glass (SOG) film as an intermediate layer. The process developed is the first critical step that can enable three-dimensional (3D) integration and wafer level packaging of MEMS with electronic circuits.