航空机载设备中可编程逻辑器件的第三方测评方法研究

目前航空机载设备中可编程逻辑器件的应用领域和规模逐步扩大,在设备软件测评过程中软件测试人员面临着是否需要对FPGA/CPLD进行测试、如何测试的困惑。针对该疑问,本文对传统的软件测试方法和可编程逻辑器件验证方法进行分析,并借鉴军用产品软件第三方测评进入条件评估的思路,提出了能够较好地适应高安全性设备软件第三方测评的流程和方法,提高可编程逻辑器件测评的效率。     

ispLSI1032E器件及其应用

介绍了Lattice公司的大规模集成电路ispLSI1032E,它是一种在系统复杂可编程逻辑器件(CPLD),借助于EDA设计软件可以随时更改芯片的功能,而且不需要改动印制电路板(PCB)的结构,大大提高了系统设计的效率,并保证了设计的正确性。最后设计了基于该芯片的EDA教学实验系统。     

基于ISP技术的电子密码锁设计

介绍一种基于在系统可编程(ISP)技术和复杂可编程逻辑器件(CPLD)的新型电子密码锁的设计方法,阐述了其工作原理和软硬件设计.在硬件上,用Lattice公司的ISP大规模集成芯片对其外围电路进行集成,用1片CPLD实现了几十片分离元件才能实现的功能,几乎将整个系统下载于同一芯片中,实现了所谓的片上系统,从而大大简化了系统结构,增强了系统的可靠性和性价比.该密码锁特别适用于宾馆、办公大楼、仓库等人员经常变动的场所.     

Parameter Test of ROIC for IRFPA Based on Virtual Instrument Technology

The readout integrated circuit(ROIC)technology is one of the critical technologies in the research of an infrared focal plane array(IRFPA).Based on the virtual instrument technology,a system for parameter test of ROIC is developed for IRFPA.The complex programmable logic device(CPLD)is applied into the system to increase its flexibility,With high reliability and precision,along with the integrated software and hardware environment,the system can test all kinds of ROICs.     

基于ispLSI 1032E的数字式移相信号发生器

ispLSI 1032E是美国Lattice公司的一款在系统可编程(ISP)的高密度复杂可编程逻辑器件(CPLD).介绍了ispLSI 1032E的基本结构及其开发软件ispDesignEXPERT的应用.在此基础上,文中给出了基于ispLSI 1032E和直接数字频率合成(DDS)技术的数字式移相信号发生器的基本原理以及主要模块的设计.全数字化设计,使得该系统控制方便灵活.     

CPLD实现雷达自动增益控制的优化

复杂的可编程逻辑器件可以完成较大规模的组合逻辑电路设计，提高系统的集成化。本文介绍了复杂可编程逻辑器件和电路设计的一般流程，以及数字自动增益控制电路的组成和采用CPLD设计的实现。     

A hand vein recognition system based on DSP and CPLD

The hand vein recognition system based on digital signal processing (DSP) and complex programmable logic device (CPLD) is designed according to the requirements for equipment volume, accuracy and reaction speed. The overall structure and detailed implementation of the system hardware architecture are discussed in this paper. Moreover, the design philosophy and specific realization of system software as well as core algorithms are explored. The recognition system owns many good characteristics, such as high-degree integration, simple structure, flexible programming, convenient application and so on, which make it suitable for circumstances with high requirements for personal identification.     

CPLD在PD雷达信号模拟器中的应用研究

介绍了雷达信号模拟器的基本原理,基于Altera公司的FLEX10k10复杂可编程逻辑器件和JTAG技术实现一种在系统可编程的雷达信号模拟器,给出了实现方法和仿真结果.     

可编程逻辑器件在测控电路中的应用与设计

本文论述了在测控电路中使用可编程逻辑器件（ＰＬＤ）的意义与优越性；利用逻辑设计软件ＡＢＥＬ进行了大型变压器油温控制器通用阵列逻辑（ＧＡＬ）的设计与开发。     

CPLD在高精度超声波微位移及流量传感器测量系统中的应用

本文介绍了CPLD在一种新型超声波微位移传感器及流量测量系统设计中的应用.系统采用了高速复杂可编程逻辑器件CPLD技术,在CPLD芯片内设计有高速双端口RAM,控制采样时序逻辑及CPU接口、总线等电路,采样速率高达80MHz,采样深度1K字节,很好地解决了超声波微位移传感器软件算法对采样的要求,并可实现在线升级,大大提高了系统的整体性能.     

基于CPLD的CCD驱动时序的设计

CCD(电荷耦合器件)作为一种应用广泛的新型半导体光电器件,驱动时序电路的实现是其应用的关键问题。提出了基于CPLD(复杂可编程逻辑器件)实现CCD驱动电路的方法。选用Al-tera公司的MAX7000S系列CPLD作为硬件设计平台,运用VHDL对驱动时序电路进行了描述,并给出了部分程序,采用Altera公司的QUARTUSⅡ软件对所设计的驱动程序进行了仿真,并用数字示波器观察输出波形。测量和仿真的结果证明是可行的。     

基于Xilinx Zynq的物距测量系统设计与实现

为了对障碍物距离精确测量,基于最新Zedboard FPGA(现场可编程逻辑阵列)开发板,采用软硬件协同的设计方法,设计了障碍物距离测量系统的软硬件。系统为智能小车平台提供了完整的距离测量服务,测距范围能够达到2 cm⁴.5 m,精度可达0.2 cm。该设计包含从底层硬件电路设计、可编程逻辑IP(Intellectual Property)核设计、到Linux设备驱动的设计全部流程,对于在Zynq-7000 FPGA上软硬件从事开发的人员有一定的参考价值。     

A family of user-programmable peripherals with a functional unitarchitecture

A family of user-programmable peripherals, utilizing an integration strategy based on a programmable system device (PSD) concept, is described. Specifically, PSD is an efficient and highly configurable integration of high-density memory and LSI level logic blocks. The configurability is derived by providing programmable logic and programmable interconnect. PSDX is the first PSD family of programmable microcontroller peripherals; it integrates 256 kb to 1 Mb of EPROM, 16 kb of SRAM, a 28-input by 42-product term programmable logic device (PLD), and flexible I/O ports. This family is primarily targeted for embedded microcontroller applications. Using one PSD device it is possible to replace all the core peripherals in the system and, as a result, achieve a reduction in components, power dissipation, and overall system cost. The flexible architecture is achieved by providing 46 configuration options, which allows the PSD to interface with virtually any 8- or 16-b microcontroller. The integration is made possible by developing a special configurability and testability scheme. These parts are realized on a 1.2-μm CMOS EPROM process     

基于CPLD直接数字频率合成器的设计与仿真

介绍了直接数字频率合成器的工作原理,并利用Altera公司的FLEX10k复杂可编程逻辑器件(CPLD)给出了实现方法和仿真结果。     

基于VHDL语言的GF(28)上快速乘法器设计

基于有限域上多项式乘法理论,采用高层次设计方法,采用CPLD实现了GF(2^8)上8位快速乘法器,利用XILINX公司的Foundation Series3．1i集成设计环境完成了快速乘法器的VHDL源代码输入、功能仿真、布局与布线、时序仿真,并用XC9572PC84可编程逻辑芯片验证了该电路设计。该乘法器可以应用于RS(255,223)码编／译码器。     

一种视频字幕显示控制电路的设计

文章介绍了一种可远程接收的智能视频字幕显示控制电路。该电路采用MCS8051单片机作为控制核心,EPF7064S可编程逻辑器件产生所需时序及信号,W9952QP视频解码器产生视频信号。着重阐述了可编程逻辑器件内部逻辑电路的设计。     

基于CPLD的FPGA从并快速加载方案

提出了基于复杂可编程逻辑器件(CPLD)的现场可编程门阵列(FPGA)从并加载方案,及逻辑代码的实现过程,并给出仿真结果。该方案理论计算结果表明,当加载SPARTAN-6系列最高端的6SLX150T时,采用基于CPLD的从并加载方式,共需要加载时间为1.221 s,完全满足通信产品的快启动要求,具有较高的应用价值。     

Software-programmable digital pre-distortion on new generation FPGAs

In this paper we present a software programmable design flow that facilitates the implementation and integration of efficient digital pre-distortion (DPD) solutions on the leading-edge field programmable gate arrays, combining industry-standard embedded processors and programmable logic fabric into one chip. In addition to software programmability, another key contribution of this design flow is the flexible partitioning of functionality among the hardware and software components, depending on the complexity of the DPD parameter estimation algorithm in use. We have applied processor-specific optimizations to the software implementation and used Vivado high-level synthesis (HLS) tool as the design tool for the programmable logic. Furthermore, we have compared two different techniques for the integration of hardware and software components, where we have chosen the one with better area/latency trade-off. We present a comprehensive study reporting the DPD parameter update times when exploring the partitioning of the functionality among hardware and software. For low-complexity algorithms, we show that a software-only solution is applicable after carrying out the processor-specific software optimizations. For higher-complexity algorithms, we use Vivado HLS to accelerate the time-consuming blocks in the programmable logic, leading to a speed-up factor of up to 7× in the overall algorithm execution time. We present the performance results for two target devices. We also show that our accelerators use only a small portion of the programmable logic fabric on these devices and that a significant reduction of the system’s energy consumption can be obtained by leveraging the FPGA fabric.     

CCD光电测量信号的高速传输与控制设计

提出一种以电荷耦合器件（CCD）TCD1703C为感光元件的光电测量信号高速传输与控制设计方案。CPLD（EPM240）作为整个传输系统的控制核心,主要完成线阵CCD驱动时序的产生、高速A／D芯片（THS12082）的初始化与采样控制以及FIF0（SN74V273）缓存数据的复位配置;并通过USB2．0（CY7C68016A）接口的GPIF接口模式完成控制信号的发送以及实现采集系统与计算机之间的数据高速传输。描述了CPLD的逻辑控制软件设计流程及USB固件、软件设计方案及思想,通过多次软件和实验室测试仿真表明,该设计已满足多种光电测量的硬件数据采集卡要求。