Programmable CMOS switched-capacitor biquad using quasi-passivealgorithmic DAC's

This paper describes an electrically programmable switched-capacitor (SC) biquad using quasi-passive algorithmic digital-to-analog converters (DAC's). Since only two equal-valued capacitors are needed for programming each capacitance value, the proposed technique offers compact, cost-effective programmability when compared to traditional programming techniques employing binary-weighted capacitor-arrays (C-arrays). A demonstration prototype chip realized in a 1.2 μm CMOS double-metal double-poly technology, and which implements an 8 b programmable SC biquad giving a wide range of lowpass, bandpass and highpass filtering functions, occupies an active area of only 0.38 mm²     

Adequate SC model of op-amp with finite DC gain and bandwidth suitable for two-op-amp SC biquad analysis

An adequate model of a nonideal op-amp operating in a two-op-amp SC biquad is derived. The model leads to an equivalent SC circuit containing ideal components. Substitution of any op-amp in an SC biquad by its equivalent SC circuit allows the exact frequency response of the biquad to be found easily, taking into account the finite DC gain and bandwidth of op-amps.     

Testable switched-capacitor filters

A design-for-testability (DFT) methodology for switched-capacitor (SC) filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off- and online test. A programmable biquad is used for on-chip comparison of the transfer functions for every filter stage. Test area overhead consists of the programmable biquad, a set of switches, and a finite-sequential-machine (FSM) control part. The design and implementation of an example filter are included to assess the potential usefulness of this approach     

New monolithic switched-capacitor differentiators with good noiserejection

Inverting and noninverting switched-capacitor (SC) differentiators suitable for integrated-circuit implementation are proposed and analyzed. Their structures are simple, parasitic-free, and less sensitive to offset voltage and power-supply voltage changes. In addition, their fabrication process and operating clocks are fully compatible with conventional SC integrators. Noise analysis shows a good low-frequency noise-rejection capability. The high-frequency noise can be suppressed and does not overdrive the output of the SC differentiators. To demonstrate the application of the SC differentiators in the SC filter, a bandpass differentiator-type biquad is presented. Both the differentiators and the biquad have been fabricated and measured. The differentiation waveforms and the good consistency between the measured and the simulated circuit responses verify the correct operation of the SC differentiators     

Novel stray-insensitive SC bandpass filter

A new stray-insensitive SC bandpass filter derived from Moschytz's modified Tarmy-Ghausi configuration is described. Design equations and comparison with the Fleischer-Laker biquad are presented.     

CAD tools for the synthesis and layout of SC filters and networks

This paper describes two programs for the synthesis and layout generation of SC filters and networks. The first part of the paper describes a technology-independent synthesis and optimization program for SC filters. The program allows for the exact synthesis of cascaded SC biquad and SC ladder filters. Two performance measures related to sensitivity and noise are employed to estimate the performance of the synthesized circuits and to select optimum realizations. The same measures are used in a novel capacitance assignment procedure. The second part of the paper describes a flexible SC layout generator, which can be adapted to various design rules and floorplans by means of a technology file. Area efficient layout is generated by placing individual circuit elements rather than building blocks. Crosstalk between conductors is minimized by a router that distinguishes between different kinds of nodes.1. The scaling of the biquad circuit is dependent on the position of the biquad in the cascade.2. This may not seem to be overly important, since high-pass-type filters do not occur that often in practical applications. If one considers, however, that SCSYN is to be used as a general filter synthesis program, thenevery filter must be automatically realizable. In such an environment, a CAD program that can design all but one type of filter is either quite useless or very limited indeed.3. Note that an SC filter, in contrast to a digital filter, may contain delay-free loops.     

Mixed analog/digital, FIR/IIR realization of a linear-phase lowpassfilter

A 5 kHz linear-phase lowpass filter is implemented in a 2-μm BiCMOS technology as a combination of sigma-delta front-end, a digital shift register, a switched capacitor (SC) summer circuit with 50 input capacitors, and an SC biquad running at a 1 MHz clock. The measured group delay variation in the passband is less than 1 μs and the measured total harmonic distortion (THD) is -80 dB for an input sine wave amplitude of 0.7 V at 1 kHz. The circuit consumes 80 mW from ±5 V supply and measures 8.12 mm² without pads     

Improving the testability of switched-capacitor filters

A design-for-test methodology for SC filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off-and on-line tests. The approach uses a comparison (voting) mechanism to indicate whether or not two copies of a filter element (a biquad, for instance) have a similar response during their actual operation. The design and implementation of a few filter examples are included to assess the potential usefulness of this new approach.     

Improving the testability of switched-capacitor filters

A design-for-test methodology for SC filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off- and on-line tests. The approach uses a comparison (voting) mechanism to indicate whether or not two copies of a filter element (a biquad, for instance) have a similar response during their actual operation. The design and implementation of a few filter examples are included to assess the potential usefulness of this new approach.     

A 3 V 10 MHz pseudo-differential SC bandpass filter using gainenhancement replica amplifier

This paper describes the design strategy and implementation of a high frequency low voltage pseudo-differential SC filter which use opamps with gain enhancement replica amplifier. Experimental results of a biquad SC bandpass with a center frequency of 10 MHz and a Q of 10 are presented. The realized opamp has an open-loop unity-gain bandwidth of 850 MHz, a phase margin of about 62°, and a dc gain of 50 dB. The prototype filter dissipates 23 mW from a 3 V supply and occupies 0.3 mm ² in a 0.8 μm N-well single-poly, double-metal CMOS process     

Switched-capacitor biquad with low influence of finite gains

The letter describes a switched-capacitor (SC) biquad which exhibits less effect of the finite gains on the Q-factor and centre frequency than other known biquads of this type. The properties of the circuit have been established by extensive simulation studies using a symbolic analysis program.     

An economical digitally programmable switched programmable switched-capacitor biquad

An economical digitally programmable (DP) switched-capacitor (SC) biquad is proposed. It is stray-insensitive and can realize all of the five generic filters. Laboratory results agree with the theoretical ones.     

Low-voltage high-speed switched-capacitor circuits without voltage bootstrapper

Low-voltage high-speed switched-capacitor (SC) circuit design without using voltage bootstrapper is presented. The basic building block used for low-voltage SC circuit design is the auto-zeroed integrator (AZI), which can work at both low voltage and high sampling frequency. With this method, two low-voltage SC systems were successfully designed and implemented in 1.2-/spl mu/m CMOS technology. The first one is a fully differential SC bandpass biquad working at 1.5 V and 5.0-MHz clock frequency. The measured Q value is 8.0 at the center frequency of 833 kHz. The second one is a fully differential fourth-order bandpass /spl Delta//spl Sigma/ modulator that also works at 1.5 V and 5.0 MHz. Its measured third-order intermodulation is less than -78 dBc due to the low distortion characteristic of AZI. The measured signal-to-noise ratio of the modulator is 61 dB within the narrow band of 25 kHz centered at 1.25 MHz.     

A digital automatic tuning technique for high-order continuous-time filters

A digital automatic tuning technique for high-order continuous-time filters is proposed. Direct tuning of overall response is achieved without separating individual biquad sections, eliminating switches and their parasitics. Output phase of each biquad section is tuned to known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase detection. Frequency and quality factor tuning loops for each biquad are controlled digitally, providing more stable tuning by activating only one loop at a given time. The tuning system was verified by a prototype sixth-order bandpass filter which was fabricated in a conventional 0.5 /spl mu/m CMOS process with /spl plusmn/1.5 V power supply.     

Analysis of Errors in a Comparator-Based Switched-Capacitor Biquad Filter

Comparator-based switched-capacitor (CBSC) techniques have become popular in reducing power consumption and increasing the speed of data converters. This brief investigates the use of CBSC techniques for implementing a biquad filter. A CBSC implementation of a low-pass biquad is proposed, and the sources of error are analyzed. It is shown that implementing the lossy integrator as the last stage produces a lower offset voltage. The sensitivity of the biquad omega₀ and Q to the CBSC overshoot error is shown to be similar to that of the finite operational amplifier gain error in a switched-capacitor filter. Simulation results confirm the presented theory.     

A 15 MHz 20 mW BiCMOS switched-capacitor biquad operating with 150Ms/s sampling frequency

In order to increase the sampling frequency of SC filters the Precise Opamp Gain (POG) design approach is presented. It is based on the use of large bandwidth opamps with low but precise DC gain. The finite gain value is taken into account in the design phase. This produces capacitor values slightly different from those obtained with the standard design. A BiCMOS opamp with a nominal gain of 96 and unity-gain frequency of 650 MHz is used in a biquadratic lowpass filter with Q=2.8 designed with the POG approach. In a 1.2 μm BiCMOS technology, the prototype lowpass biquad operates with sampling frequency up to 150 Ms/s with 0.2 dB accuracy in the transfer function. For a sampling frequency of 150 Ms/s, the cut off frequency is 15 MHz. The dynamic range (for 1% THD) is 67 dB, and THD is less than -60 dB for a 1.5 Vpp 5 MHz input signal. The chip area is 1 mm², and the power consumption is 20 mW     

New universal filter using only current followers as active elements

A new universal current-mode (CM) biquad filter is presented which can realise all the five standard filter functions namely lowpass, bandpass, highpass, notch and allpass employing only unity-gain current followers (CF) as active elements. The workability of the proposed universal biquad, realised with CMOS unity-gain current followers, is established by SPICE simulations. The new circuit provides explicit CM outputs from high output impedance terminals and possesses a number of advantageous features all of which are not available simultaneously in any of the previously reported CF-based universal biquad filters.     

New voltage-model/current-mode universal biquad filter using unity-gain cells

A new universal biquad filter is presented which can realize all the five standard filter functions namely lowpass, bandpass, highpass, notch and allpass in voltage-mode (VM) as well as in current-mode (CM) employing only unity-gain cells (i.e. voltage followers and current followers) as active elements. Explicit VM/CM outputs are available from low output impedance terminals and high output impedance terminals, respectively. The workability of the proposed universal biquad, realized with CMOS unity-gain cells, is established by SPICE simulations.     

Low voltage VHF biquad section

A new biquad section based on pseudo-differential continuous-time transconductors for applications in low-voltage systems over the VHF band is presented. A prototype fourth-order 200 MHz bandpass filter with very high Q factor confirms the feasibility of the proposed biquad in very-high frequency applications such as IF bandpass sections of RF front-end circuits     

耦合二次节型开关电流带通滤波器的改进双线性设计

本文采用改进双线性变换，以一种新型双二次节为基块进行开关电流（ＳＩ）带通滤波器的设计。这种双二次节是用本文提出的双抽样方式ＳＩ改进型通用积分器构成的。文中介绍了耦合二次节型全极点及有限传输零点带通滤波器的设计方法。用该方法设计的ＳＩ滤波电路具有较好的高频特性，并能保持无源原型的低灵敏度特点。文中给出了Ｃｈｅｂｙｓｈｅｖ和Ｅｌｌｉｐｔｉｃ带通滤波器设计的实例。