High Dynamic Range Design for ΣΔM with Wide Input Ranges

A new design algorithm is introduced to improve the input ranges of Sigma-Delta Modulation (M). Modified digital error correction techniques are proposed and employed to carry out the wide range DAC of a modulator. This design algorithm includes the advantages from both single-bit M and multi-bit M. This paper utilizes a second order lowpass modulator as an explanatory example to demonstrate our design process as well as the performance improvement. The analytical results from a quasilinear model are described to offer a theoretical explanation of the system performance. This algorithm can also be applied to bandpass and MASH architectures.     

1 V All-MOS ΣΔ A/D Converters in the Log-domain

This paper presents novel low-voltage all-MOS analog circuit techniques for the synthesis of oversampling A/D converters. The new approach exploits the possibilities of Log-domain processing by using the MOSFET in subthreshold operation. Based on this strategy, a complete set of very low-voltage (down to 1 V) low-power (below 100 W) all-MOS basic building blocks is proposed. The resulting analog circuit techniques allow the integration of A/D converters for low-frequency (below 100 KHz) applications in digital CMOS technologies. Examples are given for a standard 0.35 m VLSI process.     

A 4 GHz ΔΣ Fractional-N Frequency Synthesizer

A 4 GHz fractional-N frequency synthesizer for wireless communications applications is implemented in a 0.35 m BiCMOS process. The synthesizer achieves a close-in phase noise of –66 dBc/Hz. The key building blocks are an ECL multiple-modulus prescaler employing the phase-switching architecture to minimize the power dissipation, a digital third-order MASH -modulator that controls the modulus of the prescaler, a very linear phase detector that enables the synthesizer to achieve a low close-in phase noise, and a chargepump providing a constant output current over a large output voltage range. The power dissipation of the synthesizer chip is 27.7 mW from a 2.7 V supply.     

Optimization and Design of a Low Power Switched Current A/D-ΣΔ-Modulator for Voice Band Applications

This paper presents a third order switched current -modulator. The modulator is optimized at the system level for minimum power consumption by careful design of the noise transfer function. A thorough noise analysis of the cascode type current copiers used to implement the modulator, together with a new methodology for evaluating the nonlinear settling behavior is presented. This leads to a new optimization methodology that minimize the power consumption in switched current circuits for given design parameters. The optimization methodology takes process variations into account. The modulator is implemented in a standard 2.4 m CMOS process only using MOS capacitors. For a power supply of 3.3 V the power consumption is approximately 2.5 mW when operating at a sampling rate of 600 kHz. Under these condition the peak SNR it measured to 74.5 dB with a signal band width of 5.5 kHz. Due to internal clamping in the integrators and proper scaling the modulator shows excellent stability properties. In order to compare the performance of the modulator presented in this paper to other -modulators two figure-of-merits (FOMs) are proposed. From these figure-of-merits it is found that the performance of the modulator presented in this paper is significantely higher than the perforamce of other switched current -modulators reported. Also, the figure-of-merits show that the performance is comparable to the performance of reported switched capacitor -modulators.     

A Direct Digital Synthesizer with Tunable Delta Sigma Modulator

In direct digital synthesizer (DDS) applications, the drawback of the conventional delta sigma () modulator structure is that its signal band is fixed. In the new architecture presented in this paper, the signal band of the modulator is tuned according to the DDS output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length second degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. Two DDSs with tunable 1-bit D/A converters (real and complex) were designed and implemented on a programmable logic device (PLD); experimental results show their desired operation and performance.     

A Difference Reference Voltage Buffer for ΔΣ-Converters

An open loop architecture for a reference voltage buffer in -converters is presented to achieve fast-settling, since the settling time of the references plays an important role in the global performance of sampled data converters. This design has been tested on a 2-1 -converter with an on-chip bandgap reference increasing the input related dynamic range up to 93.4 dB for a bandwidth of 99 kHz.     

Current Operational Amplifier (COA): CMOS Realization and Active Compensation

A methodology for analysis and synthesis of lowpass sigma-delta () converters is presented in this paper. This method permits the synthesis of modulators employing continuous-time filters from discrete-time topologies. The analysis method is based on the discretization of a continuous-time model and using a discrete simulator, which is more efficient than an analog simulator. In our analysis approach, the influence of the sample and hold block and non-idealities of the feedback DAC can be systematically modeled by discrete-time systems. Finally, a realistic design of a second-order modulator with a compensation of the non-ideal behavior of the DAC is given. Moreover, simulation results show a good agreement with the theoretical predictions.     

Digital Technique for Instability Detection and Saturation Recovery in High-Order SC ΣΔ Modulators

Stability and saturation recovery are a key concern in High-order Switched Capacitor (SC) modulators, since they are conditionally stable architectures.A novel digital technique, which allows to detect instability in the digital domain, a fast recover of high-order modulators from instability and guarantees a minimum of Signal-to-Noise Ratio (SNR) also when the architecture gets unstable, is proposed. This technique operates in two steps: first, the instability is detected in the digital domain and the system is recovered to a proper operation and then a digital post-processing is performed in order to achieve a residual SNR also in the instability condition.This strategy has been applied to a 6th-order SC bandpass modulator operating at 42.8 MHz and featuring 74 dB Dynamic Range (DR) in a 200 kHz bandwidth. The benchmark modulator has been integrated in a standard double-poly 0.35 m 3.3 V CMOS technology with five metal layers.     

Substrate Noise Simulation Techniques for Analog-Digital Mixed LSI Design

Crosstalk from digital to analog circuits can be causative of operation fails in analog-digital mixed LSIs. This paper describes modeling techniques and simulation strategies of the substrate coupling noise. A macroscopic substrate noise model that expresses the noise as a function of logic state transition frequencies among digital blocks is proposed. A simulation system based on the model is implemented in the mixed signal simulation environment, where performance degradation of the 2nd order ADC coupled to digital noise sources is clearly simulated. These results indicate that the proposed behavioral modeling approach allows practicable full chip substrate noise simulation measures.     

Geometric properties of nonlinear networks containing capacitor-only cutsets and/or inductor-only loops. Part I: Conservation laws

This paper is the first in a two part sequence which studies nonlinear networks, containing capacitor-only cutsets and/or inductor-only loops from the geometric coordinate-free point of view of differentiable manifolds. Given such a nonlinear networkN, with °₀ equal to the sum of the number of independent capacitor-only cutsets and the number of independent inductor-only loops, we establish the following: (i) circuit theoretic sufficient conditions to guarantee that the set ⁰, of equilibrium points is a ₀-dimensional submanifold of the state space ofN; (ii) circuit theoretic sufficient conditions for the condition thatN has ₀ independent conservation laws and hence that through each point of the state space ofN, there passes a codimension ₀ invariant submanifold ^* of the network dynamics; (iii) circuit theoretic sufficient conditions to guarantee that the manifolds ^* and ⁰ intersect transversely.This work was supported by the Natural Sciences and Engineering Research Council of Canada, under Grant Number A7113, and by scholarships from the Natural Sciences and Engineering Research Council of Canada and the Ontario Provincial Government.     

Digital Modulator with Bandpass Delta-Sigma Modulator

A digital quadrature modulator with a bandpass -modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f_s/4, –f_s/4 (f_s is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm² (0.13 m CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz (D/A converter full-scale output current 11.5 mA).     

Stabilization of third-order, single-stage Sigma-Delta modulators

The issue of stability of higher-order, single-stage Sigma-Delta () modulators is addressed using a method from nonlinear system theory. As a result, theoretical bounds for the quantizer input of the modulators are derived. A new method for stabilizing the modulators is then presented. It uses the quantizer input bound for possible instability detection. Upon detection of such a state, the highest-order integrator is cut off, effectively reducing the order of the modulator, and thus resulting in a stable system. The method is easily implemented and results in a very good signal-to-noise ratio (SNR) and fast return to normal operation compared to other stabilization methods.Financial support from General Secretariat for Research and Technology of Greece under contract PENED 95/1729.     

A 70-MHz Continuous-Time CMOS Band-Pass ΣΔ Modulator for GSM Receivers

A 70-MHz continuous-time CMOS band-pass modulator for GSM receivers is presented. Impulse-invariant-transformation is used to transform a discrete-time loop-filter transfer function into continuous-time. The continuous-time loop-filter is implemented using a transconductor-capacitor (G _m -C) filter. A latched-type comparator and a true-single-phase-clock (TSPC) D flip-flop are used as the quantizer of the modulator. Implemented in a MOSIS HP 0.5-m CMOS technology, the chip area is 857 m × 420 m, and the total power consumption is 39 mW. At a supply voltage of 2.5 V, the maximum SNDR is measured to be 42 dB, which corresponds to a resolution of 7 bits.     

Noise considerations for mixed‐signal RF IC transceivers

This paper discusses design tradeoffs for mixedsignal radio frequency integrated circuit (RF IC) transceivers for wireless applications in terms of noise, signal power, receiver linearity, and gain. During air wave transmission, the signal is corrupted by channel noise, adjacent interfering users, image signals, and multipath fading. Furthermore, the receiver corrupts the incoming signal due to RF circuit nonlinearity (intermodulation), electronic device noise, and digital switching noise. This tutorial paper gives an overview of the design tradeoffs needed to minimize RF noise in an integrated wireless transceiver. Fundamental device noise and the coupling of switching noise from digital circuits to sensitive analog sections and their impact on RF circuits such as frequency synthesizers are examined. Methods to minimize mixedsignal noise coupling and to model substrate noise effects are presented.     

A Reduced Delay Method for Improving the Performance of Sigma-Delta Analog-to-Digital Converters (ADC)

Excess loop delay in a continuous-time switched-current modulator causes a stability problem and degrades the modulator's dynamic range. This paper presents a simple and effective way to reduce the loop delay and improve the modulator's performance. The loop delay of the ADC is reduced by feeding the predicted next state to the comparator. With reduced loop delay, a larger loop gain is allowed without a stability problem, and hence, the dynamic range of the ADC is improved. A new circuit architecture to realize a second-order modulator with this method is also presented. From the simulation result, the new architecture shows a 6–10 dB improvement in dynamic range for a second-order modulator.     

Quality Determination for Gate Delay Fault Tests Considering Three-State Elements

Most industrial digital circuits contain three-state elements besides pure logic gates. This paper presents a gate delay fault simulator for combinational circuits that can handle three-state elements like bus drivers, transmission gates and pulled busses. The well known delay faults--slow-to-rise and slow-to-fall--are considered as well as delayed transitions from isolating signal state high impedance to binary states 0 and 1 and vice versa. The presented parallel delay fault simulator distinguishes between non-robust, robust and hazard free tests and determines the quality of a test. Experimental results for ISCAS85/89 benchmark circuits are presented as well as results for industrial circuits containing three-state elements.     

CMOS Switched-Capacitor Integrator

A switched-capacitor integrator is designed, and its performance is evaluated by computer simulation. The integrator is intended to operate in -modulation ADCs realized in basic CMOS technology. A circuit diagram of the integrator is shown. The results of a transient analysis are presented.     

Symmetry relations in multidimensional Fourier transform pairs

A relation between the types of symmetries that exist in signal and Fourier transform domain representations is derived for continuous as well as discrete domain signals. The symmetry is expressed by a set of parameters, and the relations derived in this paper will help to find the parameters of a symmetry in the signal or transform domain resulting from a given symmetry in the transform or signal domain respectively. A duality among the relations governing the conversion of the parameters of symmetry in the two domains is also brought to light. The application of the relations is illustrated by a number of two-dimensional examples.Notation R the set of real numbers - R ^m R × R × ... × R m-dimensional real vector space - continuous domain real vector - L {¦ – _i , i = 1,2,..., m} - m-dimensional frequency vector - W { – _i ,i=1,2,..., m} - m-dimensional normalized frequency vector - _P {¦ – _i , i=1,2,...,m} - g(ol) g (₁,₂,..., _m ) continuous domain signal - () ( _{1 2},..., _m )=G (j ₁,j ₂,..., j _m ) Fourier transform ofg (ol) - (A,b,,,) parameters ofT- symmetry - N the set of integers - N ^m N × N × ... × N m-dimensional integer vector spacem-dimensional lattice - h(n) h (n ₁,.,n _m ) discrete domain signal - H() Fourier transform ofh (n) - v ₁,v ₂,..., v_m m sample-direction and interval vectors - V (v ₁ v ₂ ...v _m ) sampling basis matrix - [x]^* complex conjugate ofx - detA determinant ofA - X {x¦ – x _i , i=1,2,..., m} - A ^–t [A ^–1] ^t ,t stands for transpose This work was supported in part by the Natural Sciences and Engineering Research Council of Canada under Grant A-7739 to M. N. S. Swamy and in part by Tennessee Technological University under its Faculty Research support program to P. K. Rajan.     

Performance engineering

Failure caused by poor performance renders a system just as useless as failure caused by functional errors, and can be even more expensive to correct. For many years, performance in software systems has been achieved through a fix-it-later approach, using optimisation and tuning techniques. Recent evidence shows that, with the increased use of highly complex, multi-layered, client/server, distributed architectures, these techniques cannot be relied on to deliver even the level of performance required during early operation when workloads are small, let alone over extended periods. This paper describes some of the ways in which performance can be engineered into systems — examples of how these techniques have been used in recent BT projects are included.     

Adaptive Correction of Errors in Residue Coupled MASH ΔΣ Modulators

MASH delta-sigma () modulators consist of a cascade of several lower order single-loop modulators. In an ideal cascade, the quantization error from all but the last stage are digitally canceled. The drawback with a cascaded design is the requirement of precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta-sigma stages. This paper presents a new, adaptive improvement to the residue coupled MASH delta sigma modulator. The adaptive corrections significantly reduce the sensitivity to analog imperfections. The result is a simple MASH delta-sigma modulator with high precision. Simulations of a 1-1 MASH circuit structure with errors and corrections are included to confirm the theory.