Incorporation of dielectric layers into the processing of III-nitride-based heterostructure field-effect transistors

Dielectric layers within III-nitride transistor technology can act either as passivation layers or as gate-dielectric layers. In this paper, we reflect on both issues and present novel approaches of dielectric schemes. In both cases, the elimination of surface traps or, more generally, of surface states is a key issue in obtaining improved device performance. As gate dielectrics, we introduced and investigated thermally and photoelectrochemically generated Al_xGa_2−xO₃, SiO₂, the combination of Al_xGa_2−xO₃ and SiO₂ (tandem-dielectric stack), and e-beam-deposited Al₂O₃. These dielectric layers serve simultaneously as a passivation layer. In addition, we introduced plasma-enhanced chemical-vapor deposition (PECVD)-deposited SiN_x for passivation. The results highlight the importance of passivation and the introduction of gate dielectrics and emphasize the relationship between surface states and improved direct-current (DC) performance. Backed by additional measurements, we proposed a different gateleakage mechanism for heterostructure field-effect transistor (HFET) and metal-oxide semiconductor heterostructure field-effect transistor (MOSHFET) devices.     

Potential of alternate dielectrics for single and composite film FET gate applications

The requirements for stable gate insulators and for dielectrics in MIOS non-volatile memory structures are formulated with the silicon FET technology in mind. A review of the literature on insulating layers pertinent to these applications is presented. It is shown that in addition to SiO₂, Si₃N₄ and Al₂O₃ only a small number of binary compounds deserves further consideration. To optimize dielectric behavior vitreous materials are be preferred. Since the properties of insulators are so strongly dependent on their crystallographic and chemical constitution the methods of film preparation determine to a considerable extend their characteristics.     

Role of ultrathin Al2O3 layer in organic/inorganic hybrid gate dielectrics for flexibility improvement of InGaZnO thin film transistors

We investigated flexible amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) on a polyimide (PI) substrate by using organic/inorganic hybrid gate dielectrics of poly-4vinyl phenol (PVP) and ultrathin Al₂O₃. IGZO TFTs were fabricated with hybrid PVP/Al₂O₃ gate dielectrics having Al₂O₃ layers of different nanoscale thicknesses, which were deposited by atomic layer deposition (ALD). The electrical characteristics of the TFTs with the organic/inorganic hybrid gate dielectrics were measured after cyclic bending up to 1,00,000 cycles at the bending radius of 10 mm. The ultrathin Al₂O₃ layer in the hybrid gate dielectrics improved the mechanical flexibility and protected the organic gate dielectric against damage during the sputter deposition of the IGZO layer. Finite elements method (FEM) simulations along with the structural characterization of the cyclically bent device showed the importance of optimizing the thickness of the Al₂O₃ layer in the hybrid gate dielectrics to obtain mechanically stable and flexible a-IGZO TFTs.     

Effects of radiation and charge trapping on the reliability of high-κ gate dielectrics

The radiation response and long term reliability of alternative gate dielectrics will play a critical role in determining the viability of these materials for use in future space applications. The total dose radiation responses of several near and long term alternative gate dielectrics to SiO₂ are discussed. Radiation results are presented for nitrided oxides, which show no change in interface trap density with dose and oxide trapped charge densities comparable to ultra thin thermal oxides. For aluminum oxide and hafnium oxide gate dielectric stacks, the density of oxide trapped charge is shown to depend strongly on the film thickness and processing conditions. The alternative gate dielectrics discussed here are shown to have effective trapping efficiencies that are up to 15 to 20 times larger than thermal SiO₂ of equivalent electrical thickness. A discussion of single event effects in devices and ICs is also provided. It is shown that some alternative gate dielectrics exhibit excellent tolerance to heavy ion induced gate dielectric breakdown. However, it is not yet known how irradiation with energetic particles will affect the long term reliability of MOS devices with high-κ gate dielectrics in a space environment.     

Effects of Metal Work Function and Contact Potential Difference on Electron Thermionic Emission in Contact Electrification

Triboelectric nanogenerator (TENG) is a direct measure of the surface charge density, thus providing a novel and powerful tool to study the essential mechanism of contact electrification (CE). A variety of TENGs including a Pt‐Al₂O₃ TENG, Au‐Al₂O₃ TENG, Ti‐Al₂O₃ TENG, Al‐Al₂O₃ TENG, and SiO₂‐Al₂O₃ TENG are prepared in this study. After introducing initial charges on the Al₂O₃ surface of the TENGs, the long‐term evolution of surface charge quantity is investigated at different temperatures. The results show that charge variation of all the TENGs is analogous to exponential decay and is in accord with the thermionic emission model, verifying the electron transfer dominated mechanism of CE. Additionally, it is explored for the first time that the potential barrier of materials can be regulated by changing the contacting metals or dielectrics. Regulation of the barrier at high temperatures fully excludes the influence of ions from moisture and functional groups, which further indicates the dominant role played by electron transfer in CE. Surface state models for explaining barrier regulation during CE for both metal–dielectric and dielectric–dielectric pairs are proposed. This study provides a new perspective of the exploration of CE, and a novel method for further increasing or rapidly eliminating electrification of charged materials.     

A Review on Dielectric Breakdown in Thin Dielectrics: Silicon Dioxide,High‐k,and Layered Dielectrics

Thin dielectric films are essential components of most micro‐ and nanoelectronic devices, and they have played a key role in the huge development that the semiconductor industry has experienced during the last 50 years. Guaranteeing the reliability of thin dielectric films has become more challenging, in light of strong demand from the market for improved performance in electronic devices. The degradation and breakdown of thin dielectrics under normal device operation has an enormous technological importance and thus it is widely investigated in traditional dielectrics (e.g., SiO₂, HfO₂, and Al₂O₃), and it should be further investigated in novel dielectric materials that might be used in future devices (e.g., layered dielectrics). Understanding not only the physical phenomena behind dielectric breakdown but also its statistics is crucial to ensure the reliability of modern and future electronic devices, and it can also be cleverly used for other applications, such as the fabrication of new‐concept resistive switching devices (e.g., nonvolatile memories and electronic synapses). Here, the fundamentals of the dielectric breakdown phenomenon in traditional and future thin dielectrics are revised. The physical phenomena that trigger the onset, structural damage, breakdown statistics, device reliability, technological implications, and perspectives are described.     

Towards metal electrode interface scavenging of rare-earth scandates: A Sc2O3 and Gd2O3 study

Amorphous Gd₂O₃ and Sc₂O₃ thin films were deposited on Si by high-pressure sputtering (HPS). In order to reduce the uncontrolled interfacial SiO_x growth, firstly a metallic film of Gd or Sc was sputtered in pure Ar plasma. Subsequently, they were in situ plasma oxidized in an Ar/O₂ atmosphere. For post-processing interfacial SiO_x thickness reduction, three different top metal electrodes were studied: platinum, aluminum and titanium. For both dielectrics, it was found that Pt did not react with the films, while Al reacted with them forming an aluminate-like interface and, finally, Ti was effective in scavenging the SiO₂ interface thickness without severely compromising gate dielectric leakage.     

Design of field-plate terminated 4H-SiC Schottky diodes using high-k dielectrics

Silicon carbide (SiC) field-plate terminated Schottky diodes using silicon dioxide (SiO₂) dielectric experience high electric field in the insulator and premature dielectric breakdown, attributed to the lower dielectric constant of the oxide. To alleviate this problem we explore the use of high-k dielectrics, silicon nitride (Si₃N₄) and sapphire (Al₂O₃), on 4H-SiC by numerical simulations using Medici. The simulation results show significant improvement in blocking voltages by as much as 30% and much lower electric field within the dielectrics. There is also a slight reduction in the specific-on resistance (R_sp-on) and a small increase in the forward current density due to the formation of an accumulation layer in SiC where the metal overlaps the dielectric. This effect is enhanced with increasing dielectric constant and decreasing dielectric thickness for a given dielectric.     

La2O3 gate dielectrics for AlGaN/GaN HEMT

The annealing temperature dependent electrical characteristics of La₂O₃ gate dielectrics for W gated AlGaN/GaN high electron mobility transistors (HEMTs) have been characterized. The threshold voltage (V_th) has been found to shift to positive direction with higher temperature annealing, exceeding those of Schottky HEMTs, presumably attributed to the presence of negative fixed charges at the interface between La₂O₃ and AlGaN layers. At a high temperature annealing over 500 °C, a high dielectric constant (k-value) of 27 has been achieved with poly-crystallization of the La₂O₃ film, which is useful to limit the reduction in gate capacitance. A high k-value for La₂O₃ gate dielectrics and the presence of negative charges at the interface are attractive for AlGaN/GaN HEMTs with low gate leakage and normally-off operation.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

Monte carlo study of mobility in Si devices with -based oxides

HfO₂-based high-κ dielectrics are among the most likely candidates to replace SiO₂ and the currently favoured oxinitride in the next generation of MOSFETs. High-κ materials allow the use of a thicker gate dielectric, maintaining the gate capacitance with reduced gate leakage. However, they lead to a fundamental mobility degradation due to the coupling of carriers to surface soft (low-energy) optical phonons. Comparing the vertical field dependence of the mobility for HfO₂ and SiO₂, the severe degradation in mobility in the presence of high-κ becomes evident. The introduction of a SiO₂ interfacial layer between the channel and the HfO₂ mitigates this degradation, by increasing the effective distance between the carriers and the SO phonons, thus decreasing the interaction strength, this does though lead to an increase in the equivalent oxide thickness (EOT) of the gate dielectric. The material of choice for the first commercial introduction of high-κ gate stacks is Hafnium Silicate (Si_xHf_1-xO₂). This alloy stands up better to the processing challenges and as a result suffers less from dielectric fluctuations. We show that as the fraction of Hf increases within the alloy, the inversion layer mobility is shown to decrease due to the corresponding decrease in the energy of the surface optical phonons and increase in the dielectric constant of the oxide.     

Functional modelling of non-volatile MOS memory devices

A simple first-order model of semiconductor non-volatile memory (NVM) devices is formulated. Conduction through the dielectric layers is as usual described by a dielectric resistivity, ρ but unlike the usual models which describe ρ by theoretical expressions, we have chosen to obtain ρ from experimental data on MIS capacitors. It turns out that the empirical relations for ρ for the thin-film dielectric materials of interest (SiO₂, Si₃N₄ and Al₂O₃) can be well approximated by simple exponential dependences on electric field. This is responsible for the success of the present approach, since it leads to a further simplification in the analytical solution for threshold voltage shifts (using the well-known equivalent circuits of dual-dielectric structures) of NVM devices. It is shown that a wide variety of NVM structures can be described in terms of two technology parameters, β₁ and β₂, which contain the geometry, materials, and relevant parameters describing the charging (write/erase) mechanisms. No adjustable parameters are present. Predictions of threshold voltage shifts are found to be in reasonable agreement with experiment. This model is well suited to facilitate computer-aided-design (CAD) of NVM devices. While it is recognized that this model ignores several physical details (e.g. bulk charging of dielectric layers) and is therefore not universal, it nevertheless can be readily used to predict the first-order circuit behaviour of most NVM devices, when β₁ and β₂ are properly obtained.     

Effects of polar functional groups and roughness topography of polymer gate dielectric layers on pentacene field-effect transistors

The present study analyzed the effects of the polar functional groups and rough topography of the gate dielectric layer on the characteristics of pentacene field-effect transistors. For this purpose, prior to deposition of the organic semiconductor, we introduced polar functional groups and created a rough topography onto the poly(methylmethacrylate)/Al₂O₃ gate dielectric layer using oxygen plasma treatment, and controlled the number of polar groups using an aging process. The mobility decrease observed after oxygen plasma treatment ranged from 0.2 to <0.01 cm²/V s and was related to the many polar functional groups and the rough topography of the gate dielectric, which formed localized trap states in the band gap and created disorder in the crystal structure. In addition, the electric dipole of the polar groups and the fixed interface charges induced a positive shift of the threshold voltage and an increase in the off-state current. After aging of the oxygen plasma-treated gate dielectrics, the reduced number of polar groups led to greatly enhanced charge mobility, a less positive shift of the threshold voltage, a lower off-state current, and lower activation energy compared to layers without aging. However, the mobility still remained lower than for layers without plasma treatment owing to the rough topography of the gate dielectric.     

Synchrotron study of the formation of nanoclusters in Al2O3/SiO x /Al2O3/SiO x /…/Si(100) multilayer nanostructures

Al₂O₃/SiO _x /Al₂O₃/SiO _x /…/Si(100) multilayer nanoperiodic structures (MNS) are studied by X-ray absorption near-edge structure spectroscopy (XANES). Experimental XANES spectroscopy spectra are obtained using synchrotron radiation. The formation of Si nanoclusters in the surface layers of the structures during their high-temperature annealing is observed. The structures featured intense size-dependent photoluminescence in the wavelength region near 800 nm. At the same time, it is shown that the formation of aluminum silicates is possible. The inversion effect of the intensity of the XANES spectra during the interaction of synchrotron radiation with MNSs is revealed.     

TCAD leakage current analysis of a 45 nm MOSFET structure with a high-<Emphasis Type="Italic">k</Emphasis> dielectric

The models of electrophysical effects builtinto Sentaurus TCAD have been tested. The models providing an adequate modeling of deep submicron high-k MOSFETs have been selected. The gate and drain leakage currents for 45 nm MOSFETs with polysilicon gate and SiO₂, SiO₂/HfO₂ and HfO₂ gate dielectrics have been calculated using TCAD. It has been shown that the replacement of the traditional SiO₂ gate oxide by an equivalent HfO₂ dielectric reduces the gate leakage current by several orders of magnitude due to the elimination of the impact of the tunneling effect. Besides, the threshold voltage, saturation drain current, mobility, transconductance, etc., degrade within a range of 10–20%.     

Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO₂ and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO₂/HfSiON with a U-shape nitrogen profile and a like-Si/SiO₂ interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO₂ and 1.2-nm HfSiON exhibits the lowest gate leakage.     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.     

Growth of lanthanum oxide films for application as a gate dielectric in CMOS technology

We have investigated properties of insulating lanthanum oxide (La₂O₃) films in connection with the replacement of silicon oxide (SiO₂) gate dielectrics in new generation of CMOS devices. The La₂O₃ layers were grown using metal organic chemical vapour deposition (MOCVD) at 500 °C. X-ray diffraction analysis revealed polycrystalline character of the films grown above 500 °C. The X-ray photoemission spectroscopy detected lanthanum carbonate as a principal impurity in the films and lanthanum silicate at the interface with silicon. Density of oxide charge, interface trap density, leakage currents and dielectric constant ( κ) were extracted from the C-V and I-V measurements. Electrical properties, in particular dielectric constant of the MOCVD grown La₂O₃ are discussed with regard to the film preparation conditions. The as grown film had κ11. Electrical measurements indicate possible presence of oxygen vacancies in oxide layer. The O₂-annealed La₂O₃ film had κ17.     

Improved performance by using TaON/SiO2 as dual tunnel layer in Charge-Trapping nonvolatile memory

Tunneling–barrier engineered stacks with different high-κ dielectrics are investigated by fabricating the stacked structures of Al/Al₂O₃/HfLaON/ (TaON/SiO₂)/Si and Al/Al₂O₃/HfLaON/ (HfON/SiO₂)/Si. As compared to the device with HfON/SiO₂ dual tunnel layer (DTL), the one with TaON/SiO₂ DTL shows larger memory window (3.85 V at ± 13 V/1 s), higher program/erase speeds (1.85 V/−2.00 V at ± 12 V/100 μs), better endurance (window narrowing rate of 5.7% after 10⁵ cycles). The main mechanisms involved lie in (1) the higher dielectric constant of TaON which induces high electric field in the SiO₂ layer, (2) the smaller conduction/valence-band offsets between TaON and the Si substrate, and (3) better interface quality with SiO₂. Furthermore, compared with SiO₂ single tunnel layer, better retention characteristics can be achieved for the TaON/SiO₂ DTL due to its larger thickness.