SET/CMOS混合器件研究

阐述了纳米线和纳米管电子器件的研究状况,对两种SET/CMOS基本混合器件的结构和应用以及仿真实现方法进行了论述。总结了SET/CMOS混合器件的特点。对纳米电子器件的发展进行了展望。     

基于单电子晶体管细胞神经网络的实现方法

基于单电子晶体管(SET)的I-V特性和CNN细胞单元的硬件结构原理，给出了三种基于SET的CNN硬件电路具体实现方法：一是基于SET的库仑振荡特性和CMOS数字电路的设计思想方法；二是根据细胞单元的等效结构分块实现方法；三是基于SET阵列的传输特性实现CNN方法，并重点阐述了后两种SET的CNN实现方法，分析了它们的优缺点。     

CMOS图像传感器中时间延迟积分的实现与优化

提出了一种在标准CMOS工艺下实现时间延迟积分(TDI)功能的电路结构,电路采用一面阵CMOS像素阵列,通过像素列曝光累积实现了TDI功能.详细分析了器件噪声和积分器噪声对电路的影响,提出了器件级噪声优化公式.电路采用SMIC 0.35 μm CMOS工艺实现.仿真结果表明,该电路能够实现TDI功能,运算放大器的等效输入噪声为36.1 μV,具有低噪声特性.     

基于SET/MOS混合结构的译码器电路的设计

基于SET的I-V特性以及SET与MOS管互补的特性,以MOS管的逻辑电路为设计思想,首先提出了一个SET/MOS混合结构的反相器,进而推出或非门电路,并最终实现了一个唯一地址译码器.通过SET和MOS管两者的混合构建的电路与纯SET实现的电路相比,电路的带负载能力增强;与纯MOS晶体管实现的电路相比,电路同样仅需要单电源供电,且元器件数目得到了减少,电路的静态功耗大大降低.仿真结果验证了电路设计的正确性.     

基于RTD与CMOS的新型数字电路设计

纳米电子器件RTD与CMOS电路结合,这种新型电路不仅保持了CMOS动态电路的所有优点,而且在工作速度、功耗、集成度以及电路噪声免疫性方面都得到了不同程度的改善和提高。文中对数字电路中比较典型的可编程逻辑门、全加器电路进行了设计与模拟,并在此基础上对4×4阵列纳米流水线乘法器进行了结构设计。同时讨论了在目前硅基RTD器件较低的PVCR值情况下实现相应电路的可行性。     

微光刻与微/纳米加工技术

介绍了微电子技术的关键工艺技术——微光刻与微/纳米加工技术,回顾了中国制版光刻与微/纳米加工技术的发展历程与现状,讨论了微光刻与微/纳米加工技术面临的挑战与需要解决的关键技术问题,并介绍了光学光刻分辨率增强技术、下一代光刻技术、可制造性设计技术、纳米结构图形加工技术与纳米CMOS器件研究等问题。近年来,中国科学院微电子研究所通过光学光刻系统的分辨率增强技术(RET),实现亚波长纳米结构图形的制造,并通过应用光学光刻系统和电子束光刻系统之间的匹配与混合光刻技术及纳米结构图形加工技术成功研制了20～50nm CMOS器件和100nm HEMT器件。     

CMOS工艺中横向双极型晶体管的直流与交流电学特性

在 CMOS工艺结构中,将位于阱中的 MOS 器件加适当的偏置,可以使其变为体内器件、以横向双极管的模式工作.本文利用 3μm P-well和 2μm N-well两种 CMOS工艺设计了这种横向双极器件,分析讨论了这种器件的工作原理和特点,并给出其典型的直流和交流参数的实验数据.这些分析和实验数据将有助于电路设计者了解和掌握该器件的电流、频率工作范围及特性,以便在CMOS电路中充分发挥其特长.     

基于量子元胞自动机的新型同或门结构设计北大核心

由于互补金属氧化物半导体（CMOS）器件尺寸的限制,量子元胞自动机（QCA）成为有望替代CMOS的新兴纳米器件。量子元胞自动机具有超低功耗、超高速度和高密度结构的潜在优势。提出了一种新型的同或门结构,在面积、延迟、复杂度及功耗方面相较于之前的结构均存在优势。所提出的新型同或门结构仅使用28个面积为0.02μm^2的QCA元胞,延迟仅为0.75个时钟周期。为了检验提出的设计在大型复杂QCA电路中的性能,实现了4,8和16位的奇偶校验器电路。模拟结果表明,所设计的电路性能各方面均优于先前的设计。     

一种基于单电子晶体管的二阶低通滤波器

在研完单电子晶体管(SET)I-V特性的基础上，阐明了一种分区处理法，设计了一个SET积分器电路。并据此实现了一个SET二阶低通滤波器，说明了该滤波器的工作条件、结构、性能、参数和特点。仿真结果表明，该滤波器的传输特性与采用其它两种方法描述SET I-V特性所构成的滤波器的传输特性有良好的一致性。文中所提出的SET I-V特性分区处理法，同样适用于SET在其它功能电路中的应用。     

基于忆阻器-CMOS晶体管的逻辑电路及其应用

针对传统组合逻辑电路存在的硬件资源利用率低和功耗高等问题,提出了一种基于忆阻器和CMOS晶体管的存算一体化组合逻辑电路设计方案。利用忆阻器存算一体、结构简单、与CMOS器件兼容等特性,减少了电路元器件数量。首先利用忆阻器的非易失性和阻变特性,设计忆阻与门、或门,结合CMOS晶体管实现与非门、或非门;然后,利用器件存算一体特性,提出了4R2T结构的异或门及同或门电路;最后,基于忆阻逻辑完备集设计了乘法器电路和图像加密电路,并采用LTspice验证电路功能正确性。结果表明,相比传统电路,所设计的乘法器电路元器件数量减少了50%,具有低功耗特性;所设计的图像加密电路具有良好的加密和解密效果,提升了运算效率。     

SET/CMOS hybrid process and multiband filtering circuits

We have developed an integration technology for the single electron transistor (SET)/CMOS hybrid systems. SET and CMOS transistors can be optimized without any possible degradation due to mixing dissimilar devices by adopting just one extra mask step for the separate gate oxidation (SGOX). We have confirmed that discrete devices show ideal characteristics required for the SET/CMOS hybrid systems. An SET shows obvious Coulomb oscillations with a 200-mV period and CMOS transistors show high voltage gain. Based on the hybrid process, new hybrid circuits, called periodic multiband filters, are proposed and successfully implemented. The new filter is designed to perform a filtering operation according to the periodic multiple blocking bands of which a period is originated from the SET. Such a novel function was implemented efficiently with a few transistors by making full use of the periodic nature of SET characteristics.     

SET logic driving capability and its enhancement in 3-D integrated SET–CMOS circuit

The driving capability of a single-electron transistor (SET) circuit is sensitive to the load and interconnects. We discuss about improving the performance of a SET logic in hybrid SET–CMOS circuit by parameter variation and circuit architecture along with its simulation results. With an intention of studying the SET logic drivability in a SET-only circuit, we examined a circuit composed of 2¹³ SET inverters with its interconnect effect in a 3-D CMOS IC. The schematic of the simulation is based on fabrication model of this large circuit along with interlayer and coupling capacitances of its metallization. The simulation results for delay, bandwidth and power validate the efficiency of a SET circuit.     

Enhanced write performance of a 64-mb phase-change random access memory

The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-/spl mu/m CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and multiple step-down pulse generator were employed, respectively. The read access time and SET write time are 68 ns and 180 ns, respectively.     

Low Temperature Characteristics of Schottky Barrier Single Electron and Single Hole Transistors

Schottky barrier single electron transistors (SB‐SETs) and Schottky barrier single hole transistors (SB‐SHTs) are fabricated on a 20‐nm thin silicon‐on‐insulator substrate incorporating e‐beam lithography and a conventional CMOS process technique. Erbium‐ and platinum‐silicide are used as the source and drain material for the SB‐SET and SB‐SHT, respectively. The manufactured SB‐SET and SB‐SHT show typical transistor behavior at room temperature with a high drive current of 550 μA/μm and ?376 μA/μm, respectively. At 7 K, these devices show SET and SHT characteristics. For the SB‐SHT case, the oscillation period is 0.22 V, and the estimated quantum dot size is 16.8 nm. The transconductance is 0.05 μS and 1.2 μS for the SB‐SET and SB‐SHT, respectively. In the SB‐SET and SB‐SHT, a high transconductance can be easily achieved as the silicided electrode eliminates a parasitic resistance. Moreover, the SB‐SET and SB‐SHT can be operated as a conventional field‐effect transistor (FET) and SET/SHT depending on the bias conditions, which is very promising for SET/FET hybrid applications. This work is the first report on the successful operations of SET/SHT in Schottky barrier devices.     

Single event transient pulse width measurement of 65-nm bulk CMOS circuits

Heavy ion results of a 65-nm CMOS SET pulse width testchip are given. The influences of device threshold voltage, temperature and well separation on pulse width are discussed. Experimental data implied that the low device threshold, high temperature and well speraration would contribute to wider SET. The multi-peak phenomenon in the distribution of SET pulse width was first observed and its dependence on various factors is also discussed.     

Negative bias temperature instability induced single event transient pulse narrowing and broadening

The effect of negative bias temperature instability(NBTI) on a single event transient(SET) has been studied in a 130 nm bulk silicon CMOS process based on 3D TCAD device simulations.The investigation shows that NBTI can result in the pulse width and amplitude of SET narrowing when the heavy ion hits the PMOS in the high-input inverter;but NBTI can result in the pulse width and amplitude of SET broadening when the heavy ion hits the NMOS in the low-input inverter.Based on this study,for the first time we ...     

NBTI效应导致SET脉冲在产生与传播过程中的展宽

本文研究了负偏置温度不稳定性(NBTI)对单粒子瞬态(SET)脉冲产生与传播过程的影响.研究结果表明:NBTI能够导致SET脉冲在产生与传播的过程中随时间而不断展宽.本文还基于工艺计算机辅助设计模拟软件(TCAD)进行器件模拟,提出了一种在130nm体硅工艺下,计算SET脉冲宽度的解析模型,并结合NBTI阈值电压退化的...     

纳米电子器件及其集成

对基于Top-Down加工技术的纳米电子器件如：单电子器件、共振器件、分子电子器件等的研究现状、面临的主要挑战等进行了讨论. 采用CMOS兼容的工艺成功地研制出单电子器件，观察到明显的库仑阻塞效应；在半绝缘GaAs衬底上制作了AlAs/GaAs/In0.1Ga0.9As/GaAs/AlAs双势垒共振隧穿二极管,采用环型集电极和薄势垒结构研制的共振隧穿器件，在室温下测得其峰谷电流比高达13.98，峰电流密度大于89kA/cm2；概述了交叉阵列的分子存储器的研究进展.