两种氧化方法对InSb探测器钝化效果的研究

比较了阳极氧化和Photo-CVD氧化两种钝化方式制备InSb 探测器的性能,结果表明前者反偏漏电流小,击穿电压是后者的5倍,背景光电流和零偏阻抗基本相同。C-V测试结果:前者固定表面电荷密度为21011 cm-2,后者为1.51011 cm-2。两种氧化方法制备的器件经过高温高湿老化试验后,在反偏1 V时,阳极氧化器件漏电比变化率只有Photo-CVD氧化器件的50%,二者背景光电流均有增加,可能与器件光敏面扩大有关。阳极氧化钝化方法,工艺过程易于控制,钝化效果一致性较好,器件的界面状态更加稳定。     

光伏型InSb红外探测器表面的阳极氧化

测量了阳极氧化InSb MOS结构的界面特性以及光照对经阳极氧化保护的光伏型InSb红外探测器性能的影响。实验指出,对于p-n结器件,光照使短路电流增加,器件阻抗的降低是由于光敏面扩大,而对于n~ -p结器件,短路电流不随光照变化,但I-V曲线出现了明显的软击穿,器件阻抗的降低来自于结区二边电子的隧道穿透。文章对器件性能蜕变的机制以及克服的方法进行了分析与讨论。     

InSb阳极氧化膜组分和形貌分析

利用X射线光电子能谱（XPS）分析了不同氧化条件下InSb阳极氧化膜的组成成分以及各种组分纵向分布;用观察在扫描电子显微镜（SEM）不同氧化条件下InSb阳极氧化膜的微观形貌。研究了InSb阳极氧化膜的化学和结构特性及其对自身电学性能的影响。为提高InSb阳极氧化膜制备工艺水平提供了有效参考。     

长波碲镉汞材料阳极氧化膜/ZnS界面的电学特性参数

通过碲镉汞阳极氧化膜和磁控溅射ZnS膜,结合HgCdTe器件工艺,成功制备了以阳极氧化膜和磁控溅射ZnS双层钝化膜为绝缘层的“长波弱P”型HgCdTe MIS器件.通过对器件的C-V特性实验分析,获得了长波HgCdTe材料的阳极氧化膜/ZnS界面电学特性参数.并通过获得的界面参数,计算了阳极氧化和ZnS的双层钝化膜的表面复合速度.并对MIS器件的变温C-V特性进行了实验和分析.     

电子回旋共振氮等离子体氧化后退火对4H-Si CMOS电容TDDB特性的影响

SiC MOS器件氧化膜可靠性是SiC器件研究中的重要方面。本文对4H-SiC MOS结构进行电子回旋共振(ECR)氮等离子体氧化后退火工艺处理,采用阶跃电流经时击穿以及XPS分析的方法对其氧化膜稳定性进行了电学以及物理性质方面上的分析。经分析氮等离子体处理8min的样品击穿时间和单位面积击穿电荷量都有了明显提高,并且早期失效比率有了明显降低。实验结果表明,经过适当时间的处理,ECR氮等离子体氧化后退火工艺可以有效地降低界面缺陷的密度,提高界面处激活能,从而提高绝缘膜耐受电流应力的能力。     

表面预处理对InSb钝化层界面的影响

本文介绍了采用不同的方法对InSb表面进行表面预处理,来改善InSb钝化膜层的电学性能。通过对InSb MIS结构进行C-V测试来评价不同方法预处理制备的钝化结构的电学特性。结果表明等离子预处理能明显改善InSb衬底和钝化层之间的界面性能,尤其是选用N2O等离子预处理InSb衬底表面,在控制界面陷阱和减少钝化层固定电荷方面,效果更明显,有利于提高InSb红外器件的可靠性。     

Hg_(1-x)Cd_xTe的等离子阳极氧化

本文叙述一种在Hg_(1-x)Cd_xTe上形成氧化薄膜的新的等离子氧化工艺。测量了用自身氧化膜形成的金属——绝缘层——半导体器件的电学特性。这种氧化膜有相当低的固定表面电荷,其密度为(1—3)×10~(11)电子/厘米~2,优于用化学阳极氧化所生长的氧化膜。由300埃自身氧化膜和200埃硫化锌组合而成的绝缘层,对n型和p型衬底所测量的平带电压分别是-0.5伏和-2.5伏。对于铟栅极结构所测量的功函数差是-1.7伏。氧化物的相对介电常数是13。电容——电压和电流——电压特性表明这种界面很适于光导、光伏二极管和电荷耦合器件等的制备工艺。     

SiC MOS界面氮等离子体改性及电学特性评价

降低SiO2/SiC界面态密度是SiCMOS器件研究中的关键技术问题。采用氮等离子体处理SiO2/SiC界面,制作MOS电容后通过I-V、C-V测试进行氧化膜可靠性及界面特性评价,获得的氧化膜击穿场强约为9.96MV/cm,SiO2/SiC势垒高度2.70eV,同时在费米能级附近SiO2/SiC的界面态密度低减至2.27×1012cm-2eV。实验结果表明,氮等离子体处理SiO2/SiC界面后能有效降低界面态密度,改善MOS界面特性。     

SiC掺氯热氧化技术与SiC MOS电容偏压温度不稳定性

偏压温度不稳定性(BTI)是影响SiC MOS器件性能的关键因素。提出了一种制备SiC MOS电容的新工艺，即在SiC干氧氧化气氛中掺入氯化氢(HCl),并对比了不同HCl与O₂体积流量比对SiC MOS电容电学性能的影响。结果表明，该工艺有效地改善了SiC MOS电容的栅氧击穿特性，降低了界面态密度，提升了平带电压稳定性。二次离子质谱(SIMS)和X射线光电子能谱(XPS)测试分析表明，掺氯热氧化技术能够有效消除界面缺陷。进一步分析表明，SiC掺氯热氧化技术能够降低可动离子面密度和氧化层陷阱电荷密度，能够有效改善器件的BTI特性。     

三栅FET的总剂量辐射效应研究

通过对赝MOS进行不同剂量的辐射,得到不同辐射条件下赝MOS器件的I-V特性曲线,并通过中带电压法进行分析,得出在不同辐射下SOI材料的埋氧层中产生的陷阱电荷密度和界面态电荷密度参数。采用这些参数并结合Altal三维器件模拟软件模拟了硅鳍(FIN)宽度不同的三栅FET器件的总剂量辐射效应,分析陷阱电荷在埋氧层的积累和鳍宽对器件电学特性的影响。     

Radiation damage of thermally oxidized MOS capacitors

The influence of preparation parameters and the effect of X-rays (150 keV, 10⁴rad (Si)) on oxide charge Qoxand interface state density Nssin thermally oxidized MOS varactors under different biasing conditions during irradiation has been investigated. The interface state density was determined by the ac conductance method before and after irradiation. The oxide charge has been evaluated with regard to the charge Qssof the interface states. Qsshas beeu discussed with the aid of simple models concerning the energetic distribution and recharge character of the interface states. The results indicate a similar dependence between flatband voltage, interface state density, and normalized oxide charge density as a function of gate bias during irradiation. Furthermore, the so-called "oxidation triangle" of oxide charge before irradiation exists for interface states as well. Calculations on the basis of the Schottky barrier model of the irradiated MOS structure show that the radiation-induced charge exists at both interfaces in the oxide layer. Radiation tolerance of the MOS capacitors as a function of technological parameters is discussed.     

氮钝化SiC MOS界面特性的Gray-Brown法研究

降低SiO2/SiC界面态密度,尤其是SiC导带附近的界面态密度,是SiC MOS器件研究中的关键技术问题。采用氮等离子体钝化处理SiO2/SiC界面,制作成MOS电容后通过I-V和低温C-V测试进行氧化膜击穿特性及界面特性评价。氧化膜击穿电场为9.92MV/cm,SiO2与SiC之间的势垒高度为2.69eV。使用Gray-Brown法结合Hi-Lo法分析C-V曲线,获得了距导带底EC0.05～0.6eV范围内的界面态分布,其中距EC0.2eV处的界面态密度降低至1.33×1012cm-2eV-1。实验结果表明,氮等离子体处理能有效降低4H-SiC导带附近的界面态密度,改善界面特性。     

MOS栅氧的界面特性和辐照特性研究

通过交流电导法,对经过不同时间N₂O快速热处理(RTP)的MOS电容进行界面特性和辐照特性研究。通过电导电压曲线,分析N₂O RTP对Si-SiO₂界面陷阱电荷和氧化物陷阱电荷造成的影响。结论表明,MOS电容的Si-SiO₂界面陷阱密度随N₂O快速热处理时间先增加再降低;零偏压总剂量辐照使氧化层陷阱电荷显著增加,而Si-SiO₂界面陷阱电荷轻微减少。     

Effect of NO annealing conditions on electrical characteristics of n-type 4H-SiC MOS capacitors

This paper presents the results of the effect of NO annealing temperature and annealing time on the interfacial properties of n-type 4H-SiC MOS capacitors. The interface trap density measured by conductance technique at 330°C decreases as NO annealing temperature increases from 930°C to 1130° and annealing time is extended from 30 min. to 180 min. The changes in effective oxide charge between room temperature and high temperature are calculated and used to compare different n-type 4H-SiC MOS capacitors. Higher NO annealing temperature and longer NO annealing time decrease the change in effective oxide charge, which is consistent with the NO annealing temperature/time dependence of interface trap density measured by conductance technique. However, NO annealing temperature has more pronounced influence on the SiO₂/SiC interface than NO annealing time.     

MOS器件的质子总剂量效应

介绍了几种加固和非加固 MOS电路的质子辐照总剂量效应实验 ,质子束的能量为 9、 7、 5、 2 Me V.实验结果表明 ,在相同的吸收剂量下 ,MOS器件累积电离辐射损伤与质子能量成正比 .还给出了栅极偏压对器件质子辐射损伤的影响 ,结果认为 ,对于 NMOSFET,不论是加固器件 ,还是非加固器件 ,在 +5 V的栅压偏置下 ,器件的辐射损伤比 0 V栅压下的损伤严重 ,对于加固器件 ,辐射感生界面态的密度也较高 ;而加固型 PMOSFET,在 0 V的栅压下 ,辐射损伤比 - 5 V下严重 ,且界面态的密度高     

Nanoscale germanium MOS Dielectrics-part I: germanium oxynitrides

In this paper, nanoscale germanium (Ge) oxynitride dielectrics are investigated for Ge MOS device applications. The synthesizing methodology and physical properties of these oxynitride films have been examined first. Basic electrical characteristics have been acquired on metal-gated MOS capacitors with Ge oxynitride dielectric on substrates with different dopant types and crystal orientations. Using an optimized oxidation and nitridation recipe, high-quality Ge MOS capacitors with a minimal frequency dispersion and capacitance-voltage hysteresis have been demonstrated. In addition, the Ge oxynitride dielectric-substrate interface has also been analyzed with the combined low-frequency-high-frequency capacitance method that revealed a substantial reduction of interface trap density after the forming gas anneal. An asymmetric interface trap density distribution within the Ge bandgap has been mapped out, which might explain the inferior n-channel Ge MOSFETs with oxynitride dielectric. An abnormality in the general gate leakage behavior has been observed and found to originate from a transient charge-trapping effect.     

A model for analyzing the interface properties of asemiconductor-insulator-semiconductor structure. I. Capacitance andconductance techniques

A model is presented for analyzing the interface properties of a semiconductor-insulator-semiconductor (SIS) capacitor structure. By introducing a coupling factor, conventional metal-oxide-semiconductor (MOS) capacitor theory is extended to analyze the interface properties of the film/buried-oxide/substrate interfaces of a silicon-on-insulator (SOI) material. This model was used to determine parameters such as doping concentration, buried oxide thickness, fixed oxide charge, and interface trap density from the SIMOX (separation by implantation of oxygen) based SIS capacitors     

HfO2/TaON叠层栅介质Ge MOS器件制备及电性能研究

为提高高k/Ge MOS器件的界面质量,减小等效氧化物厚度(EOT),在high-k介质和Ge表面引入薄的TaON界面层.相对于没有界面层的样品,HfO2/TaON叠层栅介质MOSFET表现出低的界面态密度、低的栅极漏电和较好的输出特性.因此利用TaON作为Ge MOS器件的界面钝化层对于获得小的等效氧化物厚度和高的高k/Ge界面质量有着重要的意义.     

Modeling MOS capacitors to extract Si—SiO2interface trap densities in the presence of arbitrary doping profiles

A conventional Poisson solver has been used to calculate the quasi-static capacitance of an MOS capacitor. The effects of an energy dependent Si-SiO2interface trap density and of an arbitrary silicon substrate doping profile have been included. This model has been used to calculate the quasi-staticC-Vcharacteristics and to compare them with those measured using Kuhn's technique for as-received and for gamma-irradiated p-type and n-type silicon MOS capacitors. The substrate doping profiles were obtained from high-frequencyC-Vcurves. Experimental and theoreticalC-Vcurves were made to agree by varying the voltage offset due to fixed oxide charge and both the magnitude and the energy distribution of interface trapped charge. The distributions of interface traps that gave the best fits between experiment and theory are donor-like with a peak 0.1 eV below midgap for the p-type and 0.1 eV above midgap for the n-type silicon MOS capacitors. The predictedC-Vcurves are insensitive to increases in the density of interface traps near the band edge.     

LPCVD-silicon oxynitride films: interface properties

The interface properties of silicon oxynitride films prepared by low-pressure chemical vapor deposition at a temperature of 860 ° C have been investigated analyzing the capacitance–voltage and ac conductance–voltage characteristics of the metal-SiO_xN_y-silicon capacitors. Consistent results for the interface trap density have been obtained from single frequency ac conductance technique, approximation C–V method and from the interface density spectrum. The post-deposition annealing results in an improvement of the interface charge properties. The contribution of the interface traps to the estimation of the fixed oxide charge has been discussed which is important for the threshold voltage control in MOS devices.