Digital Window Comparator DfT Scheme for Mixed-Signal ICs

The possibility of using window comparators for on-chip and potentially also on-line response evaluation of analogue circuits is investigated. No additional analogue test inputs are required. The additional circuitry can be either realised by means of standard digital gates taken from an available library or by full custom designed gates. With only a few gates an observation window can be realized, tailored to the application needs. With this approach, the test overhead can be kept extremely low. Due to the low gate capacitance also the load on the observed nodes is very low. Simulation results for some examples show that 100% of all assumed layout-realistic faults could be detected.     

Design of Digital Window Comparators and their Implementation within Mixed-Signal DfT Schemes

An in detail design of digital window comparators is presented. This comparator can be used for the on-chip (and potentially on-line) response evaluation of analogue circuits. The analysis shows that if the design parameter is in the order of 1 ... 0,36 for the NOR and 1 ... 2,8 for the NAND good results for the comparator can be achieved and the variation of the window position is limited to 5%. Parameter and temperature drifts are discussed along with results from characterisation. The results can be extended to deep-submicron technologies if the respective equations are used to derive the logical threshold and beta values. A simplified comparator is described that also allows the localisation of the evaluated signal. The conditions for the implementation of the window comparators into Design-for-Testability schemes are outlined. It is demonstrated that the digital window comparator can be implemented in the digital part of the mixed-signal integrated circuit.     

On-Chip Test for Mixed-Signal ASICs using Two-Mode Comparators with Bias-Programmable Reference Voltages

A design-for-testability implementation for analogue functional blocks of mixed-signal ASICs is presented. For the analogue blocks direct access via an analogue input pin for the automated test equipment is required. To this end existing OpAmp or OTA stages of the respective analogue blocks are converted into simple clocked comparators. The resulting two-mode comparators are used to observe specific internal nodes of the functional block under test. Depending on the comparator mode, the observed test response evaluation can either be static and/or quasi-dynamic. At least two reference voltages are required each with two different levels determined by a hysteresis. All necessary reference voltages are generated on-chip in the central biasing cell of the ASIC. Due to this Design-for-Testability implementation, an on-chip test evaluation can be performed without the need to bring an analogue signal on- or off-chip. From simulation and measurement results of a feasibility study performed on a general purpose test circuit realised in 0.35 m technology, the applicability was demonstrated. It showed that good fault coverages in the analogue functional blocks can be achieved. Estimations about the biasing programming indicated that this technique is in particular suitable for mixed-signal ASICs larger than 15 mm² with a typical total power consumption of more than 50 mW typical for high voltage applications.