A highly linear and fully-integrated FMCW synthesizer for 60 GHz radar applications with 7 GHz bandwidth

A highly linear and fully-integrated frequency-modulated continuous-wave (FMCW) generator based on a fractional-N phase-locked loop (PLL) that is able to synthesize modulation schemes in 57–64 GHz range is proposed in this paper. The fractional-N PLL employs Colpitts voltage-controlled oscillator (VCO) at 60 GHz with 13.5% tuning range. Automatic amplitude and frequency calibrations are implemented to avoid drifts due to process, voltage and temperature variations and to set the center frequency of the VCO. Five-stage multi-modulus divider is used for division ratio switching, controlled by the sigma-delta (\(\Sigma \Delta\)) modulator MASH 1-1-1. The frequency sweep (chirp) bandwidth and duration are fully programmable via serial peripheral interface allowing up to 16 different chirps in complex modulation scheme. The PLL reference signal is 250 MHz provided by external low-noise signal generator which is also used for digital modules clock. The overall PLL phase noise is lower than ?80 dBc/Hz at 10 kHz offset and the chirp linearity is better than 0.01%. The complete FMCW synthesizer is implemented and verified as a stand-alone chip in a commercially available SiGe HBT 130 nm BiCMOS technology. The total chip area is \(2.04\,\text {mm}^2\), and the total power consumption is 280 mW.     

A 6–9 GHz UWB balun-LNA employing current-reuse with preamplifier and CCC buffer

This paper presents a high-gain and low-power balun-LNA for ultra-wideband receiver operating in the upper band (6–9 GHz). Common gate (CG) preamplifier in front of the active balun can provide input matching and suppress noise from the follow-up stages. Active balun shares bias current with the CG stage to reduce power consumption. Capacitor-cross-coupled buffer is cascaded for signal amplitude and phase correction. The balun-LNA is fabricated in TSMC 130 nm CMOS technology and it consumes 5.5 mA current from a 1.3-V supply including buffer. This balun-LNA can achieve wideband gain from 6.5 to 9.0 GHz and the maximum gain is 23 dB. The input return loss is better than 20 dB from 6.5 to 9.0 GHz. The core area of the LNA is 0.53 mm². Simulated noise figure of the LNA is under 3.2 dB.     

A highly linear wideband 0.3-to-2.7 GHz variable-gain amplifier

A design of a differential variable-gain amplifier (VGA) with high IP3 (third-order intercept point) is discussed. To improve IP3, the third-order intermodulation products, which are generated by both an intrinsic third-order nonlinearity and a second-order interaction of a transistor, are minimized by using a nonlinear conductance. Unlike prior methods, the proposed method enables the achievement of both constant and broadband IP3 for various VGA gain settings. A design example with virtual but realistic BSIM4 transistor models is discussed to verify the analysis. The resultant amplifier example was designed and simulated in a 28-nm FDSOI CMOS technology. The amplifier achieved more than 15 dBm input-referred IP3 across a 2.4-GHz bandwidth from 0.3-to-2.7 GHz with a variable gain of 0-to-8.5 dB while consuming 3.3 mA from a 1.5-V supply.     

A highly linear 1.2 V 12bit 5–45 MS/s CMOS pipelined ADC with CM-sensing-and-input-interchanged OTA sharing

A 1.2 V 12bit programmable pipelined ADC is presented and implemented in 0.13 μm CMOS technology. A common-mode-sensing-and-input-interchanged OTA-sharing technique is proposed to address the non-resetting and successive-stage crosstalk issues in conventional OTA-sharing technique. Speed options of 5–45 MS/s are available with scalable power obtained by adjusting the bias currents for OTAs, comparators, and reference buffers, etc., or the global bias current. The measured signal-to-distortion-and-noise ratio is in range of 62.5–69.2 dB, and the peak spurious free dynamic range is 80.7 dB for all speed options, while the figure-of-merit is in the range of 0.26–0.49 pJ/conversion. The core area is 1.5 mm².     

5.18–7.42 GHz LC-VCO in subthreshold regime with low power low phase noise and immunity to PVT variations in 130 nm CMOS technology

In this paper, we propose an LC-VCO using automatic amplitude control and filtering technique to eliminate frequency noise around 2\(\omega _0\). The LC-VCO is designed with TSMC 130 nm CMOS RF technology, and biased in subthreshold regime in order to get more negative transconductance to overcome the losses in the LC-Tank and achieve less power consumption. The designed VCO operates at 5.17 GHz and can be tuned from 5.17 to 7.398 GHz, which is corresponding to 35.5% tuning range. The VCO consumes through it 495–440.5 \(\upmu\)W from 400 mV dc supply. This VCO achieves a phase noise of \(-\,122.3\) and \(-\,111.7\) dBc/Hz at 1 MHz offset from 5.17 and 7.39 GHz carrier, respectively. The calculated Figure-of-merits (FoM) at 1 MHz offset from 5.17 and 7.39 GHz is \(-\,199.7\) and \(-\,192.4\) dBc/Hz, respectively. And it is under \(-\,190.5\) dBc/Hz through all the tuning range. The FoM\(_T\) at 1 MHz offset from 5.17 GHz carrier is \(-\,210.6\) dBc/Hz. The proposed design was simulated for three different temperatures (\(-\,55\), 27, \(125\,^{\circ }\hbox {C}\)), and three supply voltages (0.45, 0.4, 0.35 V), it was concluded that the designed LC-VCO presents high immunity to PVT variations, and can be used for multi-standard wireless LAN communication protocols 802.11a/b/g.     

A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

A 0.1–4 GHz software-defined radio (SDR) receiver with reconfigurable 10–100 MHz signal bandwidth is presented. The complete system design methodology, taking blocker effects into account, is provided. Fully differential Op-Amp with Miller feedback and feed-forward compensations is proposed to support wideband analog circuits with low power consumption. The stability and isolation of inverter-based trans-conductance amplifier are analyzed in details. The design approach of high linearity Tow-Thomas trans-impedance amplifier is presented to reject out-of-band blockers. To compensate for PVT variations, IIP2, frequency tuning, DC offset and IQ calibration are also integrated on-chip. The SDR receiver has been implemented in 65 nm CMOS, with 1.2/2.5 V power supply and a core chip area of 2.4 mm². The receiver achieves S11 input matching below ?10 dB and a NF of 3–8 dB across the 0.1–4 GHz range, and a maximum gain of 82–92 dB with a 70 dB dynamic range. Dissipated power spans from 30 to 90 mW across this entire frequency range. For LTE application with 20 MHz signal bandwidth and a LO frequency of 2.3 GHz, the receiver consumes 21 mA current.     

A 2 GHz variable gain low noise amplifier in 0.18-μm CMOS

This paper describes a 2 GHz active variable gain low noise amplifier (VGLNA) in a 0.18-μm CMOS process. The VGLNA provides a 50-Ω input impedance and utilizes a tuned load to provide high selectivity. The VGLNA achieves a maximum small signal gain of 16.8 dB and a minimum gain of 4.6 dB with good input return loss. In the high gain and the low gain modes, the NFs are 0.83 dB and 2.8 dB, respectively. The VGLNA’s IIP3 in the high gain mode is 2.13 dBm. The LNA consumes approximately 4 mA of current from a 1.8-V power supply.     

CMOS implementation of a 1.6 GHz low voltage low phase noise quadrature output frequency synthesizer with automatic amplitude control

This article presents the design of a 1.2 V CMOS low phase noise quadrature output frequency synthesizer (FS) to be used for a GPS tuner application. Special reference is made to the design of a wide tuning range quadrature output voltage-controlled oscillator which is equipped with an automatic amplitude controller. It exhibits a phase noise response of less than −115 dBc/Hz at an offset of 1 MHz from the carrier and has a tuning range of over 36%. The effect of the automatic amplitude control is shown to improve phase noise at high oscillation frequencies and its noise has a negligible effect on the phase noise response even at low offset frequencies from the carrier. Preliminary analysis is presented showing the negligible effect of a DC–DC converter on the spurious level of the FS, included to permit the use of low sensitivity varactors. Design guidelines for reducing both the loop noise and the AM-to-PM conversion factors of the oscillator are also given. The design was made using the STMicroelectronics 0.13 μm HCMOS9-RF technology design kit.     

A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur

This paper presents a 5.7–6.0 GHz Phase-Locked Loop (PLL) design using a 130 nm 2P6M CMOS process. We propose to suppress reference spur through reducing the current mismatch in charge pump (CP), controlling the delay time in phase frequency detector (PFD), and using a smaller VCO gain (KVCO). With a reference frequency of 32.768 MHz, chip measurement results show that the frequency tuning range is 5.7–6.0 GHz, the reference spur is −68 dBc, the phase noise levels are −109 dBc/Hz and −135 dBc/Hz at 1 MHz and 10 MHz offset respectively for 5.835 GHz. Compared with existing designs in the literature, this work’s reference spur is improved by at least 17% and its phase noise is the lowest. Under a 1.5 V supply voltage, the power dissipation with an output buffer of the PLL is 12 mW.     

94 GHz down-conversion mixer with gain enhanced Gilbert cell in 90 nm CMOS

This paper introduces an adaptive semiblind background calibration of timing mismatches in a two-channel time-interleaved analog-to-digital converter (TIADC). By injecting a test tone at the frequency of half the overall sampling frequency of TIADC, the timing mismatch between two sub-ADCs can be quickly estimated with great accuracy without affecting the normal operation of the TIADC. The estimated coefficient can then be used in compensation module formed by a fixed structure to calibrate the timing mismatches. Simulation results demonstrate the effectiveness of the proposed estimation and correction technique.     

A 0.5–1 GHz single stage linear-in-decibel VGA with 80 dB gain range in 0.18 μm CMOS

Communication systems require a wide gain range. For example the code-division multiple access system (CDMA) requires more than 80 dB of gain range so that, many variable gain amplifiers (VGAs) must be used, resulting in high power consumption and low linearity because of VGA non-linearity factors. In this paper, a one-stage VGA in 0.18 μm technology is presented. The VGA based on the class AB power amplifier is designed and simulated for a high linearity and an 80 dB tuning range. For the linear-in-decibel tuning range, transistors in sub-threshold region is used. The current control circuit of the VGA changes gain continuously from ?68 to 18 dB at 0.5 GHz and ?60 to 20 dB at 1 GHz with gain error of less than 2 dB. The power consumption enjoys a highest value about 13.5 mW in the maximum gain and P1dB is also about ?3.4 dBm at 0.5 GHz and 2.2 dBm at 1 GHz.     

LC-VCO design optimization at 1/f 2 phase noise performance in 65 nm CMOS technology

A way of analytical calculation in the phase noise modeling of the LC-VCO topology without tail current resource is proposed. The noise current imported by the MOS channel is modeled to give approximate evaluation, and the period of the transistor noise is included in the model. Phase noise introduced by the tank loss resistance is also modeled to evaluate the circuit phase noise performance. The circuit has been implemented in a 65 nm CMOS technology. The chip occupies 951 × 705 um² areas with the buffer and pads. The test result indicates that the VCO core consumes 1.125 mW with a 1.2 V power supply, the frequency of the VCO baseband is from 1.258 to 1.37 GHz, and the multiband frequency is from 0.86 to 1.37 GHz. The best performance of the LC-VCO shows a phase noise of ?129.57 dBc/Hz at 1 MHz offset frequency from a 1.3 GHz carrier, resulting in an excellent FoM of ?191.27 dBc/Hz.     

A 90–96 GHz CMOS down-conversion mixer with high conversion gain and excellent LO–RF isolation

A 90–96 GHz down-conversion mixer for 94 GHz image radar sensors using standard 90 nm CMOS technology is reported. RF negative resistance compensation technique, i.e. NMOS LC-oscillator-based RF transconductance (GM) stage load, is used to increase the output impedance and suppress the feedback capacitance C_gd of RF GM stage. Hence, conversion gain (CG), noise figure (NF) and LO–RF isolation of the mixer can be enhanced. The mixer consumes 15 mW and achieves excellent RF-port input reflection coefficient of ?10 to ?36.4 dB for frequencies of 85–105 GHz. The corresponding -10 dB input matching bandwidth is 20 GHz. In addition, for frequencies of 90–96 GHz, the mixer achieves CG of 6.3–9 dB (the corresponding 3-dB CG bandwidth is greater than 6 GHz) and LO–RF isolation of 40–45.1 dB, one of the best CG and LO–RF isolation results ever reported for a down-conversion mixer with operation frequency around 94 GHz. Furthermore, the mixer achieves an excellent input third-order intercept point of 1 dBm at 94 GHz. These results demonstrate the proposed down-conversion mixer architecture is very promising for 94 GHz image radar sensors.     

A 0.18μm CMOS Gilbert low noise mixer with noise cancellation

正This paper presents a broadband Gilbert low noise mixer implemented with noise cancellation technique operating between 10 MHz and 0.9 GHz.The Gilbert mixer is known for its perfect port isolation and bad noise performance.The noise cancellation technique of LNA can be applied here to have a better NF.The chip is implemented in SMIC 0.18μm CMOS technology.Measurement shows that the proposed low noise mixer has a 13.7-19.5 dB voltage gain from 10 MHz to 0.9 GHz,an average noise figure of 5 dB and a minimum value of 4.3 dB.The core area is 0.6 x 0.45 mm~2.     

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a current-reused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the current-reused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum \(S_{21}\) gain of 11.4 dB gain with a \(-\)3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the measured \(S_{11}\) and \(S_{12}\) are less than \(-\)10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.     

A 60 GHz receiver front-end in 65 nm CMOS

In the past few years, the mm-wave silicon, especially 60 GHz CMOS design has experienced a transition from an obscure topic to a research hot spot. This paper presents the design of a 60 GHz receiver front-end using 65 nm CMOS technology. Initially, a heterodyne receiver front-end architecture is presented to exploit its possible compatibility with legacy systems. In order to implement the front-end, an EM simulation based methodology and the corresponding design flow are proposed. A transistor EM model, using existing compact models as core, is developed to account for the parasitic elements due to wiring stacks. A spiral inductor lumped model, based on S-parameter data from EM simulation is also derived. After the device modeling efforts, a single-stage LNA and a single-gate mixer are designed using 65 nm CMOS technology. They are characterized by EM co-simulation, and compared with the state-of-the-art. After integration, the simulated front-end achieves a conversion gain of 11.9 dB and an overall SSB noise figure of 8.2 dB, with an input return loss of −13.7 dB. It consumes 6.1 mW DC power, and its layout occupies a die area of 0.33 mm × 0.44 mm.     

A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS

A 12 GHz PLL with digital output phase control has been implemented in a 90 nm CMOS process. It is intended for LO signal generation in integrated phased array transceivers. Locally placed PLLs eliminate the need of long high frequency LO routing to each transceiver in a phased array circuit. Routing losses are thereby reduced and the design of integrated phased array transceivers becomes more modular. A chip was manufactured, featuring two separate fully integrated PLLs operating at 12 GHz, with a common 1.5 GHz reference. The chip, including pads, measures 1050 × 700 μm². Each PLL consumes 15 mA from a 1.2 V supply, with a typical measured phase noise of −110 dBc/Hz at 1 MHz offset. The phase control range exceeds 360°.     

A highly linear CMOS transconductance amplifier in 180?nm process technology

The present article describes the design and analysis of an operational transconductance amplifier (voltage to current converter) with wide linear input range. The proposed configuration combines the techniques of signal attenuation and source degeneration in order to reduce the odd order harmonic distortion significantly. The proposed circuit is compared with several circuit topologies based on MOS differential pairs with respect to their achievable linearity, input referred noise and power consumption. The linear transconductor is designed and simulated in 180?nm CMOS process technology with 1.8?V power supply. Simulation results show third order harmonic distortion (HD ₃) of ?70?dB for 600?mV_pp input signal. For 1% transconductance variation the linear range is about 1.2?V_pp. The input referred noise of the transconductor is $70\,\hbox{nV}/\sqrt{\text {Hz}}$ at 10?MHz. The quiescent power consumption is only 450???W.