Testing analog circuits using spectral analysis

In this work a test strategy for analog circuits based on spectral analysis is proposed. The test strategy is blind, in the sense that only statistical information about the input signal is needed, but no sampling of the input signal is required. This feature allows the test of analog circuits with minimum analog hardware addition. In the context of Systems-on-Chip, this strategy needs only the inclusion of a small random signal generator, and transfers most of the signal processing to the digital domain, allowing the use of a purely digital tester or a digital BIST technique. This paper presents the underlying principle of the method and experimental test results for linear analog systems.     

Frequency-domain analysis of strongly nonlinear circuits using aconsistent large-signal model

This paper describes an analysis method that extends the applicability of the frequency-domain methods to strongly nonlinear circuits. Nonlinearities are described with Chebyshev expansions which are evaluated with a numerically stable three-term recurrence formula. The method is coupled with a novel, measurement-based consistent modeling approach which allows improved accuracy in describing the frequency-dependence of the measured small-signal parameters. The analysis method and the modeling approach are verified by comparing measurements and calculations on a MESFET mixer, driven with two and three tones     

Fast solution of nonlinear equations using parallel analog hardware

Parallel analog circuits are introduced for the solution of systems of nonlinear algebraic equations and the integration of systems of differential equations. Both simulations using HSPICE and a hardware implementation are presented which show how the circuitry can be used to solve: the power flow and transient analysis problems for power systems, and the simulation of a jet engine. In all cases solutions are obtained in better than real time. The results are comparable in accuracy to digital solutions of the same problems.     

An improved analysis for the nonlinear performance of body-driven analog MOSFET circuits

This article discusses the nonlinear performance of body-driven analog long-channel MOSFET circuits. Analytical expressions are obtained for the nonlinear distortion products resulting from sinusoidal excitation of the body terminals. The special case of a single sinusoid excitation is considered in detail, and conditions for harmonic suppression are obtained.     

Trimming analog circuits using floating-gate analog MOS memory

A floating-gate MOS analog memory circuit that can be electrically programmed for positive and negative voltage changes and that can be fabricated in a standard CMOS IC process is described. Unlike existing electrically erasable floating-gate memory circuits, this circuit does not require special fabrication techniques like ultrathin tunneling oxides or textured polysilicon. Instead, mask geometry is used to cause field-enhanced Fowler-Nordheim tunneling of electrons from a floating gate. Retention measurements at elevated temperatures indicate that the loss of floating-gate charge should be less than 0.1% over a ten-year period at temperatures below 100°C. One limitation of this structure is that the rate of change of the floating-gate voltage can be quite small (e.g. 10 mV/s). A general trimming circuits, whose novel feature is that any number of trimming circuits can be independently and simultaneously adjusted across an entire IC, has been incorporated into a prototype CMOS op amp to decrease its input offset voltage from 10 mV to less than 0.5 mV     

基于灵敏度分析及Volterra级数的非线性模拟电路故障诊断

为了有效解决非线性模拟电路故障诊断问题,提出了一种基于灵敏度分析及Volterra级数理论的故障诊断方法。首先采用灵敏度分析估计激励信号的有效频带范围,根据Volterra级数确定激励信号的频率成分,以使故障可测度最大化;其次基于多音激励下Volterra核的频域输出特性进行故障特征提取,并采用主元分析(principal componentanalysis,PCA)对故障特征进行维数压缩;最后构造多值分类支持向量机(support vector machine,SVM)网络进行故障模式判别。理论分析及仿真结果表明,与以往方法比较,该方法可以显著提高非线性模拟电路故障识别率,验证了该方法的有效性。     

An adjustable accuracy model for VLSI analog circuits using lookup tables

The successful design of analog VLSI circuits requires both a precise and computationally efficient device model. An accuracy adjustable table look-up modeling methodology, using a multidimensional gradient data tracing methodology and an interpolation technique with monotonicity, has been developed for analog circuit simulation. Using this technique, several table models with different accuracies have been compiled and utilized to simulate analog circuits such as a CMOS push-pull inverter and cascode opamp with a regulated current sink without loss of computational efficiency. This accuracy adjustable modeling approach has the ability to compromise between table size (speed) and model accuracy. Model accuracy can be emphasized in a specific device operation range where accuracy is critical to circuit performance by utilizing an accuracy partitioning methodology. A generic modeling methodology has been successfully generalized with dependent and independent variables applicable to several technologies, including CMOS, bipolar, and GaAs technologies. Simulation results from table models compiled by this new approach are not only more accurate but also more computationally efficient (faster) than conventional device models such as SPICE level 2 and BSIM models.     

Model order reduction using spline-based dynamic multi-point rational interpolation for passive circuits

The efficient modeling of integrated passive components and interconnects is vital for the realization of high performance mixed-signal systems. In this paper, we develop a dynamic multi-point rational interpolation method based on Krylov subspace techniques to generate reduced order models for passive components and interconnects that are accurate across a wide-range of frequencies. We dynamically select interpolation points by applying a cubic spline-based algorithm to detect complex regions in the system's frequency response. The results indicate that our method provides greater accuracy than techniques that apply uniform interpolation points.     

Analysis of transmission line circuits using multidimensional model reduction techniques

This paper presents a new technique to reduce the order of transmission line circuits simultaneously with respect to multiple parameters. The reduction is based on multidimensional congruence transformation. The proposed algorithm provides efficient means to estimate the response of large distributed circuits simultaneously as a function of frequency and other design parameters.     

Fast reliability analysis of combinatorial logic circuits using conditional probabilities

Probabilistic reliability analysis is a common approach in logic circuit reliability analysis. Existing methods suffer from accuracy or scalability problems for large circuits because of combinatorial explosion. In this work we show how the use of conditional probabilities can overcome scalability problems while maintaining accurate reliability estimation. The source of accuracy and scalability problems in these approaches is the presence of reconverging signals. An efficient use of conditional probabilities used to decorrelate signals allows for fast and accurate reliability analysis.     

Symbolic simulators for the fault diagnosis of nonlinear analog circuits

A new symbolic technique for the realization of simulators for nonlinear analog circuits is presented. The generated simulators work with input/output in numerical form, but they are very efficient due to the use of the symbolic approach. For nonlinear components a PWL (PieceWise Linearization) method is used. The proposed approach permits to obtain libraries of simulators which can be very useful in many application fields. In particular we present a possible application to an expert system devoted to nonlinear circuit fault diagnosis. The program package, realized for this application, is described from both algorithmic and functional points of view. Some simple examples are presented in order to illustrate the main features of the program.1. We are supposing that all the nonlinear elements are represented by a characteristic of the kindI =G(V)     

Multilevel model order reduction

We present a multilevel Model Order Reduction scheme for enhancing numerical analysis of electromagnetic fields by means of grid based techniques. The scheme allows one to create nested macromodels and combine macromodels with the Fast Frequency Sweep. The implementation of the method is illustrated on the Finite Difference Frequency Domain technique and efficient nodal order reduction algorithm (ENOR) but the concept can easily be applied also for other mesh based methods and other order reduction schemes.     

Defect detection in analog and mixed circuits by neural networks using wavelet analysis

An efficient defect-oriented parametric test method for analog & mixed-signal integrated circuits based on neural network classification of a selected circuit's parameter using wavelet decomposition preprocessing is proposed in this paper. The neural network has been used for detecting catastrophic defects in two experimental analog & mixed-signal CMOS circuits by sensing the abnormalities in selected parameters, observed under defective conditions and by their consequent classification into a proper category. To reduce complexity of the neural network, wavelet decomposition is used to perform preprocessing of the analyzed parameter. Moreover, we show that wavelet analysis brings significant enhancement in the correct classification, and makes the neural network-based test method extremely efficient & versatile for detecting hard-detectable catastrophic defects in analog & mixed-signal circuits.     

State reduction for efficient digital calibration of analog/RF integrated circuits

Calibration of analog/radio-frequency (RF) integrated circuits addresses the problem of yield loss that is a result of the increased variability commonly observed in nanoscale processes. In order to compensate for increased yield loss, calibration techniques have been developed that are applied to fabricated chips, aiming at the restoration of a circuit’s performance to its acceptable range of values that are defined by the specifications. To allow calibration, adjustable elements are introduced that provide multiple states of a circuit’s operation through built-in tuning knobs. Digital calibration—that refers to the case of discrete tuning knob settings—is performed by switching to a circuit’s state at which all performance characteristics are restored to their specified ranges. Due to the large number of performance characteristics of interest a large space of tuning knob settings should be explored, that leads to a series of practical considerations that need to be addressed, such as increased times required for calibration preparation and conduction, or chip area overhead if built-in tuning knobs are used. In this paper we present a method to maintain a desired level of yield recovery through the exploitation of only a minimum number of calibration states, also ensuring low cost by shortening calibration times and reducing chip area overhead. The proposed method is assessed through case studies conducted on a typical RF mixer designed in a 180 nm CMOS technology.     

Design and analysis of CMOS analog signal processing circuits bymeans of a graphical MOST model

A graphical representation of a simple MOST (metal-oxide-semiconductor transistor) model for the analysis of analog MOS circuits operating in strong inversion is given. It visualizes the principles of signal-processing techniques depending on the characteristics of an MOS transistor. Several linearization techniques as well as a multiplying principle become transparent at the hand of the graphical representation. In the examples, special attention is focused on continuous-time filter techniques. The basis of MOSFET-C continuous-time filters and CMOS square-law circuits are explained using the graphical MOST characteristics representation     

模拟电路常见故障的诊断及处理分析

随着科学技术发展日新月异和全民智能化时代的到来,种类繁多的电子产品在人们日常生活中的应用也变得随处可见,从各个方面影响着人们的生活。但是,电子产品在使用过程中也容易受到电路故障的影响而失效。因此,在电子产品电路出现故障时,及时找到故障原因是十分必要的。文章将系统地探寻和分析电路故障的常见诊断方法,达到提升电路故障处理速率的目的,并确保将电路故障带来的损失降至最低。     

Least-squares model order reduction enhancements

Two enhancements to the least-squares (LS) discrete-time model order reduction (MOR) method are presented: scaling and frequency response matching. Scaling generally improves the low-frequency fit between the reduced-order model (ROM) and the original model. For exact gains at specific frequencies, optional frequency response constraints can easily be added to the LS MOR method. An example is presented that illustrates these enhancements. The example model is reduced with the Hankel norm, weighted impulse response gramian, and LS MOR methods. Plots of error versus frequency are given for each of the three MOR methods     

Noise analysis of dynamically nonlinear translinear circuits

Current noise analysis techniques for translinear and other companding filters are unsuitable for circuits that contain intentional dynamic nonlinearities. The authors present a method for treating dynamic nonlinearities in a straightforward manner using stochastic differential equations     

Efficient design centering of analog integrated circuits using binary search

This paper introduces a procedure for automatically design centering analog integrated circuits called the divide-and-focus method (DAF). DAF is a simple, efficient, and effective algorithm for design centering complex circuits, even if the performance of the original nominal design is poor. DAF uses a binary search of each dimension of parameter space to rapidly focus on regions promising high yield. DAF was applied to a third-order elliptic CMOS transconductance-C integrated circuit filter derived from an automated layout and containing 126 nodes and 319 MOSFETS. Using five key capacitor values as design centering parameters, DAF improved yield in the presence of parasitic capacitance (as extracted from the layout) by a factor of 19 from an initial value of 4% to a final value of 76%. By relaxing constraints on component value symmetry, DAF found a higher yield than was possible when maintaining symmetry, where DAF achieved a yield of 34%. Since DAF uses Monte Carlo analysis to estimate circuit yield, its execution time can be further reduced by exploiting the parallelism implicit in Monte Carlo techniques. Using a local area network of 10 workstations similar to those available at most engineering sites, DAF completed the design centering of the filter 7.4 times faster than when using a single workstation.Supported in part by a Research Initiation grant (CCR-9111941) from the National Science Foundation.Supported in part by a grant (MIP-9121360) from the National Science Foundation.