A low-power and robust quaternary SRAM cell for nanoelectronics

This paper presents an efficient and low-power quaternary static random-access memory (SRAM) cell based on a new quaternary inverter. For implementation, carbon nanotube field-effect transistors (CNTFETs) are used. Stacked CNTFETs are appropriately used in the proposed design to achieve a considerably low static power dissipation. The proposed SRAM has a more significant static noise margin due to its single quaternary digit line, and it is appropriate for MVL SRAM design as there are more than two stable states. The simulation results using Synopsys HSPICE with 32 nm Stanford comprehensive CNTFET model demonstrate the correct and robust operation of the proposed designs even in the presence of major process variations. In addition, the proposed SRAM cell is applied in a 4?×?4 SRAM array structure to demonstrate the efficiency of the proposed SRAM. The results indicate that the proposed design significantly lowers the power consumption and provides comparable static noise margins compared to the other state-of-the-art CNTFET-based circuits.

     

A low-power high-performance current-mode multiport SRAM

This paper presents a new approach for energy reduction and speed improvement of multiport SRAMs. The key idea is to use current-mode for both read and write operations. To toggle a memory cell, a very small voltage swing is first created on the high-capacitive bit lines. This voltage is then translated into a differential current being injected into the cell, which in turn allows complementary potential to be developed on the cell nodes. As compared to the conventional write approach, SPICE simulations using a 0.35-μm CMOS process have shown 2.8 to 9.9× in energy savings and 1.02 to 6.36× reduction in delay, for memory sizes of 32 to 1 K words. We also present a current-mode sense-amplifier that operates in a similar fashion as the write circuit. The design and implementation of a pipelined 32×64 three-port register file utilizing the proposed technique is described. Measurements of the register file chip have confirmed the feasibility of the approach     

A new low-power 10T SRAM cell with improved read SNM

This paper describes the characteristics of a new 10T structure for SRAM cell that works quite well in the sub-threshold region. This new architecture has good characteristics in write and read delay and energy compared with other new structures. This new 10T topology improves read static noise margin (SNM) and write operation speed with respect to other topologies in the same or even lower power consumption. The new topology has at least 13% lower power consumption compared with the best of recent architectures. Its write characteristics also are similar to those of 6T-SRAM, which has improved write delay and energy. The new 10T SRAM cell also consumes lower power compared with other cells. The stacking is used to suppress the standby leakage through the read path. The simulations were performed using HSPICE 2011 in a 16 nm bulk CMOS Berkeley predictive technology model (BPTM).     

A current-sensed high-speed and low-power first-in-first-out memoryusing a wordline/bitline-swapped dual-port SRAM cell

First-in-first-out (FIFO) data storages are in great demand for telecommunication LSIs. This paper presents high-speed and low-power CMOS memory techniques specialized for FIFO operation. A size-configurable architecture using the tile methodology is employed to customize the word counts and/or data bits with a. short time of less than 30 min. Four flag bits are introduced to inform the internal state of FIFO memories. To obtain a higher operating speed, an SRAM-like memory cell with current-sense readout is used. The critical-path delay of the Gray-code up/down counter, indicating the stored data volume, is shortened to 6.0 ns (66%) by using a double-rail single-stage XOR circuit. As to the low-power techniques, a wordline/bitline-swapped dual-port memory-cell architecture is proposed to cut off the static power-supply current of unselected columns. By using the hidden blanket-precharged bitline scheme, the power dissipation of the writing circuitry is minimized without degrading the operating speed. A new data-driven gated-shift-pulse architecture is also proposed to reduce the power dissipation of shift-register-type address pointers (1.5 mW at 100 MHz). A 2K-words × 8-bits FIFO memory test chip, fabricated with a 0.6-μm CMOS process (a short effective channel length of 0.35 μm is available for both the nMOS and pMOS), has demonstrated the 140-MHz operation at a typical 3.3-V power supply. The power dissipation in standby is less than 0.1 μW and that at 100-MHz dual-port operation with single fan-out loads is in the range from 28 mW (in the best case with the M-scan test pattern) to 46 mW (in the worst case with the checkerboard test pattern)     

NBTI product level reliability for a low-power SRAM technology

We present a methodology to investigate product level NBTI reliability for the 90 nm technology node including the correlation between transistor, circuit, and product level NBTI reliability. NBTI reliability lifetime, dielectric breakdown, and gate leakage currents pose an important limitation to the maximum applicable supply voltage across the gate oxide. Product standby currents and regulator design are highly influenced by transistor reliability. We will present product reliability data ensuring sufficient product level reliability as well as their correlation attempts to transistor level reliability data.     

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme

To realize high-density SRAMs, we developed a four-transistor SRAM cell with a newly developed stacked vertical poly-silicon PMOS. The vertical poly-silicon PMOS has a gate surrounding a body that forms a channel and yields a drive current of 20 /spl mu/A at 25/spl deg/C. Vertical poly-silicon PMOSs are used as transfer MOSs and are stacked over the bulk NMOSs, used as driver MOSs, to reduce the size of a four-transistor SRAM cell. As a result, the size of the proposed four-transistor SRAM cell was 38% of that of a six-transistor SRAM cell. We also developed an electric-field-relaxation scheme to reduce cell leakage and a dual-word-voltage scheme to improve cell stability. By applying these two schemes to the proposed four-transistor SRAM cell, we achieved a 90% reduction in cell leakage and an improvement in cell stability.     

A low-power SRAM using hierarchical bit line and local sense amplifiers

This paper proposes a low power SRAM using hierarchical bit line and local sense amplifiers (HBLSA-SRAM). It reduces both capacitance and write swing voltage of bit lines by using the hierarchical bit line composed of a bit line and sub-bit lines with local sense amplifiers. The HBLSA-SRAM reduces the write power consumption in bit lines without noise margin degradation by applying a low swing signal to the high capacitive bit line and by applying a full swing signal to the low capacitive sub-bit line. The HBLSA-SRAM reduces the swing voltage of bit lines to V/sub DD//10 for both read and write. It saves 34% of the write power compared to the conventional SRAM. An SRAM chip with 8 K/spl times/32 bits is fabricated in a 0.25-/spl mu/m CMOS process. It consumes 26 mW read power and 28 mW write power at 200 MHz with 2.5 V.     

An SRAM design using dual threshold voltage transistors and low-power quenchers

Static random access memories (SRAM) are widely used in computer systems and many portable devices. In this paper, we propose an SRAM cell with dual threshold voltage transistors. Low threshold voltage transistors are mainly used in driving bit-lines while high threshold voltage transistors are used in latching data voltages. The advantages of dual threshold voltage transistors can be used to reduce the access time and maintain data retention at the same time. Also, the unwanted oscillation of the output bitlines of memories caused by large currents in bitlines is reduced by adding two back-to-back quenchers. The proposed quenchers not only prevent oscillation, but also reduce the idle power consumption when the memory cells are not activated by wordline signals. Meanwhile, a large noise margin is provided such that the gain of the sense amplifier will not be reduced to avoid the oscillation. Hence, high-speed and low-power readout operations of the SRAMs are feasible.     

A robust and low-power near-threshold SRAM in 10-nm FinFET technology

This paper presents a robust and low-power single-ended robust 11T near-threshold SRAM cell in 10-nm FinFET technology. The proposed cell eliminates write disturbance and enhances write performance by disconnecting the path between cross-coupled inverters during the write operation. FinFETs suffer from width quantization, and SRAM performance is highly dependent to transistors sizing. The proposed structure with minimum sized tri-gate FinFETs operates without failure under major process variations. In addition, read disturbance is reduced by isolating the storage nodes during the read operations. To reduce power consumption this cell uses only one bit-line for both read and write operations. The proposed SRAM cell reduces write delay, average power and PDP by 20, 78 and 62%, respectively as compared to the 9T single-ended SRAM cell. Moreover, the proposed cell enhances write static noise margin by 33% under process variation.     

Stacked CMOS SRAM cell

A static random access memory (SRAM) cell with cross-coupled stacked CMOS inverters is demonstrated for the first time. In this approach, CMOS inverters are fabricated with a laser recrystallized p-channel device stacked on top of and sharing the gate with a bulk n-channel device using a modified two-polysilicon n-MOS process. The memory cell has been exercised through the write and read cycles with external signal generators while the output is buffered by an on-chip, stacked-CMOS-inverter-based amplifier.     

High-speed reduced-leakage SRAM memory cell design techniques for low-power 65 nm FD-SOI/SON CMOS technology

The paper presents a detailed study on the sub-1 V high speed operation with reduced leakage design techniques for conventional 6T Static Random Access Memory (SRAM) on fully depleted Silicon-on Insulator (FD-SOI) and fully depleted Silicon-on-Nothing (FD-SON) technology. Performance of SON MOSFET is found to be significantly better both in terms of power and speed from its equivalent SOI device. Future devices with advanced technology are promising for low-power application. The most promising high-speed, low-power operation techniques are introduced, analyzed and compared into 65 nm low-power FD-SOI/SON technology. Hspice simulations conclude Drive Source Line (DSL) architecture as the best option for high speed operation in sub 100 nm technology without affecting the Static Noise Margin (SNM) of the cells.     

6T SRAM cell analysis for DRV and read stability

The present paper analyzes the hold and read stability with temperature and aspect ratio variations. To reduce the power dissipation, one of the effective techniques is the supply voltage reduction. At this reduced supply voltage the data must be stable. So, the minimum voltage should be discovered which can also retain the data. This voltage is the data retention voltage(DRV). The DRV for 6T SRAM cell is estimated and analyzed in this paper. The sensitivity analysis is performed for the DRV variation with the variation in the temperature and aspect ratio of the pull up and pull down transistors. Cadence Virtuoso is used for DRV analysis using 45 nm GPDK technology files. After this, the read stability analysis of 6T SRAM cell in terms of SRRV(supply read retention voltage) and WRRV(wordline read retention voltage) is carried out. Read stability in terms of RSNM can be discovered by accessing the internal storage nodes. But in the case of dense SRAM arrays instead of using internal storage nodes, the stability can be discovered by using direct bit line measurements with the help of SRRV and WRRV. SRRV is used to find the minimum supply voltage for which data can be retained during a read operation. Similarly, WRRV is used to find the boosted value of wordline voltage, for which data can be retained during read operation. The SRRV and WRRV values are then analyzed for different Cell Ratios. The results of SRRV and WRRV are then compared with the reported data for the validation of the accuracy of the results.     

Statistical Design of the 6T SRAM Bit Cell

In this paper, a method for the statistical design of the static-random-access-memory bit cell is proposed to ensure a high memory yield while meeting design specifications for performance, stability, area, and leakage. The method generates the nominal design parameters, i.e., the widths and lengths of the bit-cell transistors, which provide maximum immunity to the variations in a transistor's dimensions and intrinsic threshold-voltage fluctuations. Moreover, the need to deviate from the conventional bit-cell sizing strategy to obtain a high-yield low-leakage design in the nanometer regime is demonstrated.      

面向手机通信市场Cypress固守SRAM领域优势

通过推出更高密度的CellularRAM(由Cypress、Infineon与Micron联合制定、施用于2.5G及3G无线手持终端的低功耗PSRAM规范)产品,以及可实现50%系统级带宽增幅的72MbitQDR器件,Cypress公司继续巩固了其在SRAM领域的强势地位.     

A 25-ns low-power full-CMOS 1-Mbit (128 K×8) SRAM

A 5-V full-CMOS 1-Mb SRAM (static random-access memory) is described. The access time is 25 ns with 30-pF load, and power dissipation is 75 mW at 10 MHz and less than 1 μW in standby mode. The chip is made in a 0.7-μm twin-tub, single-poly, double-metal technology on p/p⁺ epi substrate. Cascoding of NMOS devices and special timing techniques are used to suppress hot-electron degradation. The authors describe circuit techniques that obtain low active power dissipation and high speed for a byte-wide part     

Small-size low-power bipolar memory cell

A d.c.-stable random-access memory cell employing n-p-n and p-n-p transistors has been designed in a concurrent circuit-layout approach. Test chips with 2/spl times/3 arrays have been processed in a standard bipolar technology. Due to the merging of devices, the area required for a cell is only 14 mil/SUP 2/. The cells have been operated at an extremely low d.c. standby power of less than 0.1 /spl mu/W/cell. In spite of this low standby power, an array access time of 10 ns has been measured on a simulated 512-bit array in a pulsed power mode.     

一种低功耗结构的ADC设计

逐次逼近结构ADC是中速中高分辨率应用中的常见结构,其中DAC多采用电容阵列结构,但其动态功耗随分辨率的增加而增加.论文设计了一种新颖的10位ADC结构,它采用两级进行模数转换的方法,高位采用低功耗的并行模数转换结构,低位采用逐次逼近模数转换结构,通过合理设计高低位转换位数、低功耗比较器,采用简单的二进制搜索算法,有效...     

A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications

In sub-100-nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local dc level control (LDLC) for SRAM cell arrays and an automatic gate leakage suppression driver (AGLSD) for peripheral circuits. We designed and fabricated a 32-kB 1-port SRAM using 90-nm CMOS technology. The six-transistor SRAM cell size is 1.25 /spl mu/m/sup 2/. Evaluation shows that the standby current of 32-kB SRAM is 1.2 /spl mu/A at 1.2 V and room temperature. It is reduced to 7.5% of conventional SRAM.     

Locally switched and limited source-body bias and other leakage reduction techniques for a low-power embedded SRAM

A low-power embedded SRAM for a large range of applications has been implemented in a standard digital 0.18-/spl mu/m process. The leakage current in the cells is reduced by using a source-body bias not exceeding the value that guaranties safe data retention, and less leaking nonminimum length transistors. Locally short-circuiting this bias, speed and noise margin loss in active mode is avoided, especially for low supply voltages. The bias is generated internally at the carefully designed equilibrium between cell, switch, and diode limiter leakages averaged over the array. The leakage of the full SRAM, including an optimized periphery, is reduced more than 20 times. Used in an industrial RF transceiver, the measurements confirm its performances.     

Statistical models of video structure for content analysis andcharacterization

Content structure plays an important role in the understanding of video. In this paper, we argue that knowledge about structure can be used both as a means to improve the performance of content analysis and to extract features that convey semantic information about the content. We introduce statistical models for two important components of this structure, shot duration and activity, and demonstrate the usefulness of these models with two practical applications. First, we develop a Bayesian formulation for the shot segmentation problem that is shown to extend the standard thresholding model in an adaptive and intuitive way, leading to improved segmentation accuracy. Second, by applying the transformation into the shot duration/activity feature space to a database of movie clips, we also illustrate how the Bayesian model captures semantic properties of the content. We suggest ways in which these properties can be used as a basis for intuitive content-based access to movie libraries.