A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a current-reused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the current-reused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum \(S_{21}\) gain of 11.4 dB gain with a \(-\)3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the measured \(S_{11}\) and \(S_{12}\) are less than \(-\)10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.     

Design of 0.5 V voltage-combiner based OTA with 60 dB gain 250 kHz UGB in CMOS

A gain enhancement technique for a pseudo differential OTA based on voltage combiner, suitable for sub-1 V supply is presented in this letter. The proposed technique uses a G _m boosted voltage combiner. Unlike the typical voltage combiner which has an approximated gain of \(2\,\frac{{\text{V}}}{{\text{V}}}\), this voltage combiner can produce gain more than \(5\,\frac{{\text{V}}}{{\text{V}}}\). So it help us achieve nearly 60 dB DC gain with 250 kHz UGB for the pseudo differential OTA at a capacitive load of 10 pF. Power dissipation is very low i.e. 716 nW at supply of 0.5 V. So as to facilitate maximum swing at 0.5 V supply and lower the power consumption, MOS transistors are biased in weak/moderate inversion. The OTA is designed in standard 45 nm CMOS process. Phase margin of is more than \(55^{\circ }\) for a typical load of 10 pF. The input referred noise is \(150\,\upmu {\text{V}}{/}\sqrt{{\text{Hz}}}\) at 10 Hz and slew rate \(0.02\,{\text{V}}{/}\upmu{\text{s}}\) for 10 pF load.     

A multi-band low noise amplifier with strong immunity to interferers

A multi-band low noise amplifier (LNA) is designed to operate over a wide range of frequencies (with center frequencies at 1.2, 1.7 and 2.2 GHz respectively) using an area efficient switchable \(\pi\) network. The LNA can be tuned to different gain and linearity combinations for different band settings. Depending upon the location of the interferers, a specific band can be selected to provide optimum gain and the best signal-to-intermodulation ratio. This is accomplished by the use of an on-chip built-in-self-test circuit. The maximum power gain of the amplifier is 19 dB with a return loss better than 10 dB for 7 mW of power consumption. The noise figure is 3.2 dB at 1 GHz and its third-order intercept point (\(IIP_3\)) ranges from ?15 to 0 dBm. Implemented in a 0.13 \(\upmu\)m CMOS technology, the LNA occupies an active area of about 0.29 mm\(^2\). This design can be used for cognitive radio and other wideband applications, which require a dynamic configuration of the signal-to-intermodulation ratio, when sufficient information about the power and the location of the interferers is not available.     

5.18–7.42 GHz LC-VCO in subthreshold regime with low power low phase noise and immunity to PVT variations in 130 nm CMOS technology

In this paper, we propose an LC-VCO using automatic amplitude control and filtering technique to eliminate frequency noise around 2\(\omega _0\). The LC-VCO is designed with TSMC 130 nm CMOS RF technology, and biased in subthreshold regime in order to get more negative transconductance to overcome the losses in the LC-Tank and achieve less power consumption. The designed VCO operates at 5.17 GHz and can be tuned from 5.17 to 7.398 GHz, which is corresponding to 35.5% tuning range. The VCO consumes through it 495–440.5 \(\upmu\)W from 400 mV dc supply. This VCO achieves a phase noise of \(-\,122.3\) and \(-\,111.7\) dBc/Hz at 1 MHz offset from 5.17 and 7.39 GHz carrier, respectively. The calculated Figure-of-merits (FoM) at 1 MHz offset from 5.17 and 7.39 GHz is \(-\,199.7\) and \(-\,192.4\) dBc/Hz, respectively. And it is under \(-\,190.5\) dBc/Hz through all the tuning range. The FoM\(_T\) at 1 MHz offset from 5.17 GHz carrier is \(-\,210.6\) dBc/Hz. The proposed design was simulated for three different temperatures (\(-\,55\), 27, \(125\,^{\circ }\hbox {C}\)), and three supply voltages (0.45, 0.4, 0.35 V), it was concluded that the designed LC-VCO presents high immunity to PVT variations, and can be used for multi-standard wireless LAN communication protocols 802.11a/b/g.     

A 3.1–10.6 GHz UWB LNA Based on Self Cascode Technique for Improved Bandwidth and High Gain

In this work, we present a self cascode based ultra-wide band (UWB) low noise amplifier (LNA) with improved bandwidth and gain for 3.1–10.6 GHz wireless applications. The self cascode (SC) or split-length compensation technique is employed to improve the bandwidth and gain of the proposed LNA. The improvement in the bandwidth of SC based structure is around 1.22 GHz as compared to simple one. The significant enhancement in the characteristics of the introduced circuit is found without extra passive components. The SC based CS–CG structure in the proposed LNA uses the same DC current for operating first stage transistors. In the designed UWB LNA, a common source (CS) stage is used in the second stage to enhance the overall gain in the high frequency regime. With a standard 90 nm CMOS technology, the presented UWB LNA results in a gain \(\hbox {S}_{21}\) of \(20.10 \pm 1.65\,\hbox {dB}\) across the 3.1–10.6 GHz frequency range, and dissipating 11.52 mW power from a 1 V supply voltage. However, input reflection, \(\hbox {S}_{11}\), lies below \(-\,10\) dB from 4.9–9.1 GHz frequency. Moreover, the output reflection (\(\hbox {S}_{22}\)) and reverse isolation (\(\hbox {S}_{12}\)), is below \(-\,10\) and \(-\,48\) dB, respectively for the ultra-wide band region. Apart from this, the minimum noise figure (\(\hbox {NF}_{min}\)) value of the proposed UWB LNA exists in the range of 2.1–3 dB for 3.1–10.6 GHz frequency range with a a small variation of \(\pm \,0.45\,\hbox {dB}\) in its \(\hbox {NF}_{min}\) characteristics. Linearity of the designed LNA is analysed in terms of third order input intercept point (IIP3) whose value is \(-\,4.22\) dBm, when a two tone signal is applied at 6 GHz with a spacing of 10 MHz. The other important benefits of the proposed circuit are its group-delay variation and gain variation of \(\pm \,115\,\hbox {ps}\) and \(\pm \,1.65\,\hbox {dB}\), respectively.     

High-Accuracy Time-Mode Duty-Cycle-Modulation-Based Temperature Sensor for Energy-Efficient System Applications

This paper presents a new time-mode duty-cycle-modulation-based high-accuracy temperature sensor. Different from the well-known \({\varSigma }{\varDelta }\) ADC-based readout structure, this temperature sensor utilizes a temperature-dependent oscillator to convert the temperature information into temperature-related time-mode parameter values. The useful output information of the oscillator is the duty cycle, not the absolute frequency. In this way, this time-mode duty-cycle-modulation-based temperature sensor has superior performance over the conventional inverter-chain-based time domain types. With a linear formula, the duty-cycle output streams can be converted into temperature values. The design is verified in 65nm standard digital CMOS process. The verification results show that the worst temperature inaccuracy is kept within 1\(\,^{\circ }\mathrm{C}\) with a one-point calibration from \(-\)55 to 125 \(^{\circ }\mathrm{C}\). At room temperature, the average current consumption is only 0.8 \(\upmu \)A (1.1\(\,\upmu \)A in one phase and 0.5 \(\upmu \)A in the other) with 1.2 V supply voltage, and the total energy consumption for a complete measurement is only 0.384 \({\hbox {nJ}}\).     

An integrated charge-transfer relaxation oscillator without comparator

This letter presents a charge-transfer relaxation oscillator that achieves ultra-low power operation without comparator. The oscillator is implemented by charging or discharging the negative plate of the capacitor to a reference voltage through charge-transfer technique and the positive plate of the capacitor by a constant reference current, respectively. A special sawtooth waveform is generated, and a pseudo-inverter chain with delay compensation is adopted to determine the oscillation state. In the proposed structure, a conventional comparator has been eliminated to avoid comparator offset effect. The oscillator has been implemented with TSMC 0.18 \(\upmu \)m CMOS process. The circuit operates in subthreshold region and consumes a total power of 85 nW. The circuit demonstrates a frequency variation less than 0.8%/V over 1.2–1.8 V, leading to a temperature coefficient of 33 ppm/\(^{\circ }\)C over ? 40 to 80 \(^{\circ }\)C.     

A SiGe:C BiCMOS dual down converter for MIMO wireless infrastructure with configurable current consumption and linearity

This paper presents a dual RF down converter suitable for Multiple-Input and Multiple-Output infrastructure applications. The proposed architecture features a CMOS tapered buffer as local oscillator driver with a programmable supply voltage, provided by an embedded low dropout regulator. This approach allows scaling current consumption depending on linearity requirements. The RF path uses a balun with programmable tuning capacitors for single-to-differential signal conversion and \(50\text{-}\Omega\) input matching. A MOSFET passive mixer and a high-voltage (5 V) bipolar intermediate frequency amplifier complete the signal path. The circuit is fabricated in a SiGe:C BiCMOS process, occupies an area of \(2.8\, \text{mm} \, \times \, 2.5\, \text{mm}\), and has been assembled in a \(6\, \text{mm} \, \times \,6\, \text{mm}\), 40-pin, quad flat no-lead (QFN) package.     

An Ultra-Low-Power Integrated RF Energy Harvesting System in 65-nm CMOS Process

In recent years, radio frequency (RF) energy harvesting systems have gained significant interest as inexhaustible replacements for traditional batteries in RF identification and wireless sensor network nodes. This paper presents an ultra-low-power integrated RF energy harvesting circuit in a SMIC 65-nm standard CMOS process. The presented circuit mainly consists of an impedance-matching network, a 10-stage rectifier with order-2 threshold compensation and an ultra-low-power power manager unit (PMU). The PMU consists of a voltage sensor, a voltage limiter and a capacitor-less low-dropout regulator. In the charge mode, the power consumption of the proposed energy harvesting circuit is only 97 nA, and the RF input power can be as low as \(-\)21.4 dBm \((7.24\,\upmu \hbox {W})\). In the burst mode, the device can supply a 1.0-V DC output voltage with a maximum 10-mA load current. The simulated results demonstrate that the modified RF rectifier can obtain a maximum efficiency of 12 % with a 915-MHz RF input. The circuit can operate over a temperature range from \(-40\hbox { to }125\,^{\circ }\hbox {C}\) which exceeds the achievable temperature performance of previous RF energy harvesters in standard CMOS process.     

A Reduced-sp-$$\hbox {D3L}_{\mathrm{sum}}$$ Adder-Based High Frequency $$4\times 4$$4×4 Bit Multiplier Using Dadda Algorithm

A low-power, high-speed \(4\times 4\) multiplier using Dadda algorithm is proposed. The full adder blocks used in this multiplier have been designed using reduced-split precharge-data driven dynamic sum logic. Flip flops used in the pipeline registers have been designed to increase input signal noise margin, resulting in the minimization of output signal glitches. The multiplier circuit is implemented in 1P-9M Low-K UMC 90nm CMOS process technology. Post-layout simulations are carried out using Cadence Virtuoso. The proposed multiplier operates at a clock frequency of 3.5 GHz, with an average dynamic power consumption of 1.096 mW at a temperature of \(27\,^{\circ }\hbox {C}\) and 1 V supply voltage and occupies a chip area of \(76\,\upmu \hbox {m}\times 102\,\upmu \hbox {m}\).     

A continuous-time delta-sigma ADC for portable ultrasound scanners

A fully differential fourth-order 1-bit continuous-time delta-sigma ADC designed in a 65 nm process for portable ultrasound scanners is presented in this paper. The circuit design, implementation and measurements on the fabricated die are shown. The loop filter consists of RC-integrators, programmable capacitor arrays, resistors and voltage feedback DACs. The quantizer contains a pulse generator, a high-speed clocked comparator and a pull-down clocked latch to ensure constant delay in the feedback loop. Using this implementation, a small and low-power solution required for portable ultrasound scanner applications is achieved. The converter has a supply voltage of 1.2 V, a bandwidth of 10 MHz and an oversampling ratio of 16 leading to an operating frequency of 320 MHz. The design occupies a die area of \(0.0175\hbox { mm}^2\). Simulations with extracted parasitics show a SNR of 45.2 dB and a current consumption of \(489 \,\upmu \hbox {A}\). However, by adding a model of the measurement setup used, the performance degrades to 42.1 dB. The measured SNR and current consumption are 41.6 dB and \(495\,\upmu \hbox {A}\), which closely fit with the expected simulations. Several dies have been measured, and an estimation of the die spread distribution is given.     

A 90-nm CMOS 800 MHz 2$$\times$$VDD output buffer with leakage detection and output current self-adjustment

This work presents a 800 MHz 2\(\times\)VDD output buffer with PVTL (Process, Voltage, Temperature, Leakage) detection techniques to reduce slew rate (SR) variation. The threshold voltage (Vth) of MOS transistors varying with PVT is detected such that Output buffer will turn on different current paths correspondingly to decrease or increase the compensation current. Moreover, the slew rate is adjusted by Delay buffer and the leakage current sensor which compensates the dynamic and static currents, respectively. Most important of all, a deterministic sizing optimization method for the output transistors is reported and analyzed. The proposed design realized using a typical 90 nm CMOS process shows that the maximum data rate is 450/800 MHz given supply voltage 1.0/1.8 V with PCB and SMA connectors . The SR variation is reduced over 43% after the compensation of the leakage detection. The core area of the prototype is 0.056 \(\times\) 0.439 mm\(^2\), and the power consumption is 68.9/98.5 (\(\upmu\)W/MHz) at 450/800 MHz, respectively.     

An Improved-Linearity,Single-Stage Variable-Gain Amplifier Using Current Squarer for Wider Gain Range

A novel single-stage variable-gain amplifier (VGA) based on transconductance \(g_{m}\)-ratio amplifier is analyzed and designed with wider linear-in-dB gain range and improved linearity. The variable-gain amplifier proposed here consists of an exponential control block, a current squarer and an amplifier block with both input and load degeneration. With the help of current squarer which gets square function of the output current from exponential control block, the VGA achieves the maximum linear gain range in single stage. Current squarer is proposed, which is designed with compensation technique to minimize the second-order effect caused by carrier mobility reduction in short channel MOSFET. To avoid the poor linearity performance of the \(g_{{m}}\)-ratio amplifiers, the distortion is analyzed and the linearity is improved by applying input and load degenerating technique. At the same power consumption, the input 1 dB compression point can be improved by nearly 8.78 dB. Simulation results show that the VGA can provide a gain variation range of 64.09 dB (from \(-35.59\) to 28.5 dB) with a 3-dB bandwidth from 47 to 640 MHz. The circuit consumes the maximum power 3.5 mW from a 1.8-V supply.     

Design of minimally invasive all-pole analog lowpass filters

In this paper, a new design technique for designing higher order minimally invasive lowpass filters is proposed. The proposed fully differential filter has been simulated in TSMC 130 nm technology for third and fourth orders. When compared with the conventional filter implementations such as a Tow-Thomas architecture, the proposed third order solution achieves a total in-band input-referred integrated noise of \(44.09\,\upmu V\) compared to \(78.83\,\upmu V\), achieved by a Tow-Thomas implementation. The proposed solution offers higher tolerance to blockers along with lesser number of active devices required. Though, the total capacitance used is increased from 23.82 pF to 89.82 pF, from third order Tow-Thomas filter to its minimally invasive filter counterpart, the power consumption reduces by \(77\,\%\) from third order Tow-Thomas to the third order minimally invasive filter.     

A Low-Voltage Fully Differential Pure Current Mode Current Operational Amplifier

In this paper a novel high-frequency fully differential pure current mode current operational amplifier (COA) is proposed that is, to the authors’ knowledge, the first pure MOSFET Current Mode Logic (MCML) COA in the world, so far. Doing fully current mode signal processing and avoiding high impedance nodes in the signal path grant the proposed COA such outstanding properties as high current gain, broad bandwidth, and low voltage and low-power consumption. The principle operation of the block is discussed and its outstanding properties are verified by HSPICE simulations using TSMC \(0.18\,\upmu \hbox {m}\) CMOS technology parameters. Pre-layout and Post-layout both plus Monte Carlo simulations are performed under supply voltages of \(\pm 0.75\,\hbox {V}\) to investigate its robust performance at the presence of fabrication non-idealities. The pre-layout plus Monte Carlo results are as; 93 dB current gain, \(8.2\,\hbox {MHz}\,\, f_{-3\,\text {dB}}, 89^{\circ }\) phase margin, 137 dB CMRR, 13 \(\Omega \) input impedance, \(89\,\hbox {M}\Omega \) output impedance and 1.37 mW consumed power. Also post-layout plus Monte Carlo simulation results (that are generally believed to be as reliable and practical as are measuring ones) are extracted that favorably show(in abovementioned order of pre-layout) 88 dB current gain, \(6.9\,\hbox {MHz} f_{-3\text {db}} , 131^{\circ }\) phase margin and 96 dB CMRR, \(22\,\Omega \) input impedance, \(33\,\hbox {M}\Omega \) output impedance and only 1.43 mW consumed power. These results altogether prove both excellent quality and well resistance of the proposed COA against technology and fabrication non-idealities.     

A 0.36 μW/channel recorder for external ambulatory ECG recorders

There is an increasing demand for long-term ECG monitoring applications which are very low power, small size and capable of wireless data transmission. This paper presents an analog front-end and also modulator for long-term ECG recording purpose. The fully integrated system features three independent channels and a modulator. The analog front-end includes a voltage-to-time conversion and a tunable modulator to achieve a very low power consumption for wireless transmission of the data without analog to digital converter. The proposed system is designed and simulated in a \(0.18\,\upmu \hbox {m}\) CMOS technology and occupies only \(0.245\,\mathrm{mm}^{2}\). It can record ECG signal with 9.2-bit resolution while consuming only \(0.36\,\upmu {\mathrm{W}}\) per channel from a 0.9 V supply. Also, it can transmit data consuming just \(0.72\,{\upmu }\mathrm{W}\) per channel from a 0.9 V supply. The input referred noise of the readout channel is \(2.01\,\upmu {\mathrm{V}}_{{{\rm rms}}}\).     

Design and Implementation of Computationally Efficient Image Compressor for Wireless Capsule Endoscopy

An image compressor inside wireless capsule endoscope should have low power consumption, small silicon area, high compression rate and high reconstructed image quality. Simple and efficient image compression scheme, consisting of reversible color space transformation, quantization, subsampling, differential pulse code modulation (DPCM) and Golomb–Rice encoding, is presented in this paper. To optimize these methods and combine them optimally, the unique properties of human gastrointestinal tract image are exploited. Computationally simple and suitable color spaces for efficient compression of gastrointestinal tract images are proposed. Quantization and subsampling methods are optimally combined. A hardware-efficient, locally adaptive, Golomb–Rice entropy encoder is employed. The proposed image compression scheme gives an average compression rate of 90.35 % and peak signal-to-noise ratio of 40.66 dB. ASIC has been fabricated on UMC130nm CMOS process using Faraday high-speed standard cell library. The core of the chip occupies 0.018 mm\(^2\) and consumes 35 \(\upmu {\text {W}}\) power. The experiment was performed at 2 frames per second on a \(256\times 256\) color image. The power consumption is further reduced from 35 to 9.66 \(\upmu \)W by implementing the proposed image compression scheme using Faraday low-leakage standard cell library on UMC130nm process. As compared to the existing DPCM-based implementations, our realization achieves a significantly higher compression rate for similar area and power consumption. We achieve almost as high compression rate as can be achieved with existing DCT-based image compression methods, but with an order of reduced area and power consumption.     

Ultra-Fast Current Mode Sense Amplifier for Small $$I_{\mathrm{CELL}}$$ SRAM in FinFET with Improved Offset Tolerance

In this paper, a novel, high-performance and robust sense amplifier (SA) design is presented for small \(I_\mathrm{CELLl}\) SRAM, using fin-shaped field effect transistors (FinFET) in 22-nm technology. The technique offers data-line-isolated current sensing approach. Compared with the conventional CSA (CCSA) and hybrid SA (HSA), the proposed current feed-SA (CF-SA) demonstrates 2.15\(\times \) and 3.02\(\times \) higher differential current, respectively, for \({V}_{\mathrm{DD}}\) of 0.6 V. Our results indicate that even at the worst corner, CF-SA can provide 2.23\(\times \) and 1.7\(\times \) higher data-line differential voltage compared with CCSA and HSA, respectively. Further, 66.89 and 31.47 % reductions in the cell access time are achieved compared to the CCSA and HSA, respectively, under similar \(I_\mathrm{CELLl}\) and bit-line and data-line capacitance. Statistical simulations have proved that the CF-SA provides high read yield with 32.39 and 22.24 % less \(\upsigma _{\mathrm{Delay}}\). It also offers a much better read effectiveness and robustness against the data-line capacitance as well as \({V}_{\mathrm{DD}}\) variation. Furthermore, the CF-SA is able to tolerate a large offset of the input devices, up to 80 mV at \({V}_{\mathrm{DD}}=0.6\hbox {V}\).     

Ab␣Initio Study of Aluminium Impurity and Interstitial-Substitutional Complexes in Ge Using a Hybrid Functional (HSE)

The results of an ab?initio modelling of aluminium substitutional impurity (\({\hbox {Al}}_{\rm Ge}\)), aluminium interstitial in Ge [\({\hbox {I}}_{\rm Al}\) for the tetrahedral (T) and hexagonal (H) configurations] and aluminium interstitial-substitutional pairs in Ge (\({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\)) are presented. For all calculations, the hybrid functional of Heyd, Scuseria, and Ernzerhof in the framework of density functional theory was used. Defects formation energies, charge state transition levels and minimum energy configurations of the \({\hbox {Al}}_{\rm Ge}\), \({\hbox {I}}_{\rm Al}\) and \({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\) were obtained for ?2, ?1, 0, \(+\)1 and \(+\)2 charge states. The calculated formation energy shows that for the neutral charge state, the \({\hbox {I}}_{\rm Al}\) is energetically more favourable in the T than the H configuration. The \({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\) forms with formation energies of ?2.37 eV and ?2.32 eV, when the interstitial atom is at the T and H sites, respectively. The \({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\) is energetically more favourable when the interstitial atom is at the T site with a binding energy of 0.8 eV. The \({\hbox {I}}_{\rm Al}\) in the T configuration, induced a deep donor (\(+\)2/\(+1\)) level at \(E_{\mathrm {V}}+0.23\) eV and the \({\hbox {Al}}_{\rm Ge}\) induced a single acceptor level (0/?1) at \(E_{\mathrm {V}}+0.14\) eV in the band gap of Ge. The \({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\) induced double-donor levels are at \(E_{\rm V}+0.06\) and \(E_{\rm V}+0.12\) eV, when the interstitial atom is at the T and H sites, respectively. The \({\hbox {I}}_{\rm Al}\) and \({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\) exhibit properties of charge state-controlled metastability.     

A 0.18$$\upmu$$m CMOS voltage multiplier arrangement for RF energy harvesting

This work presents a two-stage voltage multiplier (VM) useful in RF energy harvesting based applications. The proposed circuit is based on the conventional differential drive rectifier, in which the input RF signal has been level shifted using a simple arrangement. This signal is then used to drive the next stage, which has been formed by using gate cross-coupled transistors. As a result, the load driving capability of the proposed architecture increases. The load in this work has been emulated in terms of a parallel RC circuit. The architecture has been implemented using standard 0.18 \(\mu\)m CMOS technology. The measurements of the two-stage conventional VM (CVM) and proposed VM circuits were performed at ISM frequencies 13.56, 433, 915 MHz and 2.4 GHz for R\(_L\) of values 1, 5, 10, 3 and 100 K\(\Omega\) with a fixed value of C\(_L\) equal to 20 pF. The performance evaluation has been done in terms of the power conversion efficiency (PCE) and average output DC voltage. The measured results show an improvement in PCE of 5% (minimum) for 13.56, 433 and 915 MHz frequencies, and up to 2% improvement for a frequency value of 2.4 GHz at the targeted load condition of 5 K\(\Omega ||\)20 pF, when compared with the measured results of the CVM circuit.