A novel SET/MOSFET hybrid static memory cell design

In this paper, a single electron transistor (SET)/metal-oxide-semiconductor field effect transistor (MOSFET)-based static memory cell is proposed. The negative differential conductance (NDC) characteristics of the SET block help us establish the static memory cell circuits more compactly than those in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks exhibiting the NDC. The peak-to-valley current ratio of the SET block is above four with C/sub G/=5.4C/sub T/ (C/sub T/=0.1 aF) at T=77K. The read and write operations of the proposed memory cell were validated with SET/MOSFET hybrid simulations at T=77 K. Even though the fabrication process that integrates MOSFET devices and SET blocks with NDC is not yet available, these results suggest that the proposed SET/MOSFET hybrid static memory cell is suitable for a high-density memory system.     

Dependence of DC characteristics of CNT MOSFETs on bandstructure models

Since their discovery in the early 1990s, the interest in carbon nanotube (CNT) electronics has exploded. One main factor that controls the device performance of CNT field-effect transistors (CNT MOSFETs) is the electronic structure of the nanotube. In this paper we use three different bandstructure models: 1) extended Hu/spl uml/ckel theory (EHT); 2) orthogonal p/sub z/ tight-binding (OTB); and 3) parabolic effective mass model (EFM) to investigate the bandstructure effects on the device characteristics of a CNT MOSFET using semiclassical and quantum treatments of transport. We find that, after proper calibration, the OTB model is essentially identical to the EHT over the energy range of interest. We also find that an even simpler parabolic EFM facilitates CNT MOSFET simulations within practically applied bias ranges.     

Calibration of Curie temperatures for LiTaO/sub 3/ single crystals by the LFB ultrasonic material characterization system

The line-focus-beam ultrasonic material characterization (LFB-UMC) system is applied to a standardized comparison and evaluation of the Curie temperatures, T/sub C/, exclusively used in evaluating the chemical compositions of commercial LiTaO/sub 3/ crystals by measuring the velocities of Rayleigh-type leaky surface acoustic waves (LSAWs), V/sub LSAW/. We measured V/sub LSAW/ and T/sub C/ (standardized) under the same T/sub C/ measurement conditions for 36/spl deg/Y X-LiTaO/sub 3/ single-crystal wafers produced by four manufacturers and related the results to the T/sub C/ (individual) measured by the individual manufacturers. The relationships between V/sub LSAW/ and T/sub C/ (individual) varied from one company to another, and a single straight line of the proportional relationship between V/sub LSAW/ and T/sub C/ (standardized) was obtained for all wafers regardless of the manufacturer. These experimental results clarify that the problem associated with T/sub C/ measurements lies in the measurement conditions and the absolute accuracy of the measurement instruments. Measurements of the center frequencies of SH-type surface acoustic wave (SAW) filter devices are compared with V/sub LSAW/ measurements. A method of calibrating T/sub C/ using this ultrasonic system is proposed to establish standardized specifications of SAW-device crystal wafers.     

Computational models of distributed aberration in ultrasound breast imaging

Two methods for simulation of ultrasound wavefront distortion are introduced and compared with aberration produced in simulations using digitized breast tissue specimens and a conventional multiple time-shift screen model. In the first method, aberrators are generated using a computational model of breast anatomy. In the second method, 10 to 12 irregularly shaped, strongly scattering inclusions are superimposed on the multiple-screen model to create a screen-inclusion model. Linear 2-D propagation of a 7.5-MHz planar, pulsed wavefront through each aberrator is computed using a first-order k-space method. The anatomical and screen-inclusion models reproduce two characteristics of arrival-time fluctuations observed in simulations using the digitized specimens that are not represented in simulations using the multiple-screen model: non-Gaussian first-order statistics and sharp changes in the rms arrival-time fluctuation as a function of propagation distance. The anatomical and screen-inclusion models both produce energy- level fluctuations similar to the digitized specimens, but the anatomical model more closely matches the pulse-shape distortion produced by the specimens. Both aberration models can readily be extended to 3-D, and the screen-inclusion model has the advantage of simplicity of implementation. Both models should enable more rigorous evaluation of adaptive focusing algorithms than is possible using conventional time-shift screen models.     

Standardized evaluation of chemical compositions of LiTaO3 single crystals for SAW devices using the LFB ultrasonic material characterization system

The line-focus-beam ultrasonic material characterization (LIFB-UMC) system is applied to compare and evaluate tolerances provided independently for the Curie temperature T/sub C/ and lattice constant /spl alpha/ to evaluate commercial LiTaO/sub 3/ single crystals by measuring the Rayleigh-type leaky surface acoustic wave (LSAW) velocities V/sub LSAW/. The relationships between VLSAW, and T/sub C/ and /spl alpha/ measured by individual manufacturers were obtained experimentally using 42/spl deg/YX-LiTaO/sub 3/ wafers as specimens from three crystal manufacturers. In addition, the relationship between VLSAW and SH-type SAW velocities V/sub SAW/ that are actually used for the SAW device wafers was obtained through calculations, using the chemical composition dependences of the acoustical physical constants for LiTaO/sub 3/ crystals reported previously. The result of a comparison between the T/sub C/ tolerance of /spl plusmn/3/spl deg/C and the /spl alpha/ tolerance of /spl plusmn/0.00002 nm through the common scale of VLSAW or VSAW demonstrated that the /spl alpha/ tolerance is 1.6 times larger than the T/sub C/ tolerance. Furthermore, we performed a standardized comparison of statistical data of T/sub C/ and /spl alpha/ for LiTaO/sub 3/ crystals grown by two manufacturers during 1999 and 2000, using VLSAW. The results clarified the differences of the average chemical compositions and of the chemical composition distributions among the crystal ingots between the two manufacturers. A guideline for the standardized evaluation procedure has been established for the SAW-device wafer specifications by the LFB-UMC system.     

DC and AC characteristics of sub-50-nm MOSFETs with source/drain-to-gate nonoverlapped structure

A MOSFET structure with a nonoverlapped source/drain (S/D) to gate region was proposed to overcome the challenges in sub-50-nm CMOS devices. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the spacer induces an inversion layer in the nonoverlap region to act as an extended S/D region. An oxide spacer is used to reduce parasitic gate overlap capacitance. A reasonable amount of inversion electrons were induced under the spacers. Internal physics, speed characteristics, short channel effects, and RF characteristics were studied with the nonoverlap distance at a fixed metallurgical channel length of 40 nm. The proposed structure had good drain-induced barrier lowering and V/sub T/ rolloff characteristics and showed reasonable intrinsic gate delay and cutoff frequency compared to those of an overlapped structure.     

Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation

In this paper, characterization and optimization have been performed on the 2-b floating-gate-type nonvolatile memory (NVM) cell based on a double-gate (DG) MOSFET structure using two-dimensional numerical simulation. The thickness and the difference of charge amount between programmed and erased states are found to be the crucial factors that put the NVM cell operation under optimum condition. Under fairly good conditions, the silicon thickness can reach below 30 nm while suppressing the read disturbance level within 1 V. With these results, operating schemes are investigated for both NAND - and NOR-type memory cells. This paper is based on simulation works which can give a reasonable intuition in flash memory operation. Although we adopted a floating-gate-type device since the exact modeling of Si/sub 3/N/sub 4/ used for the storage node is absent in the current numerical simulator, this helps to predict the operation of an oxide-nitride-oxide dielectric flash memory cell at a good degree.     

Fault diagnosis in electronic circuits based on bilinear transformation in 3-D and 4-D spaces

Presents two new methods of fault localization and identification in linear electronic circuits, based on a bilinear transformation in multidimensional spaces. The conventional bilinear transformation maps changes of circuit component parameters p/sub i/ into a family of p/sub i/-loci on the complex plane. The loci can be used for fault diagnosis as well as parametrical identification measurements of objects modeled by electrical circuits. The bilinear transformation method proposed by Martens and Dyck [1972] was based on the family of p/sub i/-loci on a plane. It was difficult to implement this method (called here the two-dimensional method) in practice because frequently p/sub i/-loci are situated too close to each other or superimpose one on another. The authors propose a new approach based on transferring p/sub i/-loci from a plane to three-dimensional (3-D) or four-dimensional (4-D) spaces. Distances between p/sub i/-loci in space are greater. This fact leads to better fault resolution and robustness against the influence of component tolerances and measurement errors. This approach also gives the possibility of creating p/sub i/p/sub j/-surfaces or hypersurfaces, which can be used for double-fault diagnosis or two-parameter identification measurements. The 3-D and 4-D algorithms of single- and double-fault diagnosis, and experimental verification of the 4-D method and the implementation of the 4-D method in a neural network are described.     

Monte Carlo Simulations of High-Performance Implant Free In0.3Ga 0.7As Nano-MOSFETs for Low-Power CMOS Applications

The potential performance of implant free heterostructure In_0.3Ga_0.7As channel MOSFETs with gate lengths of 30, 20, and 15 nm is investigated using state-of-the-art Monte Carlo (MC) device simulations. The simulations are carefully calibrated against the electron mobility and sheet density measured on fabricated III-V MOSFET structures with a high-kappa dielectric. The MC simulations show that the 30 nm gate length implant free MOSFET can deliver a drive current of 2174 muA/mum at 0.7 V supply voltage. The drive current increases to 2542 muA/mum in the 20 nm gate length device, saturating at 2535 muA/mum in the 15 nm gate length one. When quantum confinement corrections are included into MC simulations, they have a negligible effect on the drive current in the 30 and 20 nm gate length transistors but lower the 15 nm gate length device drive current at 0.7 V supply voltage by 10%. When compared to equivalent Si based MOSFETs, the implant free heterostructure MOSFETs can deliver a very high performance at low supply voltage, making them suitable for low-power high-performance CMOS applications     

Impact of SOI thickness fluctuation on threshold voltage variation in ultra-thin body SOI MOSFETs

Threshold voltage variation due to quantum confinement effect in ultra-thin body silicon-on-insulator (SOI) MOSFETs is examined. It is experimentally demonstrated that threshold voltage variation drastically increases when SOI layer is thinned down to 3 nm. A percolation model is used to estimate the contribution of surface roughness to V/sub th/ variation. The method to suppress the threshold voltage variation is also proposed, and around 15% reduction in threshold voltage variation is experimentally demonstrated by applying substrate bias. The reason of the suppression can be explained by quantum confinement effect induced by substrate bias.     

Recent developments in high curie temperature perovskite single crystals

The temperature behavior of various relaxor-PT piezoelectric single crystals was investigated. Owing to a strongly-curved morphotropic phase boundary, the usage temperature of these perovskite single crystals is limited by T/sub R-T/- the rhombohedral to tetragonal phase transformation temperature - which occurs at the significantly lower temperatures than the Curie temperature T/sub c/. Attempts to modify the temperature usage range of Pb(Zn/sub 1/3/Nb/sub 2/3/)O/sub 3/-PbTiO/sub 3/ (PZNT) and Pb(Mg/sub 1/3/Nb/sub 2/3/)O/sub 3/-PbTiO/sub 3/ (PMNT) rhombohedral crystals (T/sub c/ /spl sim/ 150-170/spl deg/C, T/sub R-T/ /spl sim/ 60-120/spl deg/C) using minor dopant modifications were limited, with little success. Of significant potential are crystals near the morphotropic phase boundary in the Pb(Yb/sub 1/2/Nb/sub 1/2/)O/sub 3/-PbTiO/sub 3/ (PYNT) system, with a T/sub c/ > 330/spl deg/C, even though T/sub R-T/ was found to be only half the value at /spl sim/160/spl deg/C. Single crystals in the novel BiScO/sub 3/-PbTiO/sub 3/ system offer significantly higher T/sub c/s > 400/spl deg/C, while exhibiting electromechanical coupling coefficients k/sub 33/ > 90% being nearly constant till the T/sub R-T/ temperature around 350/spl deg/C, which greatly increases the temperature range for transducer applications.     

3-D Design and Analysis of Functional NEMS-gate MOSFETs and SETs

Nanoelectromechanical system (NEMS)-gate metal- oxide-semiconductor field effect transistor (MOSFET) and single- electron transistor (SET) structures are investigated by combining 3-D design and SPICE simulation. First, the metal gate is simulated by using a 3-D simulator, which enables to design realistic 3-D device structures, and its movement is studied for different design parameters. It is demonstrated that a low stiffness design of the structure is essential for a low-voltage actuation. Results are compared with theoretical numerical simulation and a tunable capacitor model is then embedded in a SPICE simulator and coupled either with a transistor model for MOS-NEMS or with a newly developed SET analytical model for SET-NEMS. It is shown that the use of NEMS membrane can add new functionalities to conventional MOSFET and SET, such as very abrupt switching of the current, which can break theoretical limits of MOSFET, or modulation of Coulomb oscillations governing SET characteristics     

Breakdown of universal mobility curves in sub-100-nm MOSFETs

We explore the breakdown of universal mobility behavior in sub-100-nm Si MOSFETs, using a novel three-dimensional (3-D) statistical simulation approach. In this approach, carrier trajectories in the bulk are treated via 3-D Brownian dynamics, while the carrier-interface roughness scattering is treated using a novel empirical model. Owing to the high efficiency of the transport kernel, effective mobility in 3-D MOSFETs with realistic Si-SiO/sub 2/ interfaces reconstructed from a Gaussian or exponential correlation function can be simulated in a statistical manner. We first demonstrate a practical calibration procedure for the interface mobility and affirm the universal behavior in the long channel limit. Next, effective mobility in ensembles of MOSFETs with a gate length down to 10 nm is investigated. It is found that the random-discrete nature of the Si-SiO/sub 2/ interface leads to a distribution of carrier mobility below the interface, which can deviate considerably from universal mobility curves when L/sub gate/<6/spl Lambda/, where /spl Lambda/ is the correlation length for the SiO/sub 2/ interface.     

A novel NO/sub 2/ gas sensor based on Bis[phthalocyaninato] samarium complex/silicon hybrid charge-flow transistor

A new kind of sandwich-like bis[2,3,9,10,16,17,23,24-octakis(octyloxy)phthalocyaninato] samarium complex Sm[Pc/sup */]/sub 2/(Pc/sup */=Pc(OC/sub 8/H/sub 17/)/sub 8/) is used as film-forming material. Pure Sm[Pc/sup */]/sub 2/ and mixture of Sm[Pc/sup */]/sub 2/ and octadecanol(OA) deposited from both pure water and 10/sup -4/M Cd/sup 2+/ subphases are investigated. It is found that a mixture of 1:3 Sm[Pc/sup */]/sub 2/:OA forms an excellent material for the fabrication of the gas-sensing Langmuir-Blodgett (LB) film by studying the film-forming characteristics. A new gas sensor has been fabricated by incorporating the multilayer LB film into the gate electrode of a metal-oxide-semiconductor field effect transistor, forming an array of charge-flow transistor. On the application of a gate voltage (V/sub GS/), greater than the threshold voltage (V/sub TH/), a delay was observed in the response of the drain current. This is due to the time taken for the resistive gas-sensing film to charge up to V/sub GS/. This delay characteristic was found to depend on the concentration of NO/sub 2/. Results are presented showing that the device can detect reversibly the concentration of NO/sub 2/ gas down to 5 ppm at room temperature.     

A 2-D model that accounts for 3-D fringing in MEMS devices

MEMS devices such as comb drives and rotary drives are geometrically simple in that each of the components may be represented as a ‘sweep’ of a 2-D cross-section through a given height. This simplicity leads to simpler CAD requirements, geometric robustness, faster visualization, etc. Further, 3-D electrostatic simulation may be simplified to a 2-D problem over the cross-section if one neglects 3-D fringing. Such 2-D simulations provide a quick feedback to the designer on various parameters such as capacitance and electrostatic forces.However, as is well known, 3-D simulations cannot be avoided if fringing is significant, or when these devices need to be fully optimized. Such 3-D simulations unfortunately involve constructing the full 3-D geometry, volume/surface mesh, etc.In this paper, we demonstrate that one can pose and solve a 2-D problem that accounts for 3-D fringing. The proposed technique does not require the construction of the 3-D CAD model or surface/volume mesh. Instead, the 3-D electrostatics problem is collapsed to 2-D via a novel dimensional reduction method. Once the 2-D problem is solved, the full 3-D field and associated charges/forces can be recovered, as a post-processing step. The simplicity and computational efficiency of the technique lends itself well to parametric study and design optimization.     

Interaction between magnetoresistor and magnetotransistor in the longitudinal and folded vertical Hall devices

This study investigates the one-dimensional longitudinal and folded vertical Hall devices, fabricated in a standard 0.35-/spl mu/m CMOS process. The smallest nonlinearity error 0.18%, the minimum offset 0.29 mV, and the maximum supply-current-related sensitivity S/sub RI/=3.837 V/A/spl middot/T, are obtained with a 10-mA bias current excited by the supply voltage of 0.6 V. The main magnetic mechanism is that the filament current of the vertical magnetoresistor is directly injected into the base region of the bulk magnetotransistor (BMT) to increase the density of minority carriers and then enhance the magnetosensitivity. Furthermore, the induced Hall voltage of the longitudinal vertical Hall device is proportional to the bias current, but the folded vertical Hall device is inversely impacted. This advantage makes it possible to get a low-power folded vertical Hall device. The folded style not only reduces the nonlinearity error but also minimizes the offset. Unfortunately, the tradeoff is a fall in sensitivity. The BMT is applied to increase magnetic sensitivity and to compensate for this negative impact.     

50-nm fully depleted SOI CMOS technology with HfO/sub 2/ gate dielectric and TiN gate

In this paper, we demonstrate for the first time CMOS thin-film metal gate FDSOI devices using HfO/sub 2/ gate dielectric at the 50-nm physical gate length. Symmetric V/sub T/ is achieved for long-channel nMOS and pMOS devices using midgap TiN single metal gate with undoped channel and high-k dielectric. The devices show excellent performance with a I/sub on/=500 /spl mu/A//spl mu/m and I/sub off/=10 nA//spl mu/m at V/sub DD/=1.2 V for nMOSFET and I/sub on/=212 /spl mu/A//spl mu/m and I/sub off/=44 pA//spl mu/m at V/sub DD/=-1.2 V for pMOSFET, with a CET=30 /spl Aring/ and a gate length of 50 nm. DIBL and SS values as low as 70 mV/V nand 77 mV/dec, respectively, are obtained with a silicon film thickness of 14 nm. Ring oscillators with 15 ps stage delay at V/sub DD/=1.2 V are also realized.     

Optimization of single-gate carbon-nanotube field-effect transistors

The performance of Schottky-barrier carbon-nanotube field-effect transistors (CNTFETs) critically depends on the device geometry. Asymmetric gate contacts, the drain and source contact thickness, and inhomogenous dielectrics above and below the nanotube influence the device operation. An optimizer has been used to extract geometries with steep subthreshold slope and high I/sub on//I/sub off/ ratio. It is found that the best performance improvements can be achieved using asymmetric gates centered above the source contact, where the optimum position and length of the gate contact varies with the oxide thickness. The main advantages of geometries with asymmetric gate contacts are the increased I/sub on//I/sub off/ ratio and the fact that the gate voltage required to attain minimum drain current is shifted toward zero, whereas symmetric geometries require V/sub g/=V/sub d//2. Our results suggest that the subthreshold slope of single-gate CNTFETs scales linearly with the gate-oxide thickness and can be reduced by a factor of two reaching a value below 100 mV/dec for devices with oxide thicknesses smaller than 5 nm by geometry optimization.     

Chemically synthesized FePt nanoparticle material for ultrahigh-density recording

We have examined the magnetic anisotropy of the "heat-treated FePt nanoparticles" annealed in a magnetic field. The magnetic easy axis of the "heat-treated FePt nanoparticles" is found to be three-dimensional (3-D) random and a partial ordering fct structure is observed before annealing in the presence of a magnetic field. The value of M/sub r//M/sub s/ obtained is 0.5. After annealing in the presence of a magnetic field, the M-H loop indicates that the easy axis is oriented preferably in the perpendicular direction than along the in-plane direction. The value of H/sub c/(//)/H/sub c/(/spl perp/) at 10 K is 0.62 (1410 Oe/2250 Oe). The value of M/sub r//M/sub s/(/spl perp/) is 0.58 at 10 K larger than the value of M/sub r//M/sub s/(//). Therefore, a weak magnetic easy axis orientation is fundamentally possible on the chemically synthesized FePt nanoparticles. We have studied the recording characteristics of a 3-D random nanoparticle medium using a GUZIK spinstand and observed the recorded patterns for the medium by imaging with a magnetic force microscopy.