Under bump metallurgy study for Pb-free bumping

The demand for Pb-free and high-density interconnection technology is rapidly growing. The electroplating-bumping method is a good approach to meet finepitch requirements, especially for high-volume production, because to volume change of patterned-solder bumps during reflow is not so large compared with the stencil-printing method. This paper proposes a Sn/3.5 Ag Pb-free electroplating-bumping process for high-density Pb-free interconnects. It was found that a plated Sn/Ag bump becomes Sn/Ag/Cu by reflowing when Cu containing under bump metallurgy (UBM) is used. Another important issue for future flip-chip interconnects is to optimize the UBM system for high-density and Pb-free solder bumps. In this work, four UBM systems, sputtered TiW 0.2 μm/Cu 0.3 μm/electroplated Cu 5 μm, sputtered Cr 0.15 μm/Cr-Cu 0.3 μm/Cu 0.8 μm, sputtered NiV 0.2 μm/Cu 0.8 μm, and sputtered TiW 0.2 μm/NiV 0.8 μm, were investigated for interfacial reaction with electroplated Pb/63Sn and Sn/3.5Ag solder bumps. Both Cu-Sn and Ni-Sn intermetallic compound (IMC) growth were observed to spall-off from the UBM/solder interface when the solder-wettable layer is consumed during a liquid-state “reflow” process. This IMC-spalling mechanism differed depending on the barrier layer material.     

Double-level copper interconnections using selective copper CVD

Selective copper CVD technique involving hydrogen reduction of hexafluoro acetylacetonate copper has been used to fill vias for fabricating double-level copper interconnect structure. The surface morphology of selectively deposited copper on copper substrate of the via bottom depends strongly on via opening process. A two-step via opening process consisting of an reactive ion etching of the insulating interlayer and a wet removal of the interlayer metal results in smooth copper plug formation by CVD. Double-level copper interconnect structures have been fabricated using this technique and a via resistance as low as 100 mΩ has been obtained for a 1 μ diameter via.     

降低PAPR的门限双层次算法的研究

正交频分复用（OFDM）具有频谱利用率高、对抗频率选择性衰落能力强、调制解调简单及接收端无需复杂均衡技术等优势,但是其峰均功率比（PAPR）过高,为了解决这一缺点,将双层次最优搜索法与Kwon次优法的门限思想相结合,提出基于门限思想的双层次最优搜索算法。仿真证明,在优化的分组参数和辅助信息相同的环境下,基于门限思想的双层次最优搜索算法,在合理的门限条件下,大幅度地降低了系统的复杂性,其抑制峰均功率比性能的损失较小,且具有较强的实用性。     

印制板翘曲品质改善研究

随着电子产品向轻、薄、小的方向发展。印制板的封装方式也在不断的改变,这就对PCB的制造提出了更高的要求,特别是印制板的平整度要求,只有保证PCB在PCBA过程中有很高的平整度,才能保证SMD引脚与板面焊盘的焊接,才能保证SMT过程的质量(包括网印焊膏、贴片、等工序)。分析了造成翘曲问题的主要原因,从分析中可以看出,其原因是多方面的,可以说是从供应商的基板来料开始,一直到做成成品的印制板,还有在客户的SMT过程中,都有机会造成翘曲问题,就引起翘曲问题的主要原因进行研究,通过对印制板的排板结构的设计、压合工序的影响及FQC翻压工序分别进行了DOE实验研究,共进行了70多个工艺实验,对试验结果进行统计分析,找出影响翘曲的主要影响因素,并进行参数优化,达到改善翘曲品质的目的。     

Fluxless wetting propeities of one-side-coated under bump metallurgy and top surface metallurgy

The wetting balance test was performed in an attempt to estimate the fluxless wetting properties of under bump metallurgy (UBM)-coated Si-wafer and top surface metallurgy (TSM)-coated glass substrate to SnPb solder. The wetting curves of the single-and double-side-coated UBM had a similar shape and the parameters characterizing the curve shape showed a similar tendency as a function of temperature. Wetting property estimation was possible with the new wettability indices from the wetting curves of one side-coated specimens; F_min, F_s, and t_s. Au/Cu/Cr UBM was better than Au/Ni/Ti UBM from the point of wetting time. For TSM, it was more effective to use Cu as a wetting layer with Au as a protection layer than to use Au as a wetting layer alone. The contact angle of one-side-coated Si-plate to SnPb solder can be calculated from the force balance equation by measuring static state force and tilt angle. The contact angles of Au/Cu/Cr and Au/Ni/Ti UBM of Si-wafer to SnPb solder were 59.9° and 63.9°, respectively. The contact angles of Au/Cu/Cr and Au/Cr TSM of glass to SnPb were 78.9 and 76.1°, respectively.     

Under bump metallurgy study on copper/low-k dielectrics for fine pitch flip chip packaging

Because the semiconductor speed increases continuously, more usage of low-k dielectric materials to enhance the performance in Cu chips has taken place over the past few years. The implementation of copper (Cu) as an interconnect, in conjunction with the ultra-low-k materials as interlevel dielectrics or intermetal dielectrics in the fabrication of ultra-large-scale integrated circuits, has been used in the semiconductor community worldwide, especially for high-speed devices. The objective of this study is to investigate the under bump metallurgy (UBM) characterization with low-k dielectric material used in damascene Cu-integrated circuits. This paper focuses on electroless Ni/Au, Cu/Ta/Cu, and Ti/ Ni(V)/Cu/Au UBM fabrication on 8-in. damascene Cu wafers and flip chip package reliability with Pb-bearing and Pb-free solders. The interfacial diffusion study and bump shear test were carried out to evaluate the bump bonding, and the failure was analyzed with optical microscopy, scanning electron microscopy (SEM), and transmission electron microscopy (TEM). In order to investigate the thermal stability of the UBM system with Pb-free solder, high-temperature aging (above the melting temperature) was performed and each interface between the solder and UBM was observed with optical microscopy, SEM, and TEM, respectively. The failures observed and the modes are reported in the paper.     

Safety defect analysis and method study of data network

This paper cascades crash analysis and NS2 simulation analysis to study the network system hidden. It is combined with the theory of complex systems from the nodes and links in the network system vulnerability analysis. Firstly, we abstract complex network systems to the node and link network topology. And then we remove key nodes and link vulnerability analysis center between lines metrics to analyze the effect of the network functionality caused by node crashes or link crashes. Secondly, we construct a cascade collapse model, using NS2 simulation to study outside deliberate attack and simulation system failure analysis; and give the embodiment of cascading breakdown on the network function.     

PL study of oxygen defect formation in ZnO nanorods

Photoluminescence (PL) study of needle-like ZnO nanorods grown under standard and oxygen-rich conditions is presented. The yellow-orange band at ∼580 nm increases with excess oxygen during growth. Subsequent annealing in a reducing atmosphere shows the disappearance of this band. The yellow-orange emission is attributed to oxygen interstitials (O_i).     

Morphology and defect study in low pressure MOCVD grown AlGaAs

A low pressure MOCVD system has been adopted to grow AlGaAs epitaxial layer on Si-doped or S.I. GaAs substrate by using TMA, TEG and AsH₃ as the sources.The effect of temperature on the surface morphology has been studied and a defect free surface has nearly been obtained.From EPMA analysis, at lower growth temperature (<710°C), the “whiskers” which were observed in this study are composed of a region with much less aluminum content than the surrounding normal region, but gallium and arsenic contents are nearly the same. There are few “precipitate hillock” defects on the epilayers especially under low growth temperature (<720°C), in which region, the aluminum content is greater than the surrounding region but gallium and arsenic contents are less.Raising the growth temperature (>750°C), both of “whisker defect” and “precipitate hillock” are eliminated. Very few “twin faults” defects and “bird-fault” defects on the epitaxial layers grown under high growth temperature were observed.     

Double-level ball-riding robot balancing: From system design,modeling, controller synthesis,to performance evaluation

In this research, a new robot, double-level ball-riding robot, is introduced. The robot consists of an upper ball-riding subsystem and a lower ball-riding subsystem. The robot’s dynamics model can be considered separately in two identical planes. Euler–Lagrange equation of motion is applied in order to obtain the dynamics model. Motors are included in the robot’s model. The model is then linearized. The robot’s parameters are identified. The robot’s prototype is manufactured and assembled. Linear Quadratic Regulator with Integral (LQR + I) controller is proposed and applied in order to balance both levels of the robot. The complementary and orientation transformation are used to fuse sensors in order to obtain robot leaning angles. Balancing performance of the developed double-level ball-riding robot is evaluated by simulations and experiments. The results show efficient control performance of LQR + I controller.     

环形光源激发超声进行缺陷检测的数值研究

为了提高激光超声的激发效率且不对被测表面造成损伤,改变了光源的空间分布,采用脉冲激光环形光源激发超声及有限元方法,应用多物理场耦合软件,对铝板中激发的超声全场波形进行了数值模拟,研究了环形光源中轴线上叠加横波的激发特性随激光参量而变化的规律,并与点光源激发超声进行对比.通过模拟缺陷所导致超声场的变化规律,提出一种环光源...     

含缺陷光子晶体波分复用器研究

利用光子晶体的光子禁带和体积小的优点,在光子晶体中适当设计线缺陷和点缺陷,使这些缺陷会形成波导和微腔.根据耦合模理论,波导与波导及波导与微腔之间会发生耦合现象,通过调节耦合长度和微腔中心半径的大小,可以选择不同波长的光波在各信道中通过.依此原理,可以制作相应的光子晶体波分复用器.     

A statistical study of defect maps of large area VLSI IC's

Defect maps of 57 wafers containing large area VLSI IC's were analyzed in order to find a good match between the empirical distribution of defects and a theoretical model. Our main result is that the commonly employed models, most notably, the large area clustering negative binomial distribution, do not provide a sufficiently good match for these large area IC's. Only the recently proposed medium size clustering model is close enough to the empirical distribution. An even better match can be obtained either by combining two theoretical distributions or by a “censoring” procedure in which the worst chips are ignored. Another goal of the study was to find out whether certain portions of either the chip or the wafer had more defects than the others     

MLCI端电极缺陷引起的立碑问题研究

针对叠层片式电感器(MLCI)在回流焊过程中发生的立碑现象,通过对正常样品与立碑样品的SEM显微观察和对比分析,论述了MLCI本身缺陷引起的焊接立碑机理。结果表明:MLCI端电极内部银层不致密、孔洞多导致了元件回流焊时产生立碑。最后通过生产实例提出了一个解决此问题的方案。     

Charge pumping spectroscopy: HfSiON defect study after substrate hot electron injection

Spectroscopic charge pumping (CP) is used to study the evolution of the energy distribution of trapped electrons within HfSiON/SiO₂ gate stacks under substrate hot electron injection (SHEI). Base level CP measurements with large pulse amplitude allow an efficient charging/discharging of traps and reaching two defect bands in the HfSiON situated at 0.40 and 0.85 eV above the Si conduction band, respectively. Unlike standard constant voltage stress (CVS), SHEI enables full control of the stress by separately controlling the applied gate field, the injected electron energy, and the fluence. During CVS, HfSiON defects at 0.40 eV are generated. Conversely, during SHEI, either the shallow or the deep defects are preferentially created depending on the gate field as well as electron energy.     

Theoretical study of defect impact on two-dimensional MoS2

Our theoretical findings demonstrate for the first time a possibility of band-gap engineering of monolayer MoS₂ crystals by oxygen and the presence of vacancies. Oxygen atoms are revealed to substitute sulfur ones, forming stable MoS_2-xO_x ternary compounds, or adsorb on top of the sulfur atoms. The substituting oxygen provides a decrease of the band gap from 1.86 to 1.64 eV and transforms the material from a direct-gap to an indirect-gap semiconductor. The surface adsorbed oxygen atoms decrease the band gap up to 0.98 eV depending on their location tending to the metallic character of the electron energy bands at a high concentration of the adsorbed atoms. Oxygen plasma processing is proposed as an effective technology for such band-gap modifications.     

Reliability evaluations of under bump metallurgy in two soldersystems

Under bump metallurgy (UBM) reliability is one of the critical issues in the total reliability of a flip-chip bumping technology. Since the UBM materials and structures vary for different bumping technologies, the UBM strength and reliability need to be determined for each design and process. In addition, the stress that a UBM experiences during thermal cycles depends on the solder alloy used in the interconnect. Different solder alloys require different UBM structures and strengths to achieve good reliability in thermal cycling. In this study, a simplified stress model is developed to determine the UBM stress during thermal cycling. A simplified stress model for the UBM strength is also developed. These models are used to predict the stress and strength of the UBM under the die pull test and the thermal cycle conditions for both eutectic and high lead solder systems. A methodology for using the pull test results to evaluate UBM reliability is also discussed. This methodology can be extended to the studies of UBM's with other solder systems such as lead free solder systems     

镍铁铝混合粉末的激光熔覆冶金研究

为了利用高能激光束将镍、铁、铝金属单质的混合粉末快速熔融,得到高性能的镍铁铝合金,并直接用于熔覆,采用激光3-D打印的金属粉末成型的方法,用一台中低功率的光纤激光器,以工程中常用的轧制不锈钢板为基底,研究了一定比例的镍、铁、铝混合粉末的熔覆冶金情况。通过优化激光工艺参量（激光频率、扫描速率、激光功率和离焦量）组合,得到了质量良好的单道熔覆结果。通过激光共聚焦显微镜、晶相显微镜以及扫描电子显微镜等检测手段,对熔覆条的宏观形貌和微观组织进行观察。结果表明,可获得良好的无气孔无裂纹的合金组织,且合金与基板形成了良好的冶金结合;熔覆层硬度低于基板硬度30HV左右,但截面硬度分布均匀。该研究有助于得到各向性质统一的冶金层。