Tree structure for mismatch noise-shaping multibit DAC

A tree structure for the efficient implementation of segment selection in a multibit oversampled DAC is presented. The structure offers high-order noise-shaping of mismatch errors without the use of vector quantisation and so can be implemented in low silicon area     

Mismatch shaping for a current-mode multibit delta-sigma DAC

Mismatch shaping allows the use of multibit quantization in delta-sigma analog-to-digital converters and digital-to-analog converters (DAC's) since it noise-shapes the error caused by static element mismatch in a multibit DAC. In this paper, mismatch-shaping techniques for low-pass delta-sigma (ΔΣ) modulators are reviewed, and a mismatch-shaping technique for bandpass ΔΣ modulators is described. The dynamic error caused by frequent element switching is identified as a major source of error in a current-mode DAC with a continuous-time output. Modifying the mismatch-shaping algorithm to account for this effect yields a continuous-time ΔΣ DAC that is insensitive to both element mismatch and element switching dynamics. Experimental results confirm the effectiveness of the proposed techniques     

Digital implementation of mismatch shaping in oversampled pipelineA/D converters

Pipeline A/D converters are usually implemented with switched capacitor technology. The effect of gain errors caused by capacitor mismatch may be attenuated using mismatch-shaping techniques. The author introduces an architecture that improves the SFDR of a particular pipeline A/D converter, simply by adding digital hardware to the existing analogue design     

Oversampled pipeline A/D converters with mismatch shaping

This paper presents a pipeline analog-to-digital converter (ADC) with improved linearity. The linearity improvement is achieved through a combination of oversampling and mismatch shaping, which modulates the distortion energy out of band. Mismatch shaping can be realized in a traditional 1-bit/stage pipeline ADC, but the ADCs transfer characteristic properties limit its effectiveness at pushing the distortion out of band. These limitations can be alleviated by using a 1-bit/stage commutative feedback capacitor switching pipeline design. A test chip was fabricated in a 0.35-μm CMOS process to demonstrate mismatch shaping. Experimental results obtained indicate that the spurious-free dynamic range improves by 8.5 dB to 76 dB when mismatch shaping is used at an oversampling ratio of 4 and a sampling rate of 61 MHz. The signal-to-noise and distortion ratio improves by 3 dB and the maximum integral nonlinearity decreases from 1.8 to 0.6 LSB at the 12-bit level     

Oversampled pipeline A/D converters with mismatch shaping

The authors present a pipeline A/D converter with improved linearity (SNDR). The SNDR improvement is achieved through a combination of oversampling and mismatch shaping, which modulates the distortion energy out-of-band. At an oversampling ratio of four and 64, and a component mismatch of 0.1%, 9 and 35 dB improvements in SNDR are achieved, respectively, in comparison to a converter with no mismatch shaping     

Beam shaping to suppress phase mismatch in high power second-harmonic generation

A deliberate pattern of distributing the radiation energy of a high power laser can minimize the steady-state thermal gradients in a nonlinear crystal, thus permitting a large increase of the average powers of such systems. The theory of the two main techniques of beam shaping-fanning and scanning-is developed. Results of several experiments based on this theory are given. Experimental techniques, including some not yet attempted, are discussed.     

A bound on mean-square estimation error with background parameter mismatch

In typical parameter estimation problems, the signal observation is a function of the parameter set to be estimated as well as some background (environmental/system) parameters assumed known. The assumed background could differ from the true one, leading to biased estimates even at high signal-to-noise ratio (SNR). To analyze this background mismatch problem, a Ziv-Zakai-type lower bound on the mean-square error (MSE) is developed based on the mismatched likelihood ratio test (MLRT). At high SNR, the bound incorporates the increase in MSE due to estimation bias; at low SNR, it includes the threshold effect due to estimation ambiguity. The kernel of the bound's evaluation is the error probability associated with the MLRT. A closed-form expression for this error probability is derived under a random signal model typical of the bearing estimation/passive source localization problem. The mismatch is then analyzed in terms of the related ambiguity functions. Examples of bearing estimation with system (array shape) mismatch demonstrate that the developed bound describes the simulations of the maximum-likelihood estimate well, including the sidelobe-introduced threshold behavior and the bias at high SNR.     

Bit error rate reduction by power shaping in WDM networks with EDFAs

The trend in multi-wavelength optical networks is toward dynamic route and wavelength assignment to support burst-switching or packet switching. Where erbium-doped optical amplifiers (EDFAs) are used for multi-wavelength amplifications, the time interval between traffic blocks can be long enough to induce EDFA optical power transients created by abrupt changes in the average input power to the EDFAs and can adversely affect the performance of the network. To mitigate the effects of EDFA optical power transients on optical networks, a method based on power shaping where heads and tails are joined to the beginning and end of a traffic block is proposed. A head (tail) gradually increases (decreases) the channel power by employing a pseudo-random bit sequence in which the probability of a “1” (“0”) increases from 0 to 0.5. This paper reports experimental results showing that EDFA optical power transients can be significantly reduced with adequate shaping periods. The effects of alternative shaping profiles are examined, and for a linear shaping profile, experiments show that the drop transient deviation is reduced by 0.5 dB while the add transient deviation is reduced by 0.71 dB. We show by lab experiments that the bit error rate induced by wavelength add-drop transients in a chain of EDFAs in an emulated fiber network can be reduced by 25% using power shaping techniques. Power shaping is an economical means of suppressing EDFA optical power transients compared to other physical layer approaches that require the addition of specialized components and can be applied to EDFAs as well as other solid-state and Raman optical amplifiers.     

Design of multibit noise-shaping data converters

A synthesis methodology for selecting locations of thez-domain poles for noise-shaping coders that use multibit internal converters is presented. A key aspect of the proposed methodology is the use of the |L|₁ norm of the noise transfer function to guarantee stability rather than the power gain or |L|₂ norm which is commonly used in the design of 1-bit noise-shaping coders. Simulation verifies that the performance predicted by the new method is within a few dBs of the actual performance. In addition, two hand-designed loop filters from the literature are compared with designs generated by the proposed method.     

Vulnerability of multibit clock-controlled cascades to inversionattack

The inversion attack on nonlinear filter generators is adapted to deal with cascades of clock-controlled shift registers with multibit outputs. It is shown that under certain conditions such cascades may be vulnerable to these attacks     

Digital compensation of DAC mismatches in multibit delta-sigma ADCs

A digital compensation technique to overcome the effects of the digital-to-analogue converter (DAC)'s mismatches in multibit delta- sigma modulators is described. The technique is purely digital, does not require the injection of a pilot signal and is compatible with binary-weighted element DACs. Simulation results confirm the validity of the compensation technique for a four-bit, fifth-order lowpass modulator with an oversampling ratio of 12 and 1% mismatch in the DAC elements. The compensated modulator exhibits a peak signal- to-noise-and-distortion ratio of 74.5 dB; that is within 0.5 dB of the ideal system without mismatch.     

Phase error resilience to I/Q mismatch of a simplified CPM receiver

A low complexity receiver which was devised in previous papers proved there to be quasioptimum over additive gaussian noise and also showed low power penalty with flat Rayleigh fading, i.e., with random phase, and despite the fact that one of three reduced complexity blocks of that receiver relies on symmetries on signal's phase transitions. This letter analyzes the origin of that error resilience during the derivation of the metrics.     

Efficient construction of multibit tries for IP lookup

Srinivasan and Varghese (see ACM Trans. Comput. Syst., p.1-40, 1999) have proposed the use of multibit tries to represent routing tables used for Internet (IP) address lookups. They propose dynamic programming algorithms to determine the strides of optimal multibit fixed-stride and variable-stride tries. We improve on these algorithms by providing alternative dynamic programming formulations for both fixed- and variable-stride tries. While the asymptotic complexities of our algorithms are the same as those for the corresponding algorithms of Srinivasan and Varghese, experiments using real IPv4 routing table data indicate that our algorithms run considerably faster. Our fixed-stride trie algorithm is two to four times faster on a SUN workstation and 1.5 to three times faster on a Pentium IV PC. On a SUN workstation, our variable-stride trie algorithm is between two and 17 times faster than the corresponding algorithm of Srinivasan and Varghese; on a Pentium IV PC, our algorithm is between three and 47 times faster. An added feature of our variable-stride trie algorithm is the ability to insert and delete prefixes taking a fraction of the time needed to construct an optimal variable-stride trie "from scratch".     

基于时域特性的并行系统的采样误差估计算法

为了降低并行时间交替采样系统中通道失配误差的 硬性,利用两个标准斜波 信号的时域特性,对斜波信号多次采样,采样点减去偏置误差得到的无偏置采样值,从而求 解采样点的时间误差和增益误差联立方程,计算时间和增益误差。本文算法的采样点数和推导计算量较少,是一种快速而 精确的工程实用算法;并使用Matlab对本文算法进行模拟仿真证明其可行性,并通过Farrow 结构的滤波器对估计所得的通道失配误差进行校正验证,校正后的无杂散动态范围(SFDR,spurious free dynamic range)至少达到50dB。     

New class of multibit sigma-delta modulators using multiratearchitecture

A new multibit sigma-delta modulator is presented where the analogue-to-digital converter in the forward path is replaced by an increase in the clock rate of the integrators in the final stages. Theoretical and simulation results are presented for second- and third-order modulators     

无线传感器网络差错控制技术的能效分析

对自动请求重传(ARQ)技术和前向纠错(FEC)技术的能效进行了分析,提出在无线传感器网络中使用Chase合并混合自动请求重传(HARQ)方案实现自适应差错控制,以满足无线传感器网络的不同链路对差错控制方案的差异性要求.仿真结果表明,Chase合并HARQ为整体最优的差错控制方案.     

Addressing static and dynamic errors in unit element multibit DACs

Nonlinearity in multibit current-steering digital-to-analogue converters (DACs) originates from static mismatch and switching imperfections. Several techniques are presented to avoid this nonlinearity. When applied, the DACs are suitable for use in the feedback of continuous-time /spl Sigma//spl Delta/-converters.     

Evaluation of multibit upsets in integrated circuits under heavy charged particles

The results of computational modeling of the ionization response in VLSI elements under the ingress of a separate charged particle into its passive or active region are presented. In this study, the conditions for the appearance of multibit upsets, which are formed due to the diffusion collection mechanism of the excess charge, are substantiated. It is shown that the maximal VLSI sensitivity to multiple since upsets occurs with the ingress of a nuclear particle into passive regions arranged equidistantly from the location of a nuclear particle.     

SEP performance of coherent MPSK over fading channels in the presence of phase/quadrature error and I-Q gain mismatch

This letter presents a joint approach to the symbol-error probability (SEP) of coherent M-ary phase-shift keying in a situation where the phase error, quadrature error, and in-phase-quadrature (I-Q) gain mismatch problems take place all concurrently over an additive white Gaussian noise and arbitrary fading channel. A set of equations that characterizes the conditional SEP on an instantaneous fading signal-to-noise ratio is derived in the form of the Craig representation.