A High-Performance Polysilicon Thin-Film Transistor Built on a Trenched Body

In this paper, a high-performance polysilicon thin-film transistor (poly-Si TFT) with a trenched body is proposed, fabricated, and studied. This new trenched TFT can be easily produced by filling and etch-back technology without destroying the channel film quality. The addition of the body trench is found to reduce the off-state leakage current by 70% on average, because the trench induces a carrier scattering effect in the poly-Si grain-boundary traps, thereby affecting the leakage path. Although the off-state current is substantially reduced, the on-state current is comparable with that of a conventional TFT. Our multiple-trenched-body TFT is also shown to improve the breakdown voltage by 11%.      

Enhanced Hot Spot Cooling Using Bonded Superlattice Microcoolers With a Trench Structure

In this paper, we describe how to use Si/SiGe superlattice microcoolers to cool the target hot spots and how a trench structure could enhance its cooling performance. The microcooler chip is gold fusion bonded with a 65 $mu{hbox {m}}$ -thick silicon chip, where heaters are fabricated on the opposite of fusion bonding layer to simulate the hot spots. Our 3-D electrothermal simulations showed that with a trench structure, the maximum cooling and cooling power density could be doubled at hot spot region. Our experimental prototype also demonstrated a maximum cooling of ${sim 2}~^{circ} {hbox {C}}$ reduction at hot spot or a maximum cooling power density of 110 $~{hbox {W/cm}}^{2}$ with trench structure as compared with the 0.8 $^{circ}{hbox {C}}$ cooling without trench structure. This two-chip bonded configuration will allow the integration of spot coolers and ICs without impact on microelectronics processing process. It could be a potential on-chip hot spot cooling solution.      

Shielding region effects on a trench gate IGBT

In this paper we introduced the shielding region concept in order to relieve the electric field concentrated on the trench bottom corner. The shielded trench gate insulated gate bipolar transistor (IGBT) is a trench gate IGBT with a P+shielding region located in the bottom of a trench gate. By simulation results, we verified that a shielding region reduced the electric fields not only in the gate oxide but also in the P-base region. Compared with conventional trench gate IGBT, about 33% increment of forward breakdown voltages are achieved, but little forward voltage drop, which causes on-state loss to be increased by about 0.06 V in the shielded trench gate IGBT.     

Nearly bird's beak-free local oxidation technology for controlled dielectric formation in deep silicon trenches

Silicon deep trench isolation technology using local oxidation is reported. Scaled, high-density trench capacitors were fabricated with varying trench aspect ratios. Nearly bird's beak-free local oxidation resulted in a controlled growth of silicon dioxide on the trench bottom surfaces and significantly improved the trench gate MOS isolation characteristics. Detailed MOS capacitance measurements were performed and wafer yield in excess of 90% was demonstrated across 4 inch diameter silicon wafers.<>     

The optimization of deep trench isolation structure for high voltage devices on SOI substrate

In this paper, the process and layout optimizations for improving the isolation performance of deep trench structures on SOI substrate are proposed. In the view of process flow, the reasons for forming weak points (located at the trench bottom) in deep trench structure are analyzed. In order to solve this problem of the weak points, a method of etching partial buried oxide after etching silicon is put forward, which can increase the thickness of isolation oxide at trench bottom by 10-20%. In aspect of layout structure, a voltage drop model of double trench structures is presented and verified by the experimental results, which indicates that breakdown voltage of double trench is a function of trench spacing. It is noted that the minimum trench spacing allowed by the process design rule can ensure superior isolation capability for double trench structure. Both methods for improving the performance of the device have also been verified in 0.5 μm HV SOI technology.     

射频功率LDMOS槽形漂移区结构优化设计

对射频功率LDMOS槽形漂移区的结构进行了优化设计.基于射频功率LDMOS的频率特性,提出了矩形、倒三角形和正三角形槽结构,对槽的位置、深度、宽度进行分析,在满足相同的耐压和导通电阻条件下,得出最优结构为正三角形槽结构,该结构实现了最大程度地减小寄生反馈电容的目的,寄生反馈电容减小了24%,LDMOS的截止频率提高了15%.     

Trench SJ IGBT 的仿真研究

本文对沟槽型超结绝缘栅双极晶体管(trench SJ IGBT)进行了全面的分析,并通过Sentaurus TCAD仿真软件将其与沟槽型场截止绝缘栅双极晶体管(trench FS IGBT)进行了详尽的对比,仿真结果显示,在相同的条件下与trench FS IGBT 相比,trench SJ IGBT 的击穿电压提高了100 V,饱和导通压降降低了0.2 V,关断损耗减少了50%。最后,文章研究了电荷不平衡对trench SJ IGBT 的动静态参数的影响。对各参数和它们对电荷不平衡的灵敏度之间的折中进行了讨论。     

Recessed gate-data line-crossover structures employing an air-gapto reduce signal delay for TFT-LCD panel

Two new line-crossover structures entitled "recessed air-bridge structure" and "recessed gate-line structure," which have improved mechanical durability and reduced data-tine signal delay in active matrix liquid crystal display (AMLCD) panel, have been proposed and fabricated. In the recessed air-bridge structure, the air-gap line-crossover is located at the bottom of the oxide trench so that the floated upper lines lie flush with the panel's surface. The recessed gate-line structure was fabricated by recessing the whole gate-line into the bottom of an oxide trench. Both of the fabricated structures, without any passivation layer, were proved sufficiently robust to withstand a rubbing process, which applied realistic mechanical stresses to the AMLCD panel. Experimental results show that the signal delays of the proposed structure are less than about 20% of the conventional structure     

射频功率LDMOS槽形漂移区结构优化设计

对射频功率LDMOS槽形漂移区的结构进行了优化设计.基于射频功率LDMOS的频率特性,提出了矩形、倒三角形和正三角形槽结构,对槽的位置、深度、宽度进行分析,在满足相同的耐压和导通电阻条件下,得出最优结构为正三角形槽结构,该结构实现了最大程度地减小寄生反馈电容的目的,寄生反馈电容减小了24%,LDMOS的截止频率提高了15%.     

High-voltage lateral trench gate SOI-LDMOSFETs

We present a lateral trench gate SOI-LDMOSFET that uses narrow trenches as channels. The lateral trench gate, which allows the channel current to flow laterally on the trench side walls, decreases its on-resistance because it increases the current spreading area of the device. The specific on-resistance (R_sp) strongly depends on the trench depth, which affects the channel area on the side wall of the trench and the space between the trenches affects the channel density of the device. The R_sp of the suggested devices as a function of the lateral trench depth and the space between the trenches are studied. Three-dimensional numerical simulations with MINIMOS-NT have been performed to investigate the influence of device parameters on the R_sp and the breakdown voltage. The improvement in the current handling capability of the suggested device is about 8.3% compared to the conventional SOI-LDMOSFET.     

适用于深沟槽结构观测的TEM样品制备技术

对于深沟槽DRAM电容这类纵向深度深(超过5μm)但是平面尺寸又很小(小于0.2μm×0.2μm)的结构来说,传统的TEM制样方法,无法满足其细微结构全面观测的需求,此外传统的方法制样也比较费时,成功率也比较低。介绍了一种FIB横向切割技术,适用于对这类结构的观测。它与传统FIB制样方法的主要区别在于,切割方向由纵向切割改为横向切割。用这种方法制备的TEM样品,可以完整地观测同一个深沟槽DRAM电容结构的所有细微结构。制样过程比较简单、速度快、成功率高。以一个实例分析、比较了传统制样方法和新的制样方法,突显了FIB横向切割技术的优点。     

Design and Analysis of Refractometer Based on Bend Waveguide Structure with Air Trench for Optical Sensor Applications

This study proposes a novel optical sensor structure based on a refractometer combining a bend waveguide with an air trench. The optical sensor is a splitter structure with a reference channel and a sensing channel. The reference channel has a straight waveguide. The sensing channel consists of a U‐bend waveguide connecting four C‐bends, and a trench structure to partially expose the core layer. The U‐bend waveguide consists of one C‐bend with the maximum optical loss and three C‐bends with minimum losses. A trench provides a quantitative measurement environment and is aligned with the sidewall of the C‐bend having the maximum loss. The intensity of the output power depends on the change in the refractive index of the measured material. The insertion loss of the proposed optical sensor changes from 3.7 dB to 59.1 dB when the refractive index changes from 1.3852 to 1.4452.     

Dual-Material-Gate Technique for Enhanced Transconductance and Breakdown Voltage of Trench Power MOSFETs

In this brief, we propose a new dual-material-gate-trench power MOSFET that exhibits a significant improvement in its transconductance and breakdown voltage without any degradation in on-resistance. In the proposed structure, we have split the gate of a conventional trench MOSFET structure into two parts for work-function engineering. The two gates share the control of the inversion charge in the channel. By using 2-D numerical simulation, we have shown that by adjusting the lengths of the two gates to allow equal share of the inversion charge by them, we get the optimum device performance. By using $hbox{N}^{+}$ poly-Si as a lower gate material and $hbox{P}^{+}$ poly-Si as an upper gate material, approximately 44% improvement in peak transconductance and 20% improvement in breakdown voltage may be achieved in the new device compared to the conventional trench MOSFET.      

Power Trench MOSFET Devices on Metal Substrates

Power trench MOSFET devices have been accomplished on Cu substrates using a novel silicon-on-metal (SOM) technology. This technology transfers silicon trench MOSFET device layers from SOI wafers to metal substrates. The prototype 30-V (drain-to-source voltage) n-channel SOM device with a pitch of 2.5 $muhbox{m}$ comprises a 5-$muhbox{m}$ device layer and an electroplated Cu substrate. These devices are the first of their kind exhibiting a negligible substrate drain contribution to their specific Rdson and have a specific Rdson of 0.198 $ hbox{m} Omega cdot hbox{cm}^{2}$ at a gate voltage of 10 V. This specific Rdson is 38% smaller than that of the same device on the silicon substrate. The dc–dc converter with SOM devices shows 11% reduction in device power loss and an energy efficiency of about 2% higher than with the same Si-based devices. The operating temperature of the SOM die in the converter is also 9 $^{circ} hbox{C}$ lower than the Si-based die. The “cooler” SOM device is due to primarily improved energy efficiency. The transient thermal resistance of the SOM device is 20 $^{circ}hbox{C/W}$, which is less than half of 57.5 $^{ circ}hbox{C/W}$ for the Si-based device at a pulse duration of 10 s.      

Extended Trench Gate Superjunction Lateral Power MOSFET for Ultra‐Low Specific on‐Resistance and High Breakdown Voltage

In this paper, a lateral power metal–oxide–semiconductor field‐effect transistor with ultra‐low specific on‐resistance is proposed to be applied to a high‐voltage (up to 200 V) integrated chip. The proposed structure has two characteristics. Firstly, a high level of drift doping concentration can be kept because a tilt‐implanted p‐drift layer assists in the full depletion of the n‐drift region. Secondly, charge imbalance is avoided by an extended trench gate, which suppresses the trench corner effect occurring in the n‐drift region and helps achieve a high breakdown voltage (BV). Compared to a conventional trench gate, the simulation result shows a 37.5% decrease in R_on.sp and a 16% improvement in BV.     

Characterization of the cell leakage of a stacked trench capacitor(STT) cell

The cell leakage of a stacked trench capacitor (STT) cell has been investigated. The major leakage mechanisms of the STT are trench-to-trench leakage, trench junction leakage, and LOCOS isolation leakage. It is shown that compared to a conventional trench capacitor, the trench-to-trench leakage current is reduced and high punchthrough voltage is obtained. Therefore, the trench-to-trench spacing can be reduced 0.1 μm shorter than that of the trench capacitor. These reductions result from the STT structure itself. The surface leakage current, which is the dominant leakage current in the trench capacitor, does not flow in the STT. This paper also describes the effect of the sidewall damage caused by trench etching on the trench junction leakage. Reactive ion etching (RIE) produces deep levels just beneath the trench surface. But, the trench junction of the STT is not influenced by these deep levels because the trench surface is covered by a n^-diffused layer. This paper also investigates the relationship between the cell leakage and the retention time. At DRAM operation temperatures, LOCOS isolation leakage is dominant rather than trench junction leakage. Therefore, the deeper trench can increase the storage capacitance and improve the retention time     

On the scaling property of trench isolation capacitance foradvanced high-performance ECL circuits

A detailed study on the scaling property of trench isolation capacitance for advanced high-performance bipolar applications is presented. It is shown that the trench isolation capacitance depends on the trench structure, particularly the trench bottom and the trench fill. The dependence of the trench isolation capacitance on the trench width is analyzed for various commonly used trench structures. The impact on scaled-down high-performance emitter-coupled logic (ECL) circuits is presented     

Three-dimensional simulation of microstructure evolution in damascene interconnects: Effect of overburden thickness

Microstructure in the damascene interconnects evolves with the overburden layer, an excessive metal layer over trenches. We present the results of three-dimensional simulation, which show the effects of overburden thickness on microstructure evolution in a trench. When the thickness of the overburden is less than half of the trench depth, for a trench with the aspect ratio of unity, the microstructure in the trench tends to evolve into a bamboo structure. This effect is discussed in terms of grain sizes in the trench and those in the overburden. The thinner overburden layer would have smaller grains, of which growth is limited by its thickness. Such small-sized grains in the overburden are not likely to grow into the trench, which hardly make grain boundaries in the trench. Meanwhile, the grains from the trench are able to continue growth inside the trench, resulting in a bamboo structure. Overburden thickness affects the reliability and the electrical performance of the damascene copper interconnects. Optimization of overburden thickness is required to minimize these effects.     

高压槽型SOI LDMOS槽区设计的普适方法

论文介绍了高压SOI槽型LDMOS不同槽介质,槽宽和槽深设计的普适方法。该方法考虑了击穿电压和导通电阻的折中关系。浅而宽的槽适合用高介电常数材料填充,深而窄的槽适合用低介电常数材料填充。论文还讨论了真空槽的情况。仿真结果表明由于器件总宽度的降低,采用低介电常数材料填充槽区可以获得更高的设计优值。     

A novel trench capacitor enhancement approach by selective liquid-phase deposition

For the first time, a novel and simple trench bottle integrated process is demonstrated on dynamic random access memory (DRAM) manufacturing by selective liquid phase deposition (S-LPD) oxide. After photoresist (PR) filled into a deep trench (DT) and was recess etched at around 1.3 /spl mu/m depth, LPD oxide can be selected as a deposit onto the DT sidewall but not as a deposit on the PR surface. This S-LPD oxide is formed by using hexa-fluosilic acid (H/sub 2/SiF/sub 6/) and water without H/sub 3/BO/sub 3/. After the PR is removed, the LPD oxide becomes a protective layer on DT upper portion. Thus, the DT bottom area can be enlarged to form a trench bottle by NH/sub 4/OH wet etching. Compared to conventional DT trench, 20% of capacitance was enhanced by this S-LPD process. This novel and low-cost method is for the first time demonstrated on 200-mm wafer 110-nm trench DRAM technology.