99.83% Switching energy reduction over conventional scheme for SAR ADC without reset energy

A high-efficient switching method for successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. With the proposed variable resolution SAR ADC architecture, the average switching energy and area can be reduced by 99.60 and 73.54% respectively compared to the conventional scheme. Combined with C–2C capacitor array and unilateral monotonic scheme, the proposed two-step architecture achieves 99.83% less average switching energy and 76.37% less area reduction over the conventional approach. Furthermore, these two methods have no rest energy consumption.     

Ultra-low-power capacitor-splitting switching algorithm with minus energy for SAR ADCs

In this letter, an ultra-low-power capacitor-splitting switching algorithm for successive approximation register analog-to-digital converters is proposed. To achieve low power, the first three bit cycles consume no power from the reference by introducing minus energy during the third bit cycle and proper switching algorithm. To further reduce the switching energy, only single-side capacitors are switched from the forth bit cycle. Besides, to add one bit, the dummy capacitor is realized by four unit capacitors and switched to generate the least significant bit. Compared to the Sanyal and Sun switching technique, the proposed capacitor switching method achieves 94.19% energy saving and 47.66% capacitor area reduction.     

LSB split capacitor SAR ADC with 99.2% switching energy reduction

A highly energy efficient capacitor switching technique in a successive approximation register (SAR) analog to digital converter (ADC) for biomedical applications is presented. The proposed scheme based on new switching method, which combine the LSB split capacitive technique and monotonic method can reduce the average switching energy by 99.2% compared to the conventional SAR architecture. Besides reducing energy in each comparison cycle, the suggested method also achieves an 8× reduction in total capacitance used in the digital to analog converter over the conventional one with the same resolution. The proposed ADC can find application in biomedical engineering systems and other fields which low power consumption is needed.     

High-linear,energy-efficient and area-efficient switching algorithm for high-speed SAR ADCs

Decreasing the size of DAC capacitors is a solution to achieve high-speed and low-power successive-approximation register analog-to-digital converters (SAR ADCs). But decreasing the size of capacitors directly effects the linearity performance of converter. In this paper, the effect of capacitor mismatch on linearity performance of charge redistribution SAR ADCs is studied. According to the achieved results from this investigation, a new tri-level switching algorithm is proposed to reduce the matching requirement for capacitors in SAR ADCs. The integral non-linearity (INL) and the differential non-linearity (DNL) of the proposed scheme are reduced by factor of two over the conventional SAR ADC which is the lowest compared to the previous schemes. In addition, the switching energy of the proposed scheme is reduced by 98.02% as compared with the conventional architecture which is the most energy-efficient algorithms in comparison with the previous algorithms, too. To evaluate the proposed method an 8-bit 50 MS/s SAR ADC is designed in 0.18 um CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 25-MHz input with 48.16 dB SNDR while consuming about 589 μW from a 1.2-V supply.     

一种用于逐次逼近ADC的高能效高线性度开关电容时序

提出了一种用于逐次逼近模数转换器的高能效高线性度开关电容时序。相较于典型的基于V_CM的开关原理,该开关时序可减少37%的开关能量,并具有更高的线性度。该开关时序已应用于1V,10位300kS/s的SAR ADC,并在0.18μm标准CMOS工艺下成功流片。测试结果表明,在1V电源电压下,此SAR ADC的SNDR为55.48dB,SFDR为66.98dB,功耗为2.13μW,品质因数到达14.66fJ/c-s。DNL和INL分别为0.52/-0.47 LSB和0.72/-0.79 LSB,并且与静态非线性模型一致,最大INL出现在 V_FS/4处和3V_FS/4处。     

High energy-efficient partial floating capacitor array DAC scheme for SAR ADCs

A high energy saving and high linearity switching method of successive approximation register analogue-to-digital converters is presented. The proposed method can achieve high energy savings and high linearity due to the fact that the partial floating and split capacitor techniques are combined. This scheme has no reset energy consumption, and achieves purely 98.63% less switching energy and 75% reduction of the total capacitance over the conventional switching scheme. Moreover, the proposed scheme achieves Differential Nonlinearity and Integral Nonlinearity only 0.140LSB and 0.122LSB, respectively.     

Energy-efficient switching scheme for SAR ADC with only two reference voltages

An energy-efficient switching method for successive approximation register analog to digital converter is presented in this letter.The proposed two-step switching scheme using the goblet architecture achieves 99.52% less switching energy and 21.09% area reduction over the conventional switching scheme. Moreover, owing to the application of the goblet architecture, the proposed scheme employs only two reference voltages without any requirements for stability or accuracy of the third voltage level.     

Low-energy and area-efficient switching scheme for SAR A/D converter

A high energy-efficiency switching scheme for low-power successive approximation resister analogue-to-digital converter is proposed. With sequence initialization, monotonic switching procedure and intermittent multiple references, the average switching energy and total capacitance of the proposed scheme are reduced by 97.7 and 87.5 % respectively compared to the conventional architecture. The applicability and superiority of the proposed scheme are proven by Matlab modeling and comparison with previous works.     

高精度无线移动通信信道盲估计方法

基于多载波OFDM系统,提出了一种新的时变步长修正软加权判决递归二乘信道估计盲方法(TVCPMSDWRLS).该法通过对常规算法步长进行自适应的科学设计以便跟踪信道特征变化,同时利用接收机判决信息函数修正权系数,解决了常规RLS盲方法收敛速度慢、信道估计性能不高的缺点.仿真证明:对于不同的时延扩展、时间以及信噪比(SNR),该法均表现出比常规方法更优的性能.同时,该法亦可用于估计通信、雷达、航天等领域的其他特征参数.     

Two-step V<Subscript>cm</Subscript>-based MS switching method with dual-capacitive arrays for SAR ADCs

An ultra-low-power two-step merge and split (MS) switching method for a dual-capacitive arrays (DCAs) successive approximation register analogue-to-digital converter is presented. This method only requires two reference levels, i.e. Gnd and V_cm (V_cm = 1/2V_ref). Compared with the conventional method, the proposed method achieves 99.89 and 80.96% reduction in average switching energy and capacitors, respectively, meanwhile maintaining good linearity. In addition, it barely consumes reset energy and keeps common-mode voltage of DCAs almost constant.     

利SAR ADC降低成本、扩展应用

在解决如何让特定应用和ADC体系结构相互匹配这一问题上,工业界已经推出了一种称为SAR(Successive Approximation Register,连续逼近寄存器)ADC的数模转换产品,它可以被看作是∑-△和流水线式ADC折衷的产物.     

An efficient threshold voltage generation for SAR ADCs

In this paper, a new architecture for successive-approximation register (SAR) analog-to-digital converters (ADCs) is presented. In the proposed scheme, the threshold voltage for each comparison is divided into two parts. This results in appreciably less switching energy and less total capacitance without a substantial increase in digital complexity compared to the conventional SAR ADC. Analytical calculations and circuit level simulation results in the context of a 10-bit 100 kS/s ADC are provided to verify the usefulness of the proposed SAR ADC scheme revealing 87 % less switching power and 40 % less total capacitance in comparison with the conventional SAR ADC.     

A novel MPPT circuit with 99.1% tracking accuracy for energy harvesting

A novel maximum power point tracking (MPPT) circuit based on Buck–Boost converter is presented for micro-power energy harvesting, which efficiently improves the power efficiency and robustness of system. The proposed MPPT uses the low-power analog multiplier and multi-outputs self-powered common-gate comparator to track the input power, and simplifies data calculation and structure greatly. The fast dynamic switching circuit and digital control circuit are introduced to enhance the adaptability and flexibility of system. The performance of whole converter was validated by the simulation results in a 65-nm CMOS process. The minimum starting voltage is 0.15 V. The peak output power is 40.5 µW, with a power loss of 14.1 µW. The peak power efficiency and peak tracking efficiency are 92.1 and 99.1%, respectively. The proposed MPPT has the advantages such as low power, high efficiency, fast tracking speed, simple structure.     

Energy-efficient CMOS delay line with self-supply modulation for low-power SAR ADCs

ABSTRACT

A new digital delay line based on the inverter chain is proposed. The proposed new method of connection of the inverters allows much longer delay times to be achieved for the same number of transistors, the same amount of power to be consumed as for conventional connection of inverters. Simulation results using a 65 nm CMOS design kit from ST Microelectronics are provided. An application example of the proposed delay line is provided for low-power, low-speed successive approximation register (SAR) analogue-to-digital converters (ADC).     

Efficient signal reconstruction scheme for M-channel time-interleaved ADCs

In time-interleaved analog-to-digital converters (TI-ADCs), the timing mismatches between the channels result in a periodically nonuniformly sampled sequence at the output. Such nonuniformly sampled output limits the achievable resolution of the TI-ADC. In order to correct the errors due to timing mismatches, the output of the TI-ADC is passed through a digital time-varying finite-length impulse response reconstructor. Such reconstructors convert the nonuniformly sampled output sequence to a uniformly spaced output. Since the reconstructor runs at the output rate of the TI-ADC, it is beneficial to reduce the number of coefficient multipliers in the reconstructor. Also, it is advantageous to have as few coefficient updates as possible when the timing errors change. Reconstructors that reduce the number of multipliers to be updated online do so at a cost of increased number of multiplications per corrected output sample. This paper proposes a technique which can be used to reduce the number of reconstructor coefficients that need to be updated online without increasing the number of multiplications per corrected output sample.     

Resonant gate driver with efficient gate energy recovery and switching loss reduction

This article describes a novel resonant gate driver for charging the gate capacitor of power metal-oxide semiconductor field-effect-transistors (MOSFETs) that operate at a high switching frequency in power converters. The proposed resonant gate driver is designed with three small MOSFETs to build up the inductor current in addition to an inductor for temporary energy storage. The proposed resonant gate driver recovers the CV² gate loss, which is the largest loss dissipated in the gate resistance in conventional gate drivers. In addition, the switching loss is reduced at the instants of turn on and turn off in the power MOSFETs of power converters by using the proposed gate driver. Mathematical analyses of the total loss appearing in the gate driver circuit and the switching loss reduction in the power switch of power converters are discussed. Finally, the proposed resonant gate driver is verified with experimental results at a switching frequency of 1 MHz.     

Recovery circuit for snubber energy in power electronicapplications with high switching frequencies

A simple, reliable circuit is presented that allows snubber energy to be recovered by using a self-oscillating DC-to-DC converter. The applicability of the circuit is experimentally proved in three different types of power converters for electrical drives     

一个采用面向建立走线优化的定制三维1-fF MOM单位电容的电容型数模转换器

异步逐次比较模数转换器由于其高能效和中高性能在近年来得到了广泛的关注。其设计性能的主要瓶颈在于其单位电容的大小。本文提出了一种三维结构的金属-氧化层-金属电容,其单位电容大小仅为1 fF。该电容形似伞状,以此实现快速建立的性能需求。作者将该电容和目前国际顶尖的定制化三维电容结构进行了比较。为了验证该电容的有效性,作者设计了一个基于该电容的6位电容型数模转换器,基于TSMC 1P9M 65nm LP CMOS工艺。该数模转换器在100MS/s的工作速度下功耗为0.5mW,其中没有包含以可测性为目的的源级跟随器。静态性能测试结果显示该数模转换器的INL小于 /- 1LSB,DNL 小于 /- 0.5 LSB,从而证明了该电容的有效性。