A 2.1 μW 80 dB SNR DT ΔΣ modulator for medical implant devices in 65 nm CMOS

This paper presents a simple and robust low-power ΔΣ modulator for accurate ADCs in implantable cardiac rhythm management devices such as pacemakers. Taking advantage of the very low signal bandwidth of 500 Hz which enables high oversampling ratio, the objective is to obtain high SNDR and low power consumption, while limiting the complexity of the modulator to a second-order architecture. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-V_T devices in analog circuits and switches, allowing the modulator to operate at 0.9 V supply. Fabricated in a 65 nm CMOS technology, the modulator achieves 80 dB peak SNR and 76 dB peak SNDR over a 500 Hz signal bandwidth. With a power consumption of 2.1 μW, the modulator obtains 0.4 pJ/step FOM. To the authors’ knowledge, this is the lowest reported FOM, compared to the previously reported second-order modulators for such low-speed applications. The achieved FOM is also comparable to the best reported results from the higher-order ΔΣ modulators.     

Digital background calibration of charge pump based pipelined ADC

In the presented work, digital background calibration of a charge pump based pipelined ADC is presented. A 10-bit 100 MS/s pipelined ADC is designed using TSMC 0.18 µm CMOS technology operating on a 1.8 V power supply voltage. A power efficient opamp-less charge pump based technique is chosen to achieve the desired stage voltage gain of 2 and digital background calibration is used to calibrate the inter-stage gain error. After calibration, the ADC achieves an SNDR of 66.78 dB and SFDR of 79.3 dB. Also, DNL improves to +0.6/–0.4 LSB and INL improves from +9.3/–9.6 LSB to within ±0.5 LSB, consuming 16.53 mW of power.     

A 1.2 V 10-bit 5MS/s low power CMOS cyclic ADC based on double-sampling technique

This paper presents a 1.2 V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC). The strategy to minimize the power adopts the double-sampling technique. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch is used to achieve rail-to-rail signal swing at low-voltage power supply. The prototype ADC, fabricated in TSMC 0.18 μm CMOS 1P6 M process, achieves DNL and INL of 0.32LSB and 0.45LSB respectively, while SFDR is 69.1 dB and SNDR is 58.6 dB at an input frequency of 600 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 1.68 mW.     

A 9-bit 2 MS/s 1 mW CMOS cyclic folding A/D converter for battery management system

In this paper, a 9-bit 2 MS/s CMOS cyclic folding A/D converter (ADC) for a battery management system is described. The scheme of the ADC is based on a cyclic style to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding–interpolation architecture. The prototype ADC is implemented with a 0.35 μm 2P4M n-well CMOS process. The measured results for INL and DNL are within ±1.5/±1.0 LSB. The ADC demonstrates a maximum SNDR and SFDR of 48 and 60 dB, respectively, and the power consumption is about 1 mW at 3.3 V.     

A 10-bit 50-MS/s redundant SAR ADC with split capacitive-array DAC

A new architecture for successive-approximation register analog-to-digital converters (SAR ADC) using generalized non-binary search algorithm is proposed to reduce the complexity and power consumption of the digital circuitry. The proposed architecture is based on the split capacitive-array DAC with a simple switching logic as compared to the conventional non-binary SAR ADC architecture. A 10-bit 50-MS/s SAR ADC is designed based on the proposed architecture in a 0.18 μm CMOS technology. Simulation results show that at a supply voltage of 1.2 V, the SAR ADC achieves a peak signal-to-noise-and-distortion ratio of 59.5 dB, and a power consumption of 1.3 mW, resulting in a figure of merit of 33 fJ/conversion-step.     

A zero-crossing based 10-bit 100 MS/s pipeline ADC with controlled current in 90 nm CMOS

In this paper, a new charging technique for low power zero-crossing based circuit pipeline analog-to-digital converters (ADCs) is presented. The charging current sources are implemented as voltage-controlled current sources in order to charge the sampling capacitors based on the error signal. Using this method, the ADC power consumption is reduced while improving the accuracy. The necessary current control block is shared between consecutive stages further reducing the power consumption and die area. The proposed technique is applied to a 10-bit 100 MS/s pipeline ADC designed in a 90 nm CMOS technology with 1 V power supply. Circuit level simulation results using Cadence Spectre show a signal-to-noise and distortion ratio of 55.6 dB with 3.56 mW power consumption resulting in a figure of merit of 72.3 fJ/conv.step without employing any calibration technique.     

Algorithmic ADC operating with a single reference voltage for PLL-based chemical sensing applications

This paper deals with the design of an algorithmic switched-capacitor analog-to-digital converter (ADC), operating with a single reference voltage, a single-ended amplifier, a single-ended comparator, and presenting a small input capacitance. The ADC requires two clock phases per conversion bit and N clock cycles to resolve the N-bits. The ADC achieves a measured peak signal-to-noise-ratio (SNR) of 49.9 dB and a peak signal-to-noise-and-distortion-ratio (SNDR) of 46.7 dB at P_in = ?6dBFS with a sampling rate of 0.25 MS/s. The measured differential-non-linearity and integral-non-linearity are within +0.6/?0.5 and +0.2/?0.5 LSB, respectively. The ADC power consumption is 300 μW and it is implemented in 90 nm CMOS technology with a single power supply of 1.2 V. The ADC saves power at system-level by requiring only a single reference voltage. At system level, this solution is therefore not only robust but competitive as well.     

Combination of DAC switches and SAR logics in a 720 MS/s low-bit successive approximation ADC

In this paper a 4-bit 720 MHz low-power successive approximation register ADC is simulated in a 0.18 µm digital CMOS process. By using both of the 2-bit/step and time-interleaved techniques, a high sampling frequency is obtained. To simplify the SAR ADC in low-bit applications, the analog switches are eliminated and replaced with inherent digital switches of SAR logics. The power supply, resolution, sampling frequency, SNDR, and power consumption of the proposed SAR ADC are 1.8 V, 4-bit, 720 MHz, 22.1 dB, and 10 mW.     

L, C and X band integrated synthetic aperture radar (SAR) receiver

An integrated receiver consisting of RF front ends, analog baseband (BB) chain with an analog to digital converter (ADC) for a synthetic aperture radar (SAR) implemented in 130 nm CMOS technology is presented in this paper. The circuits are integrated on a single chip with a size of 10.88 mm². The RF front end consists of three parallel signal channel intended for L, C and X-band of the SAR receiver. The BB is selectable between 50 and 160 MHz bandwidths through switches. The ADC has selectable modes of 5, 6, 7 and 8 bits via control switches. The receiver has a nominal gain of 40 and 37 dB and noise figure of 11 and 13.5 dB for 160 MHz BB filter at room temperature for L-band and C-band, respectively. The circuits, which use a 1.2 V supply voltage, dissipate maximum power of 650 mW with 50 MHz BB and 8 bit mode ADC, and maximum power of 800 mW with 160 MHz BB and 8 bit mode ADC.     

A 0.5-V low power analog front-end for heart-rate detector

This paper presents a low power analog front-end for heart-rate detector at a supply voltage of 0.5 V in 0.18 μm CMOS technology. A fully differential preamplifier is designed with a low power consumption of 300 nW. A 150 nW fourth order Switched-opamp switched capacitor bandpass filter is designed with passband 8–32 Hz. To digitize the analog signal, a low power second-order ΣΔ ADC is designed. The dynamic range and SNR of the converter are 46 dB and 54 dB respectively and it consumes a power of 125 nW. The overall front-end system including preamplifier, SO-SC bandpass filter, ΣΔ modulator and the biasing circuits are integrated and the total system consumes a power of 0.975 μW from 0.5 V supply.     

A 0.6 V 100 KS/s 8–10 b resolution configurable SAR ADC in 0.18 μm CMOS

A resolution configurable ultra-low power SAR ADC in 0.18 μm CMOS process is presented. The proposed ADC has maximum sampling rate of 100 KS/s with configurable resolution from 8 to 10 b and operates at a supply of 0.6 V. Two-stage bootstrapped switch and voltage boosting techniques are introduced to improve the performance of the ADC at low voltage. To reduce the power consumption of the analog components of the ADC, monotonic capacitor switching procedure and fully dynamic comparator are utilized. The implementation of dynamic logic further reduces the power of the digital circuits. Post-layout simulation results show that the proposed SAR ADC consumes 521 nW and achieves an SNDR of 60.54 dB at 10 b mode, resulting in an ultra-low figure-of-merit of 6.0 fJ/conversion-step. The ADC core occupies an active area of only 350 × 280 μm².     

A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

This article presents a reconfigurable pipeline analog-to-digital converter (ADC) using a two-stage cyclic configuration. The ADC consists of two stages with 1.5 effective bit resolution, two reference circuits for voltage and current biasing, and a clock generator and timing circuit. Throughout the development of this ADC, several techniques were combined for reducing the power consumption as well as for preserving the converter linearity. To reduce the power consumption, the circuit has a single operational trans-conductance amplifier shared by both pipeline stages. To keep conversion linearity, circuits such as the bootstrapped complementary metal-oxide semiconductor (CMOS) transmission gates and a robust comparator topology were implemented. The circuit can be configured to perform conversion between 7 and 15 bit resolutions, and it works with the master clock frequency in the range of 1 kHz to 40 MHz. The circuit has been prototyped in a 3.3 V 0.35 µm CMOS process and consumes 14.1 mW at 40 MHz and 8 MSample/s sampling rate. With this resolution and sampling rate, it achieves 60.1 dB SNR, 56.57 dB SINAD and 9.1 bit ENOB at 0.666 MHz input frequency and 53.6 dB SNR, 52.4 dB SINAD and 8.6 bit ENOB at 3.85 MHz input frequency. The technological FOM obtained was 13.2 A s/m².     

A 360 fJ/conversion-step, 14-bit, 100 MS/s,digitally background calibrated pipelined ADC in 130-nm CMOS

This paper describes a 14-bit digitally background calibrated pipeline analog-to-digital converter (ADC) implemented in a mainstream 130-nm CMOS technology. The proposed calibration technique linearizes the digital output to correct for errors resulting from capacitor mismatch, finite amplifier gain, voltage reference errors and differential offsets. The software-based calibration technique requires quite modest digital resources and its estimated dynamic power is under 1 % of the ADC power consumption. After calibration, the 14-bit ADC achieves a measured peak Signal-to-Noise-plus-Distortion-Ratio of 71.1 dB at 100 MS/s sampling rate. The worst-case integral nonlinearity is improved from 32.9 down to 4 Least-Significant-Bits after calibration. The chip occupies an active area of 1.25 mm² and the core ADC (S/H+analog+digital power) consumes 105 mW. The Figure-of-Merit is 360 fJ per conversion-step.     

A Hybrid Audio ΔΣ Modulator with dB‐Linear Gain Control Function

A hybrid ΔΣ modulator for audio applications is presented in this paper. The pulse generator for digital‐to‐analog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB‐linear fashion. Also, careful chopper stabilization implementation using return‐to‐zero scheme in the first continuous‐time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 μm CMOS technology (I/O devices) and occupies an active area of 0.37 mm². The ΔΣ modulator achieves a dynamic range (A‐weighted) of 97.8 dB and a peak signal‐to‐noise‐plus‐distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from –9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 ns_RMS external clock jitter.     

Design of a fA wide dynamic range ADC for current sensing

In this paper, optimal dynamic range scaling of ΔΣ ADC using bias current estimation method is proposed. Generally, a different dynamic range scaling gives different feedback factor and effective load capacitance to each integrator in the ΔΣ ADC. It means that power consumption of each integrator strongly depends on the coefficient of the integrator. Therefore, the proposed method estimates which dynamic range scaling consumes the least power to achieve a given settling error. To verify the effectiveness of the proposed method, the noise coupled third order ΔΣ ADC having different dynamic scaling with transistor level opamps was simulated to compare the ADC performance.     

A noise-shaping SAR ADC for energy limited applications in 90 nm CMOS technology

In this paper, an ultra-low-power successive approximation register analog-to-digital converter (ADC) for energy limited applications is presented. The ADC resolution is enhanced by using a noise-shaping technique which does not need any integrator and only uses a finite impulse response (FIR) filter. To provide a first-order noise-shaping, the quantization error is firstly extracted by using the digital-to-analog converter (DAC) dummy capacitor and it is then employed in the error feedback scheme. The proposed structure employs a low-gain and low-swing operational transconductance amplifier (OTA) to realize the FIR filter which operates only at the sampling phase. To minimize the power consumption of the ADC analog part, the OTA is powered off during the conversion phase. The proposed ADC is designed and simulated in a 90 nm CMOS technology using Spectre with a 0.5 V single power supply. The simulated ADC uses a fully-differential 8-bit charge redistribution DAC with an oversampling ratio of 8 and achieves 10.7-bit accuracy. The simulated average power consumption is 4.53 μW and the achieved maximum SNDR and SFDR are 66.1 and 73.1 dB, respectively, resulting in a figure of merit of 27.6 fJ/conversion-step.     

An energy-efficient reconfigurable analog-to-digital converter for orthopedic implants

This paper presents a pipelined analog to digital converter (ADC) with reconfigurable resolution and sampling rate for biomedical applications. Significant power saving is achieved by turning off the sample-and-hold stage and the first two pipeline stages of the ADC instead of turning off the last two stages. The reconfiguration scheme allows having three modes of operation with variable resolutions and sampling rates. Reconfigurable operational transconductance amplifiers and an interference elimination technique have been employed to optimize power-speed-accuracy performance in biomedical instrumentation. The proposed ADC exhibits a 56.9 dB SNDR with 35.4 mW power consumption in 10-bit, 40 MS/s mode and 49.2 dB SNDR with only 7.9 mW power consumption in 8-bit, 2.5 MS/s mode. The area of the core layout is 1.9 mm² in a 0.35 μm bulk-CMOS process.     

Design of a high gain and highly linear common-gate UWB mixer in K-band

In this paper, in order to design a K-band common-gate Gilbert-cell mixer via a 0.18 μm CMOS technology, the π-Network and post-distortion cancellation (PDC) techniques are implemented simultaneously, resulting in the improvement of gain, bandwidth, noise figure and linearity. Also, a new method for implementing the π-Network, using the parasitic capacitances between RF and LO stage nodes, is proposed which improves the mixer performance and makes the mixer design possible at high frequencies. It is shown that the π-Network enhances the gain and bandwidth by generating complex poles in system frequency response without the need for extra power consumption. The suitable location of these poles, which gives rise to high gain and high bandwidth, is discussed and determined by MATLAB simulation. Results of simulation illustrate 3.36 dB improvement in power conversion gain and 2 dB reduction in noise figure at the same power consumption with LO power of ?1 dBm in comparison with the case when PDC technique is used only. Compared to conventional mixer, it improves the IIP3 by 6 dB. Also, the power consumption of the mixer together with the designed bias circuit is 9.68 mW at 1.8 V.     

Improved double noise coupling ΔΣ analog-to-digital converter

In Jung et al. (Electron Lett 48(10):557–558, 1), a double noise coupling scheme was proposed for ΔΣ analog-to-digital converters (ADCs) to achieve wideband and high accuracy performance combined with low power consumption. In this paper, an improved version of double noise coupling ΔΣ ADC is presented. The improved architecture reduces the power consumption significantly, by reducing the output swing of the second integrator in the modulator. Also, the improved double noise coupling ΔΣ ADC relaxes the feedback timing of the modulator using a triple sampling technique (Kanazawa et al. in IEEE Custom Integrated Circuit Conference, 2). Thus, there is no need to have high-speed comparator and DEM circuitry even for high-speed applications. By using both techniques, the performance of the double noise coupling ΔΣ ADC can be improved significantly.     

High-speed single-channel SAR ADC with a novel control logic in 65 nm CMOS

This paper presents an 8-bit 320 MS/s single-channel successive approximation register (SAR) analog-to-digital converter (ADC) with low power consumption. Through a procedure of splitting all the most significant bit (MSB) capacitors except the least significant bit (LSB) capacitor into two equal sub-capacitors and reusing the terminal capacitor, the average switching energy and total capacitance can be reduced by about 87 and 50% respectively compared to the conventional procedure. Meanwhile, high-speed operation can be achieved by using a novel SAR control logic featuring efficient hardware cost and small critical path delay. In addition, this paper analyzes how to obtain the value of the unit capacitance which exhibits trade-offs between conversion rate, power consumption and linearity performance. The SAR ADC is simulated in 65 nm CMOS technology. It can achieve 48.63 dB SNDR, 63.61 dB SFDR at a supply voltage of 1.2 V and sampling frequency of 320 MS/s for near-Nyquist input, consuming 2.59 mW of power and with a FoM of 37 fJ/conversion-step.