Memristive retinomorphic grid architecture removing noise and preserving edge

In this paper, special memristor circuit and memristive retina network structure for analogue image processing have been presented. The new developments on memristor element have opened various possibilities due to its being in nano-scale and having nonlinear behavior. The proposed memristor emulator consists of only one Operational Transconductance Amplifier (OTA) and two MOS transistors which are operated in sub-threshold region. The memristor fuse structure is obtained by connecting two proposed memristor emulators. In the second section of our paper, we proposed a circuit block which is composed of 16 × 16 pixels retinomorphic memristive grid to maintain a smoothed and edges preserved image. All simulation results for both proposed memristor circuits and retinomorphic grid are obtained as expected.     

基于FPGA的二值忆阻器仿真器研究及应用

基于FPGA的可重构性,提出了一种基于数字电路的二值忆阻器仿真器。与模拟电路忆阻器仿真器相比,所提出基于数字电路的忆阻器仿真器易于重新配置,与它所基于的数学模型表现出很好的匹配性,符合忆阻器仿真器所有要求的特点。实现了基于该仿真器的与门、或门、加法器及三人表决器。使用Altera Quartus II和ModelSim工具对仿真器功能和基于该仿真器实现的逻辑电路进行验证。给出所有设计电路的原理图、仿真结果和FPGA资源消耗。仿真结果表明,该二值忆阻器仿真器相比其他数字电路忆阻器仿真器具有更少的硬件资源消耗,更适合用于大规模忆阻器阵列研究。     

Synchronization and chaos in coupled memristor-based FitzHugh-Nagumo circuits with memristor synapse

The memristor has drawn a significant interest in the fields of neuromorphic circuits because the nanoscale memristor is a strong candidate to become the critical element of novel ultra-high density low-power non-volatile memories. In the present paper, we focus on networks of FitzHugh-Nagumo neuron circuits employing memristor. First, we build the memristor-based circuit of FitzHugh-Nagumo model. The details of the chaotic phenomena of the memristor-based FitzHugh-Nagumo circuit under external stimuli have been found with use of computer simulations, i.e., we have numerically calculated waveform diagrams, phase portraits, Lyapunov exponents and bifurcation diagram. And we also confirm these results of theoretical analyses and numerical calculations by circuit simulation experiments of the actual analog circuit realization using Multisim modeling. Then the synchronization of coupled memristor-based chaotic neurons with memristor synapse is discussed, and synchronization mechanism is also found. Finally, we have also derived the sufficient conditions of chaotic synchronization in unidirectional coupled neuron circuits and bidirectional coupled neuron circuits respectively, which are that the parameter of memristor synapse must meet certain conditions. These results of theoretical analyses have been confirmed by numerical simulation.     

新型忆阻器混沌电路及其在图像加密中的应用

忆阻器是一种拥有记忆功能的电阻,目前忆阻器的研究热点及难点在于新模型的建立以及相关方面的应用。该文提出一种基于双曲正弦函数的新型磁控忆阻器模型,通过分析电压和电流的相轨迹关系,发现其具有典型的忆阻器电压-电流特性曲线。利用新建的忆阻器模型构造新型忆阻混沌系统,通过数值仿真绘出新系统的相轨迹图、分岔图、Lyapunov 指数谱等,分析了不同参数时系统的混沌演化过程。另外,基于电路仿真软件Multisim研制了实验仿真电路, 该电路结构简单、易于实际制作,且仿真实验与理论分析结论十分吻合,证实了提出的忆阻混沌系统电路在物理上是可以实现的。最后,利用新系统混沌序列对图像进行加密,重点分析了加密直方图、相邻像素相关性以及抗攻击能力与密钥敏感性,结果表明新系统对图像密钥及明文都非常敏感,密钥空间较大,新提出的忆阻混沌系统应用于图像加密具有较高的安全性能。     

Programmable discrete-time type I and type II FIR filter design on the memristor crossbar structure

A new method for effective realization of discrete-time type I and type II FIR filters on the memristor crossbar structure is developed in this paper. For this purpose, first the analog input signal (to be filtered using the discrete-time filter) is discretized using the classical switched-capacitor circuit and then all of the required delayed samples of this discrete-time signal are generated using the circuit designed for this purpose. Next, the weighted sum of these delayed samples of the original discrete-time signal (which forms the output of the FIR filter under consideration) is produced using the memristor crossbar structure. The proposed structure for FIR filter design is, compared to classical methods, advantageous in the way that it does not need any processors or A/D converter. Moreover, it is fully implemented using analog devices and consequently free of round-off error. Another related contribution of this paper is the circuit proposed for automatic tuning the memristance of the given memristor to the desired value with a high accuracy. Four numerical examples, including the application of the proposed FIR filter for demodulation of AM signals, are studied and HSPICE simulations are presented.     

忆阻突触耦合Hopfield神经网络的初值敏感动力学

该文报道了3神经元Hopfield神经网络(HNN)在电磁感应电流作用下的初值敏感动力学。利用非理想忆阻突触，模拟由两个相邻神经元膜电位之差引起的电磁感应电流，构建了一种简单的4维忆阻Hopfield神经网络模型。借助理论分析和数值仿真，分析了不同忆阻突触耦合强度下的复杂动力学行为，揭示了与状态初值密切相关的特殊动力学行为。最后，设计了该忆阻HNN的模拟等效实现电路，并由PSIM电路仿真验证了MATLAB数值仿真的正确性。     

忆阻数字逻辑电路设计

该文简要概述了忆阻器理论的提出、应用现状及其在电子技术领域发展的现状,介绍了忆阻器在数字逻辑电路设计中的重要意义,并结合惠普(HP)忆阻器的二值特性及其电路特性,对忆阻器在数字逻辑电路设计中的发展、趋势及可应用前景进行了综述,可为忆阻器在数字逻辑电路中的后续研究及相关应用提供一定的参考。     

A new DDCC based memristor emulator circuit and its applications

Memristor is a new passive circuit element. The interaction of the memristor with other circuit elements is important for designers. In this paper, new memristor emulator circuit is designed using DDCC (differential difference current conveyor) based on CMOS. It is realized that the proposed emulator causes less complexity compared to other designed emulator circuits. Compatibility of memristor with CMOSs and its operation ability at high frequencies are very important for circuit design based on memristor. The emulator based on CMOS can manage to provide these two fundamental properties successfully. In order to test the proposed emulator, it is connected to memristor with both ways, serial and parallel, than MC circuit is analyzed and results are shown at the end of the paper.     

局部有源忆阻器电路及其在HR耦合神经元网络中的应用

该文提出一种新型局部有源忆阻器,使用标准非线性理论分析方法分析其特性,并通过直流伏安特性曲线来证明其局部有源性。此外,将局部有源忆阻器用于模拟生物突触,构建了一个局部有源忆阻突触耦合HR神经元网络。理论分析和数值仿真表明,在局部有源忆阻突触的影响下它能够产生多种放电模式和复杂的混沌行为。最后,实现了该局部有源忆阻突触耦合神经网络的模拟等效电路,并由功率模拟(PSIM)电路仿真验证了数值仿真的正确性。     

一种基于多态忆阻器的电压型神经网络电路

提出了一种基于多态忆阻器的神经网络电路硬件实现方法。采用2⁸ bit的惠普忆阻模型来构建存储权重的双忆阻稳定结构,结合了低功耗轨到轨运放技术以及寄存器技术,设计了模值与极性分离的绝对值电路,以及以忆阻器为核心、可进行正负浮点数运算的权值网络矩阵电路。通过Verilog-A编写激活单元,实现了多层忆阻神经网络。该电路采用并行输入和模拟信号处理方式,控制简单,无需中间数据缓存。实验结果表明,该方法有效提升了以忆阻器为核心的人工神经网络的稳定性和运行效率。     

Hybrid crossbar architecture for a memristor based cache

This paper describes a new memristor crossbar architecture that is proposed for use in a high density cache design. This design has less than 10% of the write energy consumption than a simple memristor crossbar. Also, it has up to 3 times the bit density of an STT-MRAM system and up to 11 times the bit density of an SRAM architecture. The proposed architecture is analyzed using a detailed SPICE analysis that accounts for the resistance of the wires in the memristor structure. Additionally, the memristor model used in this work has been matched to specific device characterization data to provide accurate results in terms of energy, area, and timing. The proposed memory system was analyzed by modeling two different devices that vary in resistance range and switching time. This system does not require that the memristor devices have inherent diode effects which limit alternate current paths. Therefore this system is capable of utilizing a much broader class of devices.An architectural analysis has also been completed that shows how the memory system may perform as a cache memory. A hybrid cache structure was used to alleviate the long write latencies of memristor devices. This approach consisted of the tag array being made of SRAM cells while the data array was made of the memristor circuit proposed. This hybrid scheme allows multiple reads and writes to concurrently access different sub-arrays within a cache. The performance of these novel memristor based caches was compared to SRAM and STT-MRAM based caches through detailed simulations. The results show that the memristor caches are denser and allow better performance along with lower system power when compared to the STT-MRAM and SRAM caches.     

忆阻器网络等效分析电路及其特性研究

随着忆阻器理论研究的不断深入和圆满实现,加上其独特的物理性质,其应用前景将非常乐观。该文提出了忆阻器有P型和N型两种,对其物理性质进行了分析研究,得出了它们具有对偶特征。基于此,忆阻器间可以通过适当的连接和参数选择,对外呈现出线性特性,而各自仍具备忆阻器的固有属性。同时,给出了忆阻器及其串并联的一种等效分析电路拓扑结构,仿真结果表明,该方法有效、结论正确,从而为忆阻器的理论和应用研究,特别是忆阻器网路的构建开辟了新途径。     

忆阻高通滤波电路准周期与混沌环面簇发振荡及慢通道效应

该文提出了一种忆阻高通滤波电路,它是由有源高通RC滤波器与二极管桥级联LC振荡器的忆阻模拟器并联耦合组成的。该文建立了电路方程与系统模型。基于分岔图、相平面图、庞加莱映射等数值仿真,开展了以反馈增益为可调参数的分岔分析,揭示了忆阻高通滤波电路中存在的准周期、混沌环面、混沌和多周期等簇发振荡行为。进一步地,通过快慢分析法,导出了快子系统的Hopf分岔集,并进而阐述了忆阻高通滤波电路慢通道效应的形成机理。最后,基于Multisim电路仿真验证了数值仿真结果。     

忆阻器的建模及高精度忆阻值读写电路的设计

使用现有电路元件设计了一种荷控忆阻器的理论模型。由于把忆阻器应用于存储器、神经网络、信号处理等领域均涉及到忆阻器的读写操作,并且目前忆阻器大多是数字量0和1的操作,没有模拟量的操作。所以利用了荷控忆阻器的电荷特性,给出一种描述如何读取忆阻器的模拟忆阻值的方法。利用了荷控忆阻器的频率特性,设计了一个反馈式忆阻值写电路,该电路能够在忆阻器的阻态范围内进行任意模拟量的写操作。仿真结果验证了设计的正确性。     

基于文氏振荡器的忆阻混沌电路

该文采用文氏桥振荡器和磁通控制的分段线性忆阻器,设计了一种新的单一参数控制的混沌电路。通过调节控制参数,该系统在忆阻器的非线性作用下,通过倍周期分岔产生了混沌和超混沌现象。利用常规的动力学分析手段研究了电路参数变化时系统的动力学特性,例如平衡点稳定性分析,李雅普诺夫指数谱和分岔图。为了验证电路的正确性,该文采用集成运放和压控开关实现了一个分段线性磁控忆阻器的模拟等效电路,并将该系统应用于提出的混沌电路,Pspice仿真结果与理论分析完全吻合。     

基于忆阻元件的五阶混沌电路研究

采用一个有源磁控忆阻器替换四阶蔡氏振荡器中的蔡氏二极管,导出了一个基于忆阻元件的五阶混沌电路,建立了相应电路状态变量的微分方程组.理论分析表明该忆阻混沌电路具有一个平衡点集,其稳定性随忆阻器初始状态变化而变化.采用常规的动力学分析手段研究了忆阻器初始状态发生变化时电路的动力学特性.数值仿真结果验证了理论分析的正确性.     

A novel current-controlled memristor-based chaotic circuit

In this paper, a novel third-order autonomous memristor-based chaotic circuit is proposed. The circuit has simple topology and contains only four elements including one linear negative impedance converter-based resistor, one linear capacitor, one linear inductor, and one nonlinear current-controlled memristor. Firstly, the voltage-current characteristic analysis of the memristor emulator for different driving amplitudes and frequencies are presented. With dimensionless system, the symmetry, equilibrium point and its stability are analysed. It is shown that the system has two unstable saddle-foci and one unstable saddle. A set of typical parameters are chosen for the generation of chaotic attractor. Differing from the common period-doubling bifurcation route in smooth dynamical systems, this memristive system shows abrupt transition from the coexisting period-1 limit cycles to robust chaos when varying system parameters. Various dynamical behaviors are analysed using the numerical simulations and circuit verifications.     

一种新型双忆阻混沌系统动力学及其电路实现研究

在经典的蔡氏混沌电路基础上,引入三次非线性磁控忆阻模型,利用一个磁控忆阻模型和一个荷控忆阻模型,外加一个负电导替换变形蔡氏电路中的蔡氏二极管,设计了一个五阶混沌电路,用常规的方法研究系统的基本动力学特性。通过数值仿真结果表明电路在参数变化情况下能产生Hopf分岔和反倍周期分岔两种分岔行为,并能产生双涡卷、单涡卷、极限环、同宿轨等不同轨道,出现了双单摆运动。观察混沌吸引子推广到功率与能量信号,观察到蝴蝶翅膀重叠的奇异吸引子。通过改变初始值,能产生共存吸引子和周期极限环共存现象。为了验证电路的混沌行为,将对设计的电路进行了PSpice仿真,电路仿真结果验证了理论分析的正确性。     

忆阻元件的研究进展

忆阻元件是一种联系电荷和磁链之间关系的新的无源电路元件,可以称其为第四类基本电路元件。本文首先介绍了忆阻元件的概念、基本模型及其数学表示方法,然后介绍了目前国内外的研究现状。国内研究主要集中于忆阻元件的数学模性、特性及与其它元件组成的简单电路的性能;国外的研究主要集中于忆阻元件在各方面的潜在应用以及由忆阻概念进一步推测忆容和忆感元件及其系统。     

基于双曲函数的通用型荷控忆阻器电路等效模型分析

目前,忆阻器模拟器的研究主要集中在磁控忆阻器,对荷控忆阻器模拟器的研究不多,双曲函数型的荷控忆阻器模拟器也很少涉及。因此,该文提出一种基于双曲函数的通用型荷控忆阻器模拟器。模拟器通过电压-电流的相互转换电路,实现电路中电压和电流信号之间的相互转换,再通过电路中对应的电路模块对产生的信号进行计算,最终得到通用型双曲荷控忆阻器模型。模拟器能够实现双曲正弦、双曲余弦以及双曲正切函数对应的荷控忆阻器模型。通用型双曲函数荷控忆阻器模拟器对应的等效电路,主要由运算放大器、电阻、电容、三极管等基本元件组成。分析模拟器在不同幅值以及不同频率的输入信号下的伏安特性曲线,得出荷控忆阻器模拟器符合记忆元件的基本特性。该文提出的通用型双曲函数荷控忆阻器模型,对忆阻器模型的发展具有一定的参考意义。