Reliability characteristics of GaAs and InP-based heterojunction bipolar transistors

The reliability characteristics of Heterojunction Bipolar Transistor made on GaAs and InP substrates are reviewed and ways of improving them by design, growth and processing are described. Materials for HBTs are grown by a variety of techniques (MBE, MOCVD, CBE). Their choice is made based on considerations such as satisfaction of design requirements and manufacturing but also dopant incorporation without risk of diffusion, as well as, minimization of hydrogen incorporation which may result in device degradation. The minority carrier lifetime in the base is influenced by hydrogen incorporation in C-InGaAs. Conventional alloyed and non-alloyed, as well as, refractory metallization schemes are considered for best reliability performance. The dielectric deposition scheme used for passivation plays a major role on device reliability. Good reliability performance is reported for GaAs but also for InP-based HBTs. A correlation is finally reported to exist between the low-frequency noise properties of HBTs and their reliability characteristics.     

Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area

The reliability of analog integrated circuits becomes a major concern for the semiconductor industry as technology continuously scales. Among the many contributing factors, manufacturing process induced parameter variations and lifetime operational-condition-dependent transistor aging are two major hurdles limiting the reliability of analog circuits. Process variations mainly influence the parametric yield value of the fresh circuits, while transistor aging due to physical effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), will cause another yield loss during circuit lifetime. In the past decades, the two issues were mainly studied separately by various communities, but analog designers nowadays need an accurate yet efficient method to analyze and optimize their circuits during the design phase, to ensure a more robust design tolerant of such joint effects.This paper proposes an efficient method for sizing of analog circuits for reliability. It is based on the analysis and optimization of the fresh worst-case distance value for each circuit performance, which can be used to characterize the robustness of circuits considering process variations and aging effects in terms of x-sigma. The fresh and aged sizing rules as well as the maximum area constraints are checked during the optimization. The trade-off between the circuit lifetime and the price we pay in terms of layout area is studied in detail. According to the result of this trade-off analysis, a longer circuit lifetime requires more total area to be spent in layout, and designers can ensure the circuit robustness with certain layout area consumption.     

Modeling to support reliability enhancement during product development with applications in the U.K. Aerospace industry

Reliability improvement is the conceptual norm but has not been achieved by all sectors of industry. The U.K. aerospace industry is one that has aspired to make the transition from a culture of reliability demonstration to enhancement. This paper presents action research that examines the challenges facing this industry. A statistical model is developed to help measure the likely impact of failure modes on operational performance, hence providing a basis for managing the enhancement process. The model, which has general applicability to other product development processes, is stated and justified. The industrial interventions are described and an analysis of findings is presented. The proposed model is better than traditional approaches because it provides a systematic process to capture and integrate data from different sources to estimate reliability by directly measuring the engineering improvement achieved through product design and development. The estimates can be used to inform a traceable coherent argument about the level and growth in reliability to management and the customer as well as to provide insight into the impact of alternative engineering modifications to the design team. The modeling process has contributed to the partial transition to reliability enhancement of a consortium of companies who have changed their standard operating procedures to reflect the lessons learned from the research intervention. The insights gained contribute to an understanding of how the U.K. aerospace industry is changing its management of reliability enhancement in design.     

Degradation behavior in upstream/downstream via test structures

The miniaturization process of CMOS components creates new challenges for the development of integrated circuits. Especially the connections with a tungsten via between two metal layers can be a problem. Changes in geometry can bear on reliability problems. For a robust metallization design it is necessary to know, how strong the influence of the tungsten via alignment affects the physical behavior. The lifetime of up- and downstream test structures with different overlaps as well as strong misalignment was determined by measurements. Investigations have shown that the alignments have a noticeable effect on the reliability and performance of test structures. The downstream line shows the expected lifetime behavior. For the upstream line no influence of the misalignment on the lifetime was found. Simulations are taken into account to understand the thermal–electrical and mechanical behavior.     

Deep-submicrometer large-angle-tilt implanted drain (LATID)technology

Deep-submicrometer large-angle-tilt implanted drain (LATID) technology is described. It is found by Monte Carlo process simulation and SIMS measurements that a sufficiently long n^- region can be formed under the gate by taking advantage of large-angle-tilt implant and successfully without ion channeling by taking care of the implant direction. A design that offsets the n⁺ implant by sidewall spacers to suppress the n⁺-gate overlap to zero while keeping the n^- region fully overlapped with the gate is found to be crucial for improved performance and reliability. The device performance, such as current drivability and short-channel effects, is described, and the circuit speed is investigated. Hot-carrier effects such as lateral electric field and device lifetime over a wide range of drain structures are also investigated. The tradeoff between device performance and hot-carrier reliability in deep-submicrometer LATID FETs is discussed     

Building-in ESD/EOS reliability for sub-halfmicron CMOS processes

MOSFET design in high performance CMOS technologies is driven primarily by performance requirements and reliability issues such as hot carrier degradation. These requirements generally lead to processes that are inherently weak in terms of ESD and EOS. This paper presents a case of building-in ESD/EOS reliability through nMOSFET drain design for a 0.35 μm CMOS process that compromises neither the performance nor the hot carrier reliability. Three process options were considered: nLDD or nDDD ESD implants, and a silicide-block option. The nDDD option for the I/O transistors was chosen as it complied with the performance and reliability (ESD and HCI) specifications and its implementation cost was lower than a silicide-block option. The paper presents data demonstrating the advantages of the nDDD solution over the other alternatives. Particularly, pulsed-EOS and HBM-ESD data, the impact of layout parameters on ESD performance, and hot-carrier data are reviewed     

Interconnect Lifetime Prediction for Reliability-Aware Systems

Thermal effects are becoming a limiting factor in high-performance circuit design due to the strong temperature dependence of leakage power, circuit performance, IC package cost, and reliability. While many interconnect reliability models assume a constant temperature, this paper analyzes the effects of temporal and spatial thermal gradients on interconnect lifetime in terms of electromigration, and presents a physics-based dynamic reliability model which returns reliability equivalent temperature and current density that can be used in traditional reliability analysis tools. The model is verified with numerical simulations and reveals that blindly using the maximum temperature leads to too pessimistic lifetime estimation. Therefore, the proposed model not only increases the accuracy of reliability estimates, but also enables designers to reclaim design margin in reliability-aware design. In addition, the model is useful for improving the performance of temperature-aware runtime management by modeling system lifetime as a resource to be consumed at a stress-dependent rate     

An algorithmic approach to increased reliability through standbyredundancy

The authors address the issue of optimal redundancy allocation, viz, improving the reliability of a system by adding cold-standby spares, through an algorithmic approach that uses the unique characteristics of an assumed underlying failure distribution. Although the approach applies to systems with mixed parallel and series configurations, the discussion is limited to a series system of components. The lifetime distributions of individual parts are of the phase type. This class of probability distributions is chosen for its ease of numerical implementation. The formulation of the reliability enhancement problem is applied, and several heuristic design algorithms are examined     

Markov process based reliability model for laser diodes in space radiation environment

The reliability of laser diodes is a prerequisite for use in satellite optical communication systems, which is significant influenced by both displacement damage effect and annealing effect. A reliability model was proposed to evaluate the reliability and lifetime for laser diodes in space radiation environment. Degradation process is separated into discrete states, and reliability model is subsequently established based on Markov process. The Markov process consists of a Poisson process and an exponential process, representing the displacement damage effect and annealing effect, respectively. Reliability characteristics of a given laser diode are simulated over 100,000 h, and applicability of this reliability model is demonstrated by analyzing the variety trend of probability density of performance states.     

Reliability of Implantable Electronic Devices: Two Case Studies

This paper presents two case studies of the reliability of implantable neural stimulators, designed specifically as auditory prostheses. These reliability results, collected from lifetime experiments, failure analysis, and manufacturing testing, confirm the crucial roles of well planned design and packaging in system reliability. Guidelines are proposed for the design of reliable implantable systems. The improvements in the second design can be traced to the better electronic design and manufacture, the careful considerations of metallurgical characteristics in bonding and connecting components, the package design, and the exhaustive tests at each step of the manufacturing process. The reliability of these designs, and of implantable systems in general, is by no means resolved nor well understood. There is a definite need for comprehensive data bases and techniques for reliability analysis of these systems as well as the systematic manufacturing test for reliability assurance, which is a growing concern in the research and development of artificial organs.     

A unified design methodology for CMOS tapered buffers

In this paper, the various disparate approaches to CMOS tapered buffer design are unified into an integrated design methodology. Circuit speed, power dissipation, physical area, and system reliability are the four performance criteria of concern in tapered buffers, and each places a separate, often conflicting, constraint on the design of a tapered buffer. Enhanced short-channel tapered buffer design equations are presented for propagation delay and power dissipation, as well as a new split-capacitor model of hot-carrier reliability of tapered buffers and a two-component physical area model. Each performance criterion is individually investigated and analyzed with respect to the number of stages and tapering factor, and the interaction of the four criteria is examined to develop both a qualitative and a quantitative understanding of the various design tradeoffs. The creation of process dependent look-up tables for optimal buffer design is described, and a methodology to apply these look-up tables to application-specific tapered buffers for both unconstrained and constrained systems is developed     

基于加速性能退化试验的板级可靠性评估

传统的可靠性评估方法一般基于失效寿命数据,而目前对于高可靠长寿命的电子产品,很难通过加速试验获得其失效寿命时间。为解决这一矛盾,将性能退化理论引入到传统可靠性评估中,提出了基于失效数据及加速性能退化的可靠性评估的新方法。应用某型雷达24V/2A稳压电源板加速性能退化试验进行验证,结果表明该方法用于高可靠长寿命电子装备的可靠性评估是正确有效的。     

EOMR: An Energy-Efficient Optimal Multi-path Routing Protocol to Improve QoS in Wireless Sensor Network for IoT Applications

The wireless sensor network based IoT applications mainly suffers from end to end delay, loss of packets during transmission, reduced lifetime of sensor nodes due to loss of energy. To address these challenges, we need to design an efficient routing protocol that not only improves the network performance but also enhances the Quality of Service. In this paper, we design an energy-efficient routing protocol for wireless sensor network based IoT application having unfairness in the network with high traffic load. The proposed protocol considers three-factor to select the optimal path, i.e., lifetime, reliability, and the traffic intensity at the next-hop node. Rigorous simulation has been performed using NS-2. Also, the performance of the proposed protocol is compared with other contemporary protocols. The results show that the proposed protocol performs better concerning energy saving, packet delivery ratio, end-to-end delay, and network lifetime compared to other protocols.

     

RF CMOS reliability simulations

We present a simulation approach to assess the reliability of an RF CMOS circuit under user conditions, based on existing DC degradation models for gate-oxide breakdown and hot-carrier degradation. The simulator allows for lifetime prediction of circuits that can withstand multiple breakdown events. Simulation results show that three power amplifiers with comparable initial circuit performance show an astronomic difference in reliability. The tool thus proves to be an asset in the analog design process.     

NBTI product level reliability for a low-power SRAM technology

We present a methodology to investigate product level NBTI reliability for the 90 nm technology node including the correlation between transistor, circuit, and product level NBTI reliability. NBTI reliability lifetime, dielectric breakdown, and gate leakage currents pose an important limitation to the maximum applicable supply voltage across the gate oxide. Product standby currents and regulator design are highly influenced by transistor reliability. We will present product reliability data ensuring sufficient product level reliability as well as their correlation attempts to transistor level reliability data.     

《射频通信电路》教材的编写思路和内容特点

射频电路已成为移动通信系统的设计瓶颈,现在射频集成电路设计师也已成为热门职业之一。我们为本科生提供了一本讲述射频通信电路的基础教科书。本文介绍了该书的三个特点：一是在主要讲述射频通信电路设计的同时,也提供了其它相关领域的基础背景知识;二是对收发机各模块的性能指标,原理和设计方法进行了系统地论述;三是将系统设计,模块设计和模块应用紧密结合在一起。     

Optimal design of reliable network systems in presence of uncertainty

In practice, network designs can be based on multiple choices of redundant configurations, and different available components which can be used to form links. More specifically, the reliability of a network system can be improved through redundancy allocation, or for a fixed network topology, by selection of highly reliable links between node pairs, yet with limited overall budgets, and other constraints as well. The choice of a preferred network system design requires the estimation of its reliability. However, the uncertainty associated with such estimates must also be considered in the decision process. Indeed, network system reliability is generally estimated from estimates of the reliability of lower-level components (nodes & links) affected by uncertainties. The propagation of the estimation uncertainty from the components degrades the accuracy of the system reliability estimation. This paper formulates a multiple-objective optimization approach aimed at maximizing the network reliability estimate, and minimizing its associated variance when component types, with uncertain reliability, and redundancy levels are the decision variables. In the proposed approach, Genetic Algorithms (GA) and Monte Carlo (MC) simulation are effectively combined to identify optimal network designs with respect to the stated objectives. A set of Pareto optimal solutions are obtained so that the decision-makers have the flexibility to choose the compromised solution which best satisfies their risk profiles. Sample networks are solved in the paper using the proposed approach. The results indicate that significantly different designs are obtained when the formulation incorporates estimation uncertainty into the optimal design problem objectives.     

Indirect adaptive control using the novel online hypervolume-based differential evolution for the four-bar mechanism

Four-bar mechanisms have increased their use in current applications from industrial to rehabilitation systems. These applications become more demanding over time, and the control systems are required to provide them higher accuracy, lower energy consumption, and an extended lifetime, among other conflicting features. In addition to the previously mentioned demands, four-bar mechanisms have highly nonlinear dynamics and are often subject to external loads that make them difficult to control. In this paper, an indirect adaptive control based on online multi-objective optimization is proposed to regulate the speed of the four-bar mechanism and increase its lifetime by smoothing the control action under the effects of uncertainties. This consists of a multi-objective optimization process for the online identification of the model parameters that fulfill the performance demands of the mechanism. In this process, a multi-objective optimization problem is stated and then solved by the novel Online Hypervolume-based Differential Evolution (O-HV-MODE) in such a way that several promising model parameter configurations are found in real-time, with different trade-offs among the performance demands. O-HV-MODE takes advantage of the past problem knowledge to accelerate the search for new solutions and uses the Hypervolume metric to increase their convergence and diversity. Then, a single model parameter configuration is selected based on the application necessities and is further used in the nonlinear compensator of the computed-torque controller, while a fixed-gain PD control loop is used for stabilization. The proposed control is validated through experimental tests and the reliability of the results with the 99% Confidence Interval test. Also, the proposal is compared with state-of-the-art linear and non-linear control approaches.     

An analysis of the reliability and design optimization of aluminium ribbon bonds in power electronics modules using computer simulation method

Ribbon bonding technique has recently been used as an alternative to wire bonding in order to improve the reliability, performance and reduce cost of power modules. In this work, the reliability of aluminium and copper ribbon bonds for an Insulated Gate Bipolar Transistors (IGBT) power module under power cycling is compared with that of wire bonds under power and thermal cycling loading conditions. The results show that a single ribbon with a cross section of 2000 μm × 200 μm can be used to replace three wire bonds of 400 μm in diameter to achieve similar module temperature distribution under the same power loading and ribbon bonds have longer lifetime than wire bonds under cyclic power and thermal cycling conditions. In order to find the optimal ribbon bond design for both power cycling and thermal cycling conditions, multi-objective optimization method has been used and the Pareto optimal solutions have been obtained for trade off analysis.     

Improving reliability performance of diffusion‐based molecular communication with adaptive threshold variation algorithm

Reliability is a vital issue in the area of communication. In this paper, we particularly investigate the reliability issue for diffusion‐based molecular communication. First, we present the communication process in system model, where a classified model is further developed at the side of receiver to divide received molecules into signal, inter‐symbol interference, and noise branches. The classified model is used to prove the feasibility and necessity of improving the reliability performance. Second, an adaptive threshold variation (ATV) algorithm is designed to be able to improve the reliability performance that enables the receiver to adapt the channel condition properly through learning process. Furthermore, the complexity of ATV and the performance in various noisy conditions are discussed. An expression of signal to interference plus noise ratio is defined in numerical simulation to verify our goal with variational parameters, as well as with the adoption of ATV algorithm. The results indicate that ATV algorithm works well in general case in improving reliability performance for diffusion‐based molecular communication.