DSP-Driven Self-Tuning of RF Circuits for Process-Induced Performance Variability

In the deep-submicrometer design regime, RF circuits are expected to be increasingly susceptible to process variations, and thereby suffer from significant loss of parametric yield. To address this problem, a postmanufacture self-tuning technique that aims to compensate for multiparameter variations is presented. The proposed method incorporates a “response feature” detector and “hardware tuning knobs,” designed into the RF circuit. The RF device test response to a specially crafted diagnostic test stimulus is logged via the built-in detector and embedded analog-to-digital converter. Analysis and prediction of the optimal tuning knob control values for performance compensation is performed using software running on the baseband DSP processor. As a result, the RF circuit performance can be diagnosed and tuned with minimal assistance from external test equipment. Multiple RF performance parameters can be adjusted simultaneously under tuning knob control. The proposed concepts are illustrated for an RF low-noise amplifier (LNA) design and can be applied to other RF circuits as well. A simulation case study and hardware measurements on a fabricated 1.9-GHz LNAs show significant parametric yield enhancement (up to 58%) across the critical RF performance specifications of interest.      

Built-in Self Test of RF Subsystems with Integrated Detectors

This paper describes a built-in self test technique for RF subsystems, using low-overhead on-chip detectors to calculate circuit specifications. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. The detector has small area overhead with a low-frequency output. A test chip was fabricated in a commercial 0.18 μm CMOS process. By using on-chip detectors in a loopback setup, both the system performance and specifications of the individual components can be accurately measured. Measurements show accurate prediction of system and component specifications.     

A test and calibration strategy for adjustable RF circuits

A test and calibration strategy suitable for adjustable RF circuits is presented in this paper. Certain performance-affecting circuit elements are designed to be digitally controllable, providing the capability to adjust the performance characteristics of a circuit’s instance around their post-fabrication values, throughout a set of discrete states of operation. The alternate test methodology is adopted for test and calibration and a set of optimally selected test observables is used to develop regression models for the prediction of the circuit’s performance characteristics in every state of operation. In the test phase, measurements of the test observables are obtained from a subset of the circuit’s states. The processing of these observables provides accurate prediction of the RF circuit’s performance characteristics in all available states and enables the discrimination of defect-free from defective circuits. The latter is further accomplished by the exploitation of an extended superset of the test observables, the use of which intends to maximize fault coverage. Moreover, the predicted performance characteristics are also used to examine compliance with the specifications and to allow calibration of the RF circuit by identifying the appropriate state of operation at which all specifications are met and, consequently, by forcing the circuit to operate in this specific state. The efficiency of the proposed technique has been validated by its application to a typical differential RF Mixer designed in a 0.18 μm CMOS technology. Simulation results have been obtained and assessed.     

A highly integrated multifunction macro synthesizer chip (MMSC) forapplications in 2-18 GHz synthesized sources

A highly integrated monolithic microwave integrated circuit (MMIC) that acts as the core of the RF section of a synthesized source is developed using commercially available 0.2-μm pseudomorphic high electron mobility transistor (PHEMT) technology. Measured performance is shown up to 18 GHz. The same system architecture is able to produce synthesized output through 40 GHz with modifications of some critical building blocks of the chip. The chip performs all the frequency selection and tuning functions. It has more than 30 RF blocks integrated on an area of 4.27×4.68 mml. Some individual blocks operate through 40 GHz     

Self-Calibration of Output Match and Reverse Isolation in LNAs Based Switchable Resistor

With recent advances in CMOS process technology, the concept of system-on-a-chip (SoC) has been realized by integrating more and more digital and analog building blocks in a single chip [2, 9]. Additionally, these advances have brought several new types of processes faults (soft fault) and higher process variations to RF circuit resulting performances degradation. In order to compensate the RF circuit performance, a novel efficient self-calibration method for 865?C870?MHz low noise amplifiers (LNAs), which constitute a RF mixed-signal circuit, is developed. This technique detects any deviation from the output match and from reverse isolation using built-in self test (BIST) methods, and then provides a corrective measure to recalibrate these LNA performances to the possible optimal value. This proposed self-calibration technique uses a switchable resistor which has been designed to investigate its ability to compensate for output match S22 and reverse isolation S12 without affecting other LNA performances. The use of this method saves space on chip and prevents adding switch resistor noise. In addition, the new calibration design shows the ability to calibrate S22 and S12 due to the catastrophic fault.     

GPS基带芯片中存储器的可测性设计

GPS基带芯片中嵌入的存储器采用存储器内建自测试(Memory Built-in-Self-Test,MBIST)技术进行可测性设计,并利用一种改进型算法对存储器内建自测试电路的控制逻辑进行设计,结果表明整个芯片的测试覆盖率和测试效率均得到显著提高,电路性能达到用户要求,设计一次成功.     

Current monitoring circuit for fault detection in CMOS integrated circuit

This article presents a built-in current sensor (BICS), which detects faults using the current testing technique in CMOS integrated circuits. This circuit employs cross-coupled PMOS transistors, which are used as current comparators. The proposed circuit has a negligible impact on the performance of the circuit under test (CUT). In addition, no extra power dissipation and high-speed fault detection are achieved. It can be applied to deep sub-micron processes. The validity and effectiveness are verified through the HSPICE simulation on circuits with faults. The entire area of the test chip is 116×65 μm². The BICS occupies only 41×17 μm² of the area of the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix 0.35 μm 2-poly-4-metal N-well CMOS process.     

基于TD-SCDMA的CMOS低通滤波器的设计

这里提出一种基于时分同步码多址技术（TD-SCDMA）的互补金属氧化物半导体（CMOS）滤波器带宽校正方法及校正电路。该方法应用于RS1012芯片（TDSCDMA无线收发芯片）,该芯片采用0.18um射频（RF）COMS工艺。滤波器带宽的调节范围和调节精度在理论和投片中都得到了验证。实现该方法的RC校正电路结构简单,版图面积很小,只有0.04 mm2,电流仅为600 uA。校正电路最大调节范围设计值为＋30%,校正精度为＋2.1%,此测试结果与理论计算是一致的。     

Estimation and compensation of process-induced variations in capacitors for improved reliability in integrated circuits

This paper describes a method for the estimation of capacitor process variations in integrated circuits and for the subsequent compensation of such variations through a calibration scheme that exploits a variable capacitor bank. An architecture for the calibration circuit is proposed, and various problems that arise during implementation are discussed. The design consists of an oscillator whose output frequency is inversely proportional to the capacitor value and simple state machine for measurement of capacitor process variations. The design of optimum capacitor bank is described together with the adequate tuning plan. The circuit is fabricated and verified in 130 nm RF CMOS process and can be easily scaled to sub-100-nm technologies.     

Fabrication, RE performance, and yield of a combined limitingamplifier and dual-modulus prescalar GaAs IC chip

Production technology details, RF performance, and yield results for an ECL-compatible, L-band, limiting dual-modulus (÷10/11) prescalar are presented. Monolithic integration of analog and digital circuit functions is achieved using refractory self-aligned-gate FET technology. When tested with -22-dBm input signal power, one lot of six wafers had a total RF chip yield of 19% with a best-wafer yield of 43%. The average operating frequency was 1.45 GHz (SD=51 MHz) with an average power dissipation of 696 mW (SD=23 mW)     

一种激光雷达探测模块控制电路的设计和制作

传统上使用机械旋钮调节光电倍增管 (PMT) 增益的方法不仅存在需要人为依据经验手动操作、准确性差等 弊端, 而且 PMT 增益易受温度影响, 需要根据环境温度动态调整 PMT 的高压, 这些局限性都不利于其在激光雷达系 统中的应用。为了便于对 PMT 进行增益调节并保持 PMT 增益的稳定, 设计了可用于激光雷达系统的 PMT 控制电路 板, 该电路可使用计算机实现增益调节和高压的温度自适应调节, 从而精简了信号探测系统的结构与体积, 提升了信 号的稳定性。本工作采用内置高压电源的 H10721-20 型 PMT, 并基于 STM32 单片机结合数模转换器 (DAC) 和外围 电路完成控制电路板的设计并进行实际制作。进一步对使用电位器调节的 PMT 和利用所提出的控制方法进行调节 的 PMT 进行了高压稳定性的对比实验, 并对使用 PMT 控制电路板的米散射激光雷达的性能进行了测试。实验结果 表明所提出的控制方法可实现更稳定的 PMT 增益控制, 设计的 PMT 控制电路板具有良好的可靠性。     

A Frequency Tuning Method for a Planar Inverted-F Antenna

A novel method is presented for electrically tuning the frequency of a planar inverted-F antenna (PIFA). A tuning circuit, comprising an RF switch and discrete passive components, has been completely integrated into the antenna element, which is thus free of dc wires. The proposed tuning method has been demonstrated with a dual-band PIFA capable of operating in four frequency bands. The antenna covers the GSM850, GSM900, GSM1800, PCS1900 and UMTS frequency ranges with over 40% total efficiency. The impact of the tuning circuit on the antenna's efficiency and radiation pattern have been experimentally studied through comparison with the performance of a reference antenna not incorporating the tuning circuit. The proposed frequency tuning concept can be extended to more complex PIFA structures as well as other types of antennas to give enhanced electrical performance.     

RF calibration of on-chip DfT chain by DC stimuli and statistical multivariate regression technique

The problem of parameter variability in RF and analog circuits is escalating with CMOS scaling. Consequently every RF chip produced in nano-meter CMOS technologies needs to be tested. On-chip Design for Testability (DfT) features, which are meant to reduce test time and cost also suffer from parameter variability. Therefore, RF calibration of all on-chip test structures is mandatory. In this paper, Artificial Neural Networks (ANN) are employed as a multivariate regression technique to architect a RF calibration scheme for DfT chain using DC- instead of RF (GHz) stimuli. The use of DC stimuli relaxes the package design and on-chip routing that results in test cost reduction. A DfT circuit (RF detector, Test-ADC, Test-DAC and multiplexers) designed in 65 nm CMOS is used to demonstrate the proposed calibration scheme. The simulation results show that the cumulative variation in a DfT circuit due to process and mismatch can be estimated and successfully calibrated, i.e. 25% error due to process variation in DfT circuit can be reduced to 2.5% provided the input test stimuli is large in magnitude. This reduction in error makes parametric tests feasible to classify the bad and good dies especially before expensive RF packaging.     

X波段ISAR波形激励与失真补偿

论述一种X波段可扩充相控阵高分辨逆合成孔径雷达波形激励设计过程,分析了波形激励及其内单元电路的原理及指标分配方法,该波形激励采用调制器产生宽带线性调频(LFM)信号,且采用了倍频法提高激励带宽,突破了宽带信号产生及校正、宽带激励等宽带相控阵雷达系统的关键技术,解决了宽带、窄带系统的波形激励硬件共用问题,随整机进行外场实验,性能指标满足要求。     

A New Automatic Compensation Network for System‐on‐Chip Transceivers

This paper proposes a new automatic compensation network (ACN) for a system‐on‐chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on‐chip ACN using 0.18 µm SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design‐for‐testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.     

A self-calibration technique for wide tuning range PLLs

This paper presents a new calibration technique applicable for wide tuning range phase locked loops (PLLs) using very low gain voltage controlled oscillators (VCO). This technique uses the PLL main loop for the coarse and fine tuning of the VCO. Instead of using two loops which has been reported in previous works, in this work the VCO tuning voltage is used to calibrate the VCO switch capacitor array. Since the proposed calibration circuit operates in a closed loop form, it can be used for channel selection as well as adjusting for process, voltage and temperature variations. In addition, the calibration circuit has been used to set the VCO tail current in order to optimize VCO phase noise. A prototype frequency synthesizer has been designed in 0.18-μm CMOS process to work for a frequency range from 2.4 to 2.72 GHz. Simulation results show that using the proposed technique, a spur level of ?60 dB at 5 MHz offset from carrier was achieved while having negligible power overhead.     

宽带超短波射频前端的设计和实现

宽带超短波射频前端是软件无线电通信平台的关键部分之一。在此介绍了集成宽带调制芯片TRF372017和解调芯片ADRF6850,设计了宽带超短波射频模块的实现方案。基于这两款芯片分别实现了发送电路和接收电路,并结合软件无线电基带处理平台加载了宽带通信波形进行测试。测试结果显示,该射频模块具有较好的性能,且具有体积小,功耗低,增益控制范围大等优点。     

A modified closed-loop auto frequency calibration technique for a 1.571-GHz integer-N PLL

In this paper, a modified closed-loop auto frequency calibration technique (MCL-AFC) is adopted in an integer-N phase-locked loop (PLL) for GPS-L1 application. The ignorance of circuit initial conditions setting in the closed-loop AFC may cause the start-up trap and long frequency calibration time. To solve these problems, the MCL-AFC technique is introduced. The process of MCL-AFC is listed below: first, initialisation process is only used for start-up of PLL; second, closed-loop voltage comparison process and open-loop switching process will take place alternately until optimum frequency control words are obtained. Tuning voltage searching range is reduced by half during the voltage comparison process since VCO’s tuning voltage is set to half of supply voltage through switching process. The MCL-AFC circuit is implemented in a 1-poly 6-metal 180 nm CMOS process and its chip area is 0.0167 mm². The measured locked output frequency of the PLL is 1.571 GHz and the out-band phase noise is ?131.9dBc/Hz at 1 MHz. The calibration time of PLL with MCL-AFC circuit is reduced to only 5µs while whole locking time is about 10.2µs.     

5GHz0.18μm CMOS宽带LC VCO

采用0.18μm RF CMOS工艺,设计了一个5GHz的宽带电感电容压控振荡器。该压控振荡器的电路结构选用互补交叉耦合型,采用噪声滤波技术降低相位噪声,并采用开关电容阵列扩展其调谐范围。后仿真结果表明,实现了4.44～5.44GHz的宽调谐。振荡器的电源电压为1.8V,工作电流为2.78mA,版图面积为0.37mm2。     

Principles of large-signal MESFET operation

The large-signal RF operating principles of MESFET amplifiers are investigated using a circuit simulator that incorporates a physics based MESFET model which has been augmented with a new gate breakdown model. It is demonstrated that the main saturating mechanisms of the MESFET under large-signal RF operation are forward and reverse conduction of the gate electrode. Maximized RF performance of MESFET amplifiers is obtained by optimally positioning the dynamic load line relative to the RF-IV plane. The position of the dynamic V-I characteristic is determined by device breakdown, bias, and circuit tuning conditions