A novel full-wave rectifier/sinusoidal frequency doubler topology based on CFOAs

In this paper, a high-efficiency class-F power amplifier (PA) is designed using integration between a low voltage p-HEMT transistor and a miniaturized microstrip suppressing cell. It results in nth harmonic suppression and high power added efficiency (PAE) under low radio frequency (RF) input powers. The simulation is performed based on harmonic balance analysis. The proposed power amplifier is fabricated, and measurements results validated the simulations. The proposed power amplifier operates at 1.8 GHz with 100 MHz bandwidth and an average PAE of 71.1%, with very low drain voltage of 2 V. At fundamental frequency of 1.8 GHz, the maximum measured PAE is 73.5% at about 12 dBm RF input power. The maximum output power and gain are 23.4 and 17.5 dBm in RF input power ranges of 0–12 dBm, respectively. The fabricated class-F PA with such characteristics can be used for power amplifications in wireless transmitters such as 4G (4th generation)-LTE (long term evolution) communication systems.     

New fully-differential amplifier-less pipelined ADC with wide power scalability and ERBW

A 24 GHz power amplifier for direct-conversion transceiver using standard 0.18 μm CMOS technology is reported. The three-stage power amplifier comprises two cascaded cascode stages for high power gain, followed by a common-source stage for high power linearity. To increase the saturated output power (P_sat) and power-added efficiency (PAE), the output stage adopts a Wilkinson-power-divider- and combiner-based two-way power dividing and combining architecture. The power amplifier consumes 163.8 mW and achieves power gain (S₂₁) of 22.8 dB at 24 GHz. The corresponding 3-dB bandwidth of S₂₁ is 4.2 GHz, from 22.7 to 26.9 GHz. At 24 GHz, the power amplifier achieves P_sat of 15.9 dBm and maximum PAE of 14.6 %, an excellent result for a 24 GHz CMOS power amplifier. In addition, the measured output 1-dB compression point (OP_1dB) is 7 dBm at 24 GHz. These results demonstrate the proposed power amplifier architecture is very promising for 24 GHz short-range communication system applications.     

基于双向牵引与谐波抑制的Doherty功率放大器设计

为了提高功率放大器(Power Amplifier,PA)的效率,提出一种基于双向牵引与谐波抑制的对称式Doherty功率放大器(Symmetrical Doherty Power Amplifier,SDPA)结构。该结构在经典DPA 的基础上,首先利用多谐波双向牵引技术获得功放的实际最佳阻抗,然后对主辅功放的二、三次谐波进行抑制,降低了漏极电压电流的重合,最后通过添加补偿线调节主辅功放的功率分配,使得功放整体获得最大的效率。为了验证上述谐波抑制理论与双向牵引技术的正确性,采用GaN 器件设计了一款应用在4G 基站的SDPA。测试结果显示:SDPA 在2.6 GHz 处的小信号增益为12.6 dB,2.5-2.7 GHz 频段内的增益平坦度为±0.75 dB,频带内的S11小于-11.9 dB,在三载波测试时经过数字预失真(Digital Pre-Distortion,DPD)系统纠正后的相邻信道泄漏比(Adjacent Channel Leakage Rate,ACLR)约为-45 dBc,SDPA 在峰值功率点附近的功率附加效率(Power Added Efficiency,PAE)接近60%,在回退点处的PAE约为48%。实验结果验证了该设计方案的可行性。     

1.95GHz Doherty功率放大器设计

基于SMIC 0.18 μm RF CMOS工艺,设计了一款1.95 GHz的Doherty功率放大器.为了保持两路功放相位最大一致性,主功放(PA1)和辅功放(PA2)采用了同一种CMOS功率放大器,仅改变其偏压使其工作在不同模式.CMOS功率放大器为工作于AB类的两级放大电路,集成了输入和级间匹配网络;功分器以及λ...     

A highly linear and efficient differential CMOS power amplifier with harmonic control

A 2.45 GHz fully differential CMOS power amplifier (PA) with high efficiency and linearity is presented. For this work, a 0.18-/spl mu/m standard CMOS process with Cu-metal is employed and all components of the two-stage circuit except an output transformer and a few bond wires are integrated into one chip. To improve the linearity, an optimum gate bias is applied for the cancellation of the nonlinear harmonic generated by g/sub m3/ and a new harmonic termination technique at the common source node is adopted along with normal harmonic termination at the drain. The harmonic termination at the source effectively suppresses the second harmonic generated from the input and output. The amplifier delivers a 20.5dBm of P/sub 1dB/ with 17.5 dB of power gain and 37% of power-added efficiency (PAE). Linearity measurements from a two-tone test show that the power amplifier with the second harmonic termination improves the IMD3 and IMD5 over the amplifier without the harmonic termination by maximally 6 dB and 7 dB, respectively. Furthermore, the linearity improvements appear over a wide range of the power levels and the linearity is maintained under -45 dBc of IMD3 and -57dBc of IMD5 when the output power is backed off by more than 5dB from P/sub 1dB/. From the OFDM signal test, the second harmonic termination improves the error vector magnitude (EVM) by over 40% for an output power level satisfying the 4.6% EVM specification.     

An improved 860–960 MHz fully integrated CMOS power amplifier designation for UHF RFID transmitter

An improved design of 860–960 MHz fully integrated CMOS power amplifier (PA) for UHF RFID transmitter is presented in this paper. It utilizes three stage differential structure, including common-source structure applying RC feedback circuit to improve linearity, cascade structure adopting self-biased cascode technique and self-forward-body-bias (SFBB) technique to overcome shortcomings of low breakdown voltage and to reduce supply voltage respectively in order to obtain high output power, high efficiency and low supply voltage. By integrating these techniques organically, simulation results demonstrate that the circuit provides 21 dBm output power and 35% power-added efficiency (PAE) with 3 V supply. A comparison with other PAs operating in similar frequencies shows the proposed LNA has advantages of higher output power, higher PAE, higher linearity and lower supply voltage.     

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-$mu$ m 2.5-V standard I/O FETs in a 0.13- $mu$m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.      

A 900 MHz,21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

A two-stage differential linear power amplifier(PA) fabricated by 0.18μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power,efficiency and harmonic performance.Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency(PAE) is 35.4%,the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled.The total area with ESD protected PAD is 1.2×0.55 mm~2.Sy...     

CMOS linear high performance push amplifier for WiMAX power amplifier

In this work a novel and efficient approach is proposed to optimize the linearity and efficiency of power amplifiers used in mobile WiMAX applications. A linear and high performance push amplifier is designed and implemented in 0.18 μm CMOS technology to enhance the linearity of a class-E switched-mode power amplifier. The proposed push amplifier consists of two sections; analog and switching sections. The analog section provides required linearity and the switching section guarantees satisfying total efficiency level. Each block is designed and optimized to meet required specifications. The core power amplifier which is a class-E switched-mode power amplifier is also designed to have maximum possible efficiency. The implemented circuit is simulated using HSPICERF and TSMC models for active and passive elements. The proposed power amplifier provides a maximum output power of 25 dBm and a power added efficiency (PAE) as high as 48% at 2.5 GHz operation frequency and supply voltage of 1.8 V. At 1 dB compression point this PA exhibits 23 dBm of output power with 42% PAE and 4.5% EVM which was appropriate for 64QAM OFDM signals.     

A High-Efficient CMOS RF Power Amplifier With Automatic Adaptive Bias Control

A 2.4-GHz Doherty power amplifier (PA) is developed in 0.18-mum CMOS technology. An automatic adaptive bias control circuit is integrated with the auxiliary PA to improve the overall performance of the PA. Operated at 3V, the P_{1 dB} and associated power-added-efficiency (PAE) of the PA are 21dBm and 33%, respectively. At the output power 6-dB backoff from P_{1 dB}, the PAE remains 21%. The limited PAE degradation at backoff power levels makes the PA suitable for the applications with high peak-to-average power ratio     

Ultra‐small Form‐Factor Helix on Pad‐Type Stage‐Bypass WCDMA Tx Power Amplifier Using a Chip‐Stacking Technique and a Multilayer Substrate

A fully integrated small form‐factor HBT power amplifier (PA) was developed for UMTS Tx applications. For practical use, the PA was implemented with a well configured bottom dimension, and a CMOS control IC was added to enable/disable the HBT PA. By using helix‐on‐pad integrated passive device output matching, a chip‐stacking technique in the assembly of the CMOS IC, and embedding of the bulky inductive lines in a multilayer substrate, the module size was greatly reduced to 2 mm × 2.2 mm. A stage‐bypass technique was used to enhance the efficiency of the PA. The PA showed a low idle current of about 20 mA and a PAE of about15% at an output power of 16 dBm, while showing good linearity over the entire operating power range.     

基于GaN器件的连续型高效宽带功率放大器设计*

提出一种高效宽带功率放大器的设计方法,并基于GaN HEMT 器件CGH40010F 设计了验证电路。利用功放管输出寄生参数的等效网络,将基于连续型功放理论得到的负载阻抗转换到封装参考面上,并利用多谐波双向牵引技术对转换后的负载阻抗进行适当调整,使二次谐波负载阻抗位于高效率区以及基频负载阻抗能够获得高功率附加效率和高输出功率。谐波阻抗位于高效率区使得匹配网络的设计简化为基频匹配网络的设计,降低了对谐波阻抗匹配的难度和宽带匹配网络设计的复杂度。实验结果表明:在1GHz -3GHz 工作频带(相对带宽100%)内,功率附加效率在53%-64.6%之间,输出功率为39.5±2dBm,增益为11.5±2dB,二次谐波小于-15dBc,三次谐波小于-25dBc。     

High Efficiency RF Power Amplifier Designed With Harmonic Real-Time Active Load-Pull

In this work, a high efficiency p-HEMT radio frequency power amplifier (PA) is designed using a new multiharmonic real-time active load-pull using the large signal network analyzer. This technique synthesizes a large set of instantaneous load mismatches to quickly find the optimal harmonic impedances, so as to achieve high PA efficiency in a shortened design cycle. At 2 GHz a demo power amplifier implemented with a p-HEMT demonstrated a power added efficiency (PAE) of 68.5% for 18.0 dBm output power, while achieving a maximum PAE of 75% below the 1 dB compression point for 18.6 dBm output power.     

High‐Efficiency CMOS Power Amplifier Using Uneven Bias for Wireless LAN Application

This paper proposes a high‐efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current‐mode transformer‐based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18‐μm RF‐CMOS process with a supply voltage of 3.3 V. The measured gain, P_1dB, and efficiency at P_1dB are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25‐dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.     

一种新型提高射频功率放大器PAE的电路技术

提出了一种新型提高射频功率放大器功率附加效率(PAE)的电路技术,该方法通过滤除二次谐波分量、反射叠加三次谐波分量以提高电路PAE,分析了相位匹配的机制及其影响因素.基于该技术设计了一款功率放大器,仿真结果表明:工作频率为918 MHz时,该功放的P1dB达到了30.05 dBm,功率附加效率达到了58.75%,较普通...     

Analysis and design of high-power and efficient,millimeter-wave power amplifier systems using zero degree combiners

We present the analysis and design of high-power millimetre-wave power amplifier (PA) systems using zero-degree combiners (ZDCs). The methodology presented optimises the PA device sizing and the number of combined unit PAs based on device load pull simulations, driver power consumption analysis and loss analysis of the ZDC. Our analysis shows that an optimal number of N-way combined unit PAs leads to the highest power-added efficiency (PAE) for a given output power. To illustrate our design methodology, we designed a 1-W PA system at 45 GHz using a 45 nm silicon-on-insulator process and showed that an 8-way combined PA has the highest PAE that yields simulated output power of 30.6 dBm and 31% peak PAE.     

A 2.4 GHz high output power and high efficiency power amplifier operating at inductive breakdown in CMOS technology

In this paper, a novel CMOS power amplifier (PA) with high output power and power added efficiency is designed to operate in the avalanche region by increasing the supply voltage for the first time. With the X-parameter measurement based poly-harmonic distortion (PHD) behavioral model including the X^S and X^T terms, the simulation results can reveal accurate large signal characteristics of the whole PA at breakdown. The output power at 1-dB compression point of 30.2 dBm with 34.1% PAE at 2.4 GHz is obtained.     

A Highly Efficient and Linear Class-AB/F Power Amplifier for Multimode Operation

The class-AB/F power amplifier (PA), a multimode PA, which can operate at both class-AB and class-F modes, is analyzed and compared with the conventional class-F and class-AB PAs. The open-circuited third harmonic control circuit enhances the efficiency of the PA without deteriorating the linearity of class-AB mode of the PA. The voltage and current waveforms are simulated to evaluate the appropriate operation for the modes. To demonstrate the multimode PA, the PA is implemented using an InGaP/GaAs HBT process and it is tested with reverse-link IS-95A code division multiple access (CDMA) and PCS1900 global system for mobile communications signals in the personal communications service band. The class-AB operation for a CDMA signal delivers a power-added efficiency (PAE) of 38.9% and an adjacent channel power ratio of 49.5 and 56.5 dBc at the offset of 1.25 and 2.25 MHz, respectively, at the output power of 28 dBm. The maximum PAE of 64.7% under the class-F operation is measured at 32.5-dBm output power for a GSM signal. The class-AB/F PA is a good candidate for the multimode PA of next-generation wireless communication systems.     

A modified class-F power amplifier with miniaturized harmonic control circuit

In this paper, a modified class-F power-amplifier (PA) for GSM applications is designed, simulated and tested. In this design, novel symmetrical meandered lines compact microstrip resonant cell (SMLCMRC), is proposed as a new harmonics control circuit (HCC), which resulted in size compression, power added efficiency (PAE) enhancement, power gain improvement, and better linearization in the PA. In this work both of the conventional class-F amplifier and proposed amplifier with SMLCMRC is designed at 1.8 GHz. The measurements show that the proposed PA with SMLCMRC has 72.54% maximum PAE, 17.13 dB gain and the 1 dB compression point (P1dB) is about 35.1 dBm. These results show, 16.5% improvement in PAE, 1.33 dB increment in gain and 1.1 dB improvement in linearity operating range of proposed amplifier compared to the conventional PA.     

A High Gain 77 GHz Power Amplifier Operating at 0.7 V Based on 90 nm CMOS Technology

A 77 GHz 90 nm CMOS power amplifier (PA) demonstrates a gain of 17.4 dB and a saturated output power of 5.8 dBm at a low supply voltage of 0.7 V. To take care of hot-carrier injection degradation, the supply voltage is reduced from a standard voltage of 1.0 V. The saturated output power is increased to 9.4 dBm with a linear gain of 20.6 dB at 1.0 V operation. The amplifier consists of three-stage common-source nMOSFETs with gate widths of 40, 80, and 160 $mu{rm m}$. To our best knowledge, the developed PA shows the highest gain ever achieved for W-band CMOS amplifier. The measured temperature characteristics suggest that a simple compensation technique is possible by gate bias control.