混沌同步自保持特性在保密通信中的应用研究

给出了一种便于集成的改进型Chua电路，构造出一种具有一定鲁棒性、抗干扰等特性的驱动-响应式混沌同步系统，研究发现此混沌同步系统具有自保持特性，并给出研究结果。利用此特性，解决了目前如何同时在同一信道中传输混沌同步控制信号和密文信号的关键性问题，实验证明了此方法的可行性，为混沌在保密通信的实际应用奠定了基础。     

A General-Purpose Microprocessor-Based Control Circuit for a Three-Phase Controlled Rectifier Bridge

A novel general-purpose microprocessor-based control circuit for a three-phase controlled rectifier is presented. The performance exhibited by the controller is superior to previously presented circuits. The firing angle is smoothly controlled in the range of 0 to 180/s=deg/ with a fast response and a constant open loop gain, even for the cases where the converter is fed by a weak ac system of unregulated frequency. The synchronization between the line and VCO is implemented by an efficient software-controlled PLL. The effect of source impedance in delaying the synchronization signal has been properly compensated for by the-control circuit. The implementation of the compensation circuit is also presented. The hardware and software control circuit implementation built around an 8086 microprocessor is discussed, and the experimental results are given.     

GPS在双（多）基地高频地波雷达中的应用

针对双(多)基地高频地波雷达高精度同步问题，给出了一种利用GPS模块进行校频的时间同步方法。该方法采用FPGA器件，外同步源来自GPS接收信号，通过对FPGA内部设计的数字鉴相器输出的相差进行处理，并通过时间步长由小增大的方式调整恒温晶振的调谐电压，结果获得很高的频率同步精度。输出各信号的时间关系由软件设定，以计数方式产生，不但电路简单，调试修改方便，更重要的是使各信号问的时序关系准确、稳定、可靠，减少了雷达的相位误差。考虑到GPS接收机不能正常接收到信号的情况，FPGA内部的波形产生逻辑模块还进行了冗余设计，在GPS接收机不能正确接收到信号时，产生精度由时钟保证的同步信号，确保时间同步信号的连续性。文中还给出了利用ModelSim进行仿真的结果。理论分析和仿真结果说明了该文设计方案的可行性。     

Chaotic Communication Based on the Particle-in-a-Box Electronic Circuit

A secure communication system based on the error-feedback synchronization of the electronic model of the particle-in-a-box system is proposed. This circuit allows a robust and simple electronic emulation of the mechanical behavior of the collisions of a particle inside a box, exhibiting rich chaotic behavior. The required nonlinearity to emulate the box walls is implemented in a simple way when compared with other analog electronic chaotic circuits. A master/slave synchronization of two circuits exhibiting a rich chaotic behavior demonstrates the potentiality of this system to secure communication. In this system, binary data stream information modulates the bifurcation parameter of the particle-in-a-box electronic circuit in the transmitter. In the receiver circuit, this parameter is estimated using Pecora-Carroll synchronization and error-feedback synchronization. The performance of the demodulation process is verified through the eye pattern technique applied on the recovered bit stream. During the demodulation process, the error-feedback synchronization presented better performance compared with the Pecora-Carroll synchronization. The application of the particle-in-a-box electronic circuit in a secure communication system is demonstrated.     

一种单输入控制器下的忆阻混沌同步电路设计与实现

该文提出一种在单输入控制器下基于忆阻器的混沌同步模拟电路设计及其实现方法,并将它应用于基于忆阻混沌同步的保密通信.首先,基于混沌同步理论,构建了混沌同步系统及保密通信模型,并设计实现了一种4阶压控忆阻混沌电路和混沌加密解密电路.其次,将所设计的忆阻混沌电路作为混沌驱动和响应电路,根据它们的误差系统设计了一种单输入混沌同...     

A quasi-three-dimensional large-signal circuit model for lateral transient analysis of MOS device

A new quasi-three-dimensional large-signal circuit model of the metal-oxide-semiconductor capacitance (MOSC) under non-equilibrium depletion or inversion bias is presented. This model is based on the threedimensional version of Sah's distributed equivalent circuit model. A simple technique of scaling the circuit elements to account for circular symmetry is shown. The circuit elements perpendicular to the MOS interface are integrated to yield a quasi-three-dimensional circuit model. The numerical analysis technique of Green and Schewchun is then used to obtain photocurrent transient responses under arbitrary signal level. Theoretical photocurrent transient calculations are in excellent agreement with experimental curves, both for the fast initial transient as well as the slow long time decay.     

12.5 Gbps 1:16 DEMUX IC with high speed synchronizing circuits

A 12.5 Gbps 1:16 demultiplexer(DEMUX) integrated circuit is presented for multi-channel high-speed data transmission.A novel high-speed synchronizing technique is proposed and integrated in this DEMUX chip. Compared with conventional synchronizing techniques,the proposed method largely simplifies the system configuration. The experimental result demonstrates that the proposed circuit is effective in two-channel synchronization under a clock frequency of 12.5 GHz.The circuit is realized using 1μm GaAs heteroj unction bipolar transistor technology with die area of 2.3×2.3 mm~2.     

A synchronization technique for static delta-modulated PWMinverters

A synchronization technique for static delta-modulated PWM inverters is presented. This control strategy removes the frequency modulation inherent in the delta-modulated inverter. Furthermore, synchronization of the PWM pulses with the reference signal ensures balanced phase voltages in three-phase applications. The performance of the modulator is analyzed using digital simulations and is verified with experimental circuits     

Low-complexity space-time processor for DS-CDMA communications

A novel wideband beamforming technique for cellular CDMA systems is presented in this paper. The proposed algorithm asymptotically provides the maximum SINR estimate of the signal with the desired code (SDC) by optimally combining desired signals from different paths and canceling strong multiuser access interference (MUAI). A two-dimensional (2-D) matched filter structure is used where not only different temporal samples of the matched filter output are processed but where those from matched filters connected to different antennas are processed as well. In contrast to previously proposed techniques, an exact code synchronization for the SDC is not required. The algorithm presented herein asymptotically provides the arrival time of the multipaths within a bit period and the optimum beamformers for extracting each of them. Space-time filters for combining the fingers across both space and time while canceling the MUAIs are constructed correspondingly. The instrumental property exploited by this technique is the fact that although the respective spectra of the SDC and MUAI components at the matched filter output are statistically identical, the respective spectra of their squared values differ. A simplified RAKE structure-based receiver is also proposed. The 2-D RAKE receiver considerably decreases the computations but requires a coarse SDC code synchronization. A technique to achieve coarse SDC code synchronization is also proposed     

基于分段搜索的CMMB粗同步算法

传统CMMB粗同步算法采用硬件电路实现,环境适应性差且无法实现多标准兼容。针对此问题,提出一种分段搜索的CMMB粗同步算法,该算法在不损失同步性能的基础上,通过分段搜索时域同步信号的方法,大幅压缩了所需的数据存储器容量,适用于DSP实现。该方法也可应用于其他基于OFDM技术的通信系统中。     

MLC混沌电路耦合同步的充分条件

基于混合混沌信号的单向耦合方法,研究MLC(Murali-Lakshmanan-Chua)电路混沌同步问题;利用Bellman-Gronwall不等式,分析并给出MLC混沌电路耦合同步的一个充分条件。     

基于LEA-5T的快速高精度授时系统

为了进一步提高授时系统的精度和授时速度,采用新一代具有室内高精度授时技术的授时芯片LEA-5T作为标准时间基准源,设计了快速高精度授时系统.设计了系统的原理电路、详细阐述了原理电路的工作原理、介绍了私有协议UBX Protocol、时间码信息的提取及时间基准信号的确定方法,最后提供了样机图片以供读者参考.实践表明,该系统产生同步脉冲信号与秒基准信号的同步精度为0.6 μs,可满足同步精度小于1 μs的要求;首次授时速度快,热启动下小于4 s;信号敏感,在恶劣气候或只有一颗星可见时也可以实现授时.     

A new approach for a phase controlled self-oscillating mixer

The analytical and experimental demonstration of subharmonic synchronization and phase shifting of a push-pull self-oscillating mixer is presented for the first time. Inherent high mixing gain of the self-oscillating mixer circuit is exploited to generate a strong signal at the same frequency of the reference signal, which is related to the local oscillator's (LO) phase information. A phase error between this signal and the reference signal is extracted in a phase comparator before phase locking. Analytical modeling of frequency and phase stabilization of the push-pull self-oscillating mixer is presented, which is also experimentally verified for a self-oscillating mixer at 12 GHz. This self-oscillating mixer circuit demonstrates efficient phase locking, 0°-180° continuous phase shifting capability in addition to the reported large locking range (>10 MHz), low close-in to carrier phase noise (<7 dB degradation of a 6 GHz synthesized reference signal), and a high mixer conversion gain (>17 dB at 17 GHz). The demonstrated subharmonic phase locking approach replaces the need for a frequency multiplier or divider before the phase comparator. The synchronized push-pull self-oscillating mixer circuit is applicable to the millimeter-wave frequency distributed transmitters and receivers, where low-loss phase shifting and efficient subharmonic phase and frequency locking are hard to achieve     

Evaluation of a soft synchronization technique for DS/SS signals

Soft synchronization of direct-sequence spread-spectrum (DS/SS) signals introduces the capability of despreading with a continuously improving estimate of the spreading code. The soft synchronization technique presented and demonstrated in this paper exploits the eigenstructure of a frequency-channelized DS/SS signal to estimate the code. The estimate improves steadily as more data is collected, resulting in an improved estimate of the message signal. This allows commencement of despreading at an early stage when the code-estimate is still imperfect. Under infinite-time average assumptions a perfect code estimate can be obtained when the signal is received in arbitrary levels of white background noise. This paper demonstrates the synchronization performance of the technique through simulations under finite time-average conditions for environments with fading, multipath, and multi-user interference. The soft synchronization capability is demonstrated. Results show that the technique can remove frequency offsets on the received signal that are integer multiples of the code repeat rate, and that its performance is not degraded by multipath     

A novel communication strategy for decentralized control of paralleled multi-inverter systems

A new communication strategy for decentralized control of paralleled multi-inverter systems is introduced in this paper. The proposed strategy utilizes the common mode signal's circuit in the paralleled system as a channel of communication between individual inverters. Source voltage synchronization for paralleled inverters is presented to demonstrate its effectiveness. One inverter module acts as a source and a synchronized signal is sent by means of frequency modulation in this channel to all other modules via the common mode current. Each module will then receive and transform the signal to be used as a synchronized voltage command for individual inverters. The approach enables synchronization in the paralleled multi-inverter system and the method is not affected by external factors such as load change, output voltage variation, and different types of loads. The principle of operation, performance of the proposed strategy, as well as the experimental evaluation with three single-phase paralleled inverters are discussed and presented in this paper.     

一种用于高速QPSK解调的四次方环载波恢复电路

为解决高速QPSK信号全数字解调的技术瓶颈问题,采用模拟方案,研制了一种四次方环载波恢复电路,重点介绍了应用混频器上变频特性的宽带平方电路以及锁相环(PLL)载波提取电路的设计过程.测试结果表明,该载波恢复电路可以完成载频为720 MHz、码速率100 Mbit/s～1 Gbit/s范围的QPSK信号同步载波恢复,解决了高速信号相干解调中载波同步的关键技术问题.     

Simple square-rooting circuit using OTAs

A method to implement a square-rooting circuit is described. The proposed circuit employs operational transconductance amplifiers (OTAs) as the only active elements. The implementation technique is based on an electronically variable resistor formed by the OTA, where the magnitude of the resistance is controlled by the output current, to provide the square-rooting function. The proposed scheme can operate with both a voltage input and a current input signal. The purpose of the circuit is emphasised in terms of simple configuration, high accuracy and low cost. Experimental results showing the circuit performance are presented.     

用细胞神经网络超混沌同步系统实现保密通信

本文提出了一种基于细胞神经网络超混沌同步系统的双通道保密通信系统。用降维观测器思想实现了四阶细胞神经网络超混沌系统的高精度同步，并将其用于双通道混沌保密通信：一个通道传送与信息信号无关的混沌系统的输出信号实现高精度同步，另一个通道传送用混沌信号加密的信息信号。由于同步和加密信号分开传送并且采用了超混沌系统，所设计的保密通信系统具有更高的保密性。     

Improved auxiliary particle filter‐based synchronization of chaotic Colpitts circuit and its application to secure communication

In this paper, we propose a synchronization scheme based on an improved auxiliary particle filter (IAPF) for chaotic Colpitts circuit and conduct an experimental study on the synchronization performance with application to secure communications. Specifically, with the synchronization scheme, when the chaotic signals generated by an analog Colpitts circuit are transmitted through a nonideal channel, the distorted signals are processed digitally by the novelly designed IAPF at the receiver, in order to obtain the synchronized signals of the transmitter circuit. Experimental results indicate that synchronization can be achieved over both the additive white Gaussian noise channel and the multipath fading channel with low signal‐to‐noise ratio, even if there exist severe circuit parameter mismatches between the transmitter and the receiver. Furthermore, a chaos‐masking secure communication system is constructed and verified over both the additive white Gaussian noise channel and the multipath fading channel, and the bit error rate is evaluated versus different signal‐to‐noise ratios and symbol periods. It is shown that the achievable bit error rate can reach the order of magnitude of 10 ^{− 4} without error correction coding techniques. In addition, security analysis demonstrates that the proposed chaotic secure communication system is resistant to the brute‐force attack. Copyright © 2013 John Wiley & Sons, Ltd.